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1 | /* |
2 | * Copyright (C) 2006 Ben Skeggs. | |
3 | * | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining | |
7 | * a copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sublicense, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial | |
16 | * portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
19 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
21 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
22 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
23 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
24 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Authors: | |
30 | * Ben Skeggs <darktama@iinet.net.au> | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "nouveau_drm.h" | |
36 | #include "nouveau_drv.h" | |
37 | #include "nouveau_reg.h" | |
38 | #include <linux/ratelimit.h> | |
39 | ||
40 | /* needed for hotplug irq */ | |
41 | #include "nouveau_connector.h" | |
42 | #include "nv50_display.h" | |
43 | ||
44 | void | |
45 | nouveau_irq_preinstall(struct drm_device *dev) | |
46 | { | |
47 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
48 | ||
49 | /* Master disable */ | |
50 | nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); | |
51 | ||
52 | if (dev_priv->card_type == NV_50) { | |
53 | INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); | |
54 | INIT_LIST_HEAD(&dev_priv->vbl_waiting); | |
55 | } | |
56 | } | |
57 | ||
58 | int | |
59 | nouveau_irq_postinstall(struct drm_device *dev) | |
60 | { | |
61 | /* Master enable */ | |
62 | nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); | |
63 | return 0; | |
64 | } | |
65 | ||
66 | void | |
67 | nouveau_irq_uninstall(struct drm_device *dev) | |
68 | { | |
69 | /* Master disable */ | |
70 | nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); | |
71 | } | |
72 | ||
73 | static int | |
74 | nouveau_call_method(struct nouveau_channel *chan, int class, int mthd, int data) | |
75 | { | |
76 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
77 | struct nouveau_pgraph_object_method *grm; | |
78 | struct nouveau_pgraph_object_class *grc; | |
79 | ||
80 | grc = dev_priv->engine.graph.grclass; | |
81 | while (grc->id) { | |
82 | if (grc->id == class) | |
83 | break; | |
84 | grc++; | |
85 | } | |
86 | ||
87 | if (grc->id != class || !grc->methods) | |
88 | return -ENOENT; | |
89 | ||
90 | grm = grc->methods; | |
91 | while (grm->id) { | |
92 | if (grm->id == mthd) | |
93 | return grm->exec(chan, class, mthd, data); | |
94 | grm++; | |
95 | } | |
96 | ||
97 | return -ENOENT; | |
98 | } | |
99 | ||
100 | static bool | |
101 | nouveau_fifo_swmthd(struct nouveau_channel *chan, uint32_t addr, uint32_t data) | |
102 | { | |
103 | struct drm_device *dev = chan->dev; | |
104 | const int subc = (addr >> 13) & 0x7; | |
105 | const int mthd = addr & 0x1ffc; | |
106 | ||
107 | if (mthd == 0x0000) { | |
108 | struct nouveau_gpuobj_ref *ref = NULL; | |
109 | ||
110 | if (nouveau_gpuobj_ref_find(chan, data, &ref)) | |
111 | return false; | |
112 | ||
113 | if (ref->gpuobj->engine != NVOBJ_ENGINE_SW) | |
114 | return false; | |
115 | ||
116 | chan->sw_subchannel[subc] = ref->gpuobj->class; | |
117 | nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_rd32(dev, | |
118 | NV04_PFIFO_CACHE1_ENGINE) & ~(0xf << subc * 4)); | |
119 | return true; | |
120 | } | |
121 | ||
122 | /* hw object */ | |
123 | if (nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE) & (1 << (subc*4))) | |
124 | return false; | |
125 | ||
126 | if (nouveau_call_method(chan, chan->sw_subchannel[subc], mthd, data)) | |
127 | return false; | |
128 | ||
129 | return true; | |
130 | } | |
131 | ||
132 | static void | |
133 | nouveau_fifo_irq_handler(struct drm_device *dev) | |
134 | { | |
135 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
136 | struct nouveau_engine *engine = &dev_priv->engine; | |
137 | uint32_t status, reassign; | |
138 | int cnt = 0; | |
139 | ||
140 | reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1; | |
141 | while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { | |
142 | struct nouveau_channel *chan = NULL; | |
143 | uint32_t chid, get; | |
144 | ||
145 | nv_wr32(dev, NV03_PFIFO_CACHES, 0); | |
146 | ||
147 | chid = engine->fifo.channel_id(dev); | |
148 | if (chid >= 0 && chid < engine->fifo.channels) | |
149 | chan = dev_priv->fifos[chid]; | |
150 | get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET); | |
151 | ||
152 | if (status & NV_PFIFO_INTR_CACHE_ERROR) { | |
153 | uint32_t mthd, data; | |
154 | int ptr; | |
155 | ||
156 | /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before | |
157 | * wrapping on my G80 chips, but CACHE1 isn't big | |
158 | * enough for this much data.. Tests show that it | |
159 | * wraps around to the start at GET=0x800.. No clue | |
160 | * as to why.. | |
161 | */ | |
162 | ptr = (get & 0x7ff) >> 2; | |
163 | ||
164 | if (dev_priv->card_type < NV_40) { | |
165 | mthd = nv_rd32(dev, | |
166 | NV04_PFIFO_CACHE1_METHOD(ptr)); | |
167 | data = nv_rd32(dev, | |
168 | NV04_PFIFO_CACHE1_DATA(ptr)); | |
169 | } else { | |
170 | mthd = nv_rd32(dev, | |
171 | NV40_PFIFO_CACHE1_METHOD(ptr)); | |
172 | data = nv_rd32(dev, | |
173 | NV40_PFIFO_CACHE1_DATA(ptr)); | |
174 | } | |
175 | ||
176 | if (!chan || !nouveau_fifo_swmthd(chan, mthd, data)) { | |
177 | NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d " | |
178 | "Mthd 0x%04x Data 0x%08x\n", | |
179 | chid, (mthd >> 13) & 7, mthd & 0x1ffc, | |
180 | data); | |
181 | } | |
182 | ||
183 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0); | |
184 | nv_wr32(dev, NV03_PFIFO_INTR_0, | |
185 | NV_PFIFO_INTR_CACHE_ERROR); | |
186 | ||
187 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, | |
188 | nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1); | |
189 | nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4); | |
190 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, | |
191 | nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1); | |
192 | nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0); | |
193 | ||
194 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, | |
195 | nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); | |
196 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); | |
197 | ||
198 | status &= ~NV_PFIFO_INTR_CACHE_ERROR; | |
199 | } | |
200 | ||
201 | if (status & NV_PFIFO_INTR_DMA_PUSHER) { | |
202 | NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d\n", chid); | |
203 | ||
204 | status &= ~NV_PFIFO_INTR_DMA_PUSHER; | |
205 | nv_wr32(dev, NV03_PFIFO_INTR_0, | |
206 | NV_PFIFO_INTR_DMA_PUSHER); | |
207 | ||
208 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000); | |
209 | if (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT) != get) | |
210 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, | |
211 | get + 4); | |
212 | } | |
213 | ||
139295b6 FJ |
214 | if (status & NV_PFIFO_INTR_SEMAPHORE) { |
215 | uint32_t sem; | |
216 | ||
217 | status &= ~NV_PFIFO_INTR_SEMAPHORE; | |
218 | nv_wr32(dev, NV03_PFIFO_INTR_0, | |
219 | NV_PFIFO_INTR_SEMAPHORE); | |
220 | ||
221 | sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE); | |
222 | nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); | |
223 | ||
224 | nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4); | |
225 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); | |
226 | } | |
227 | ||
6ee73861 BS |
228 | if (status) { |
229 | NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n", | |
230 | status, chid); | |
231 | nv_wr32(dev, NV03_PFIFO_INTR_0, status); | |
232 | status = 0; | |
233 | } | |
234 | ||
235 | nv_wr32(dev, NV03_PFIFO_CACHES, reassign); | |
236 | } | |
237 | ||
238 | if (status) { | |
239 | NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt); | |
240 | nv_wr32(dev, 0x2140, 0); | |
241 | nv_wr32(dev, 0x140, 0); | |
242 | } | |
243 | ||
244 | nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING); | |
245 | } | |
246 | ||
247 | struct nouveau_bitfield_names { | |
248 | uint32_t mask; | |
249 | const char *name; | |
250 | }; | |
251 | ||
252 | static struct nouveau_bitfield_names nstatus_names[] = | |
253 | { | |
254 | { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, | |
255 | { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, | |
256 | { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, | |
257 | { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } | |
258 | }; | |
259 | ||
260 | static struct nouveau_bitfield_names nstatus_names_nv10[] = | |
261 | { | |
262 | { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, | |
263 | { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, | |
264 | { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, | |
265 | { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" } | |
266 | }; | |
267 | ||
268 | static struct nouveau_bitfield_names nsource_names[] = | |
269 | { | |
270 | { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, | |
271 | { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, | |
272 | { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, | |
273 | { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, | |
274 | { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, | |
275 | { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, | |
276 | { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, | |
277 | { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, | |
278 | { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, | |
279 | { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, | |
280 | { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, | |
281 | { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, | |
282 | { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, | |
283 | { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, | |
284 | { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, | |
285 | { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, | |
286 | { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, | |
287 | { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, | |
288 | { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, | |
289 | }; | |
290 | ||
291 | static void | |
292 | nouveau_print_bitfield_names_(uint32_t value, | |
293 | const struct nouveau_bitfield_names *namelist, | |
294 | const int namelist_len) | |
295 | { | |
296 | /* | |
297 | * Caller must have already printed the KERN_* log level for us. | |
298 | * Also the caller is responsible for adding the newline. | |
299 | */ | |
300 | int i; | |
301 | for (i = 0; i < namelist_len; ++i) { | |
302 | uint32_t mask = namelist[i].mask; | |
303 | if (value & mask) { | |
304 | printk(" %s", namelist[i].name); | |
305 | value &= ~mask; | |
306 | } | |
307 | } | |
308 | if (value) | |
309 | printk(" (unknown bits 0x%08x)", value); | |
310 | } | |
311 | #define nouveau_print_bitfield_names(val, namelist) \ | |
312 | nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist)) | |
313 | ||
314 | ||
315 | static int | |
316 | nouveau_graph_chid_from_grctx(struct drm_device *dev) | |
317 | { | |
318 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
319 | uint32_t inst; | |
320 | int i; | |
321 | ||
322 | if (dev_priv->card_type < NV_40) | |
323 | return dev_priv->engine.fifo.channels; | |
324 | else | |
325 | if (dev_priv->card_type < NV_50) { | |
326 | inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4; | |
327 | ||
328 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
329 | struct nouveau_channel *chan = dev_priv->fifos[i]; | |
330 | ||
331 | if (!chan || !chan->ramin_grctx) | |
332 | continue; | |
333 | ||
334 | if (inst == chan->ramin_grctx->instance) | |
335 | break; | |
336 | } | |
337 | } else { | |
338 | inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12; | |
339 | ||
340 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
341 | struct nouveau_channel *chan = dev_priv->fifos[i]; | |
342 | ||
343 | if (!chan || !chan->ramin) | |
344 | continue; | |
345 | ||
346 | if (inst == chan->ramin->instance) | |
347 | break; | |
348 | } | |
349 | } | |
350 | ||
351 | ||
352 | return i; | |
353 | } | |
354 | ||
355 | static int | |
356 | nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret) | |
357 | { | |
358 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
359 | struct nouveau_engine *engine = &dev_priv->engine; | |
360 | int channel; | |
361 | ||
362 | if (dev_priv->card_type < NV_10) | |
363 | channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf; | |
364 | else | |
365 | if (dev_priv->card_type < NV_40) | |
366 | channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; | |
367 | else | |
368 | channel = nouveau_graph_chid_from_grctx(dev); | |
369 | ||
370 | if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) { | |
371 | NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel); | |
372 | return -EINVAL; | |
373 | } | |
374 | ||
375 | *channel_ret = channel; | |
376 | return 0; | |
377 | } | |
378 | ||
379 | struct nouveau_pgraph_trap { | |
380 | int channel; | |
381 | int class; | |
382 | int subc, mthd, size; | |
383 | uint32_t data, data2; | |
384 | uint32_t nsource, nstatus; | |
385 | }; | |
386 | ||
387 | static void | |
388 | nouveau_graph_trap_info(struct drm_device *dev, | |
389 | struct nouveau_pgraph_trap *trap) | |
390 | { | |
391 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
392 | uint32_t address; | |
393 | ||
394 | trap->nsource = trap->nstatus = 0; | |
395 | if (dev_priv->card_type < NV_50) { | |
396 | trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); | |
397 | trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS); | |
398 | } | |
399 | ||
400 | if (nouveau_graph_trapped_channel(dev, &trap->channel)) | |
401 | trap->channel = -1; | |
402 | address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR); | |
403 | ||
404 | trap->mthd = address & 0x1FFC; | |
405 | trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA); | |
406 | if (dev_priv->card_type < NV_10) { | |
407 | trap->subc = (address >> 13) & 0x7; | |
408 | } else { | |
409 | trap->subc = (address >> 16) & 0x7; | |
410 | trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH); | |
411 | } | |
412 | ||
413 | if (dev_priv->card_type < NV_10) | |
414 | trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF; | |
415 | else if (dev_priv->card_type < NV_40) | |
416 | trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF; | |
417 | else if (dev_priv->card_type < NV_50) | |
418 | trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF; | |
419 | else | |
420 | trap->class = nv_rd32(dev, 0x400814); | |
421 | } | |
422 | ||
423 | static void | |
424 | nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id, | |
425 | struct nouveau_pgraph_trap *trap) | |
426 | { | |
427 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
428 | uint32_t nsource = trap->nsource, nstatus = trap->nstatus; | |
429 | ||
430 | NV_INFO(dev, "%s - nSource:", id); | |
431 | nouveau_print_bitfield_names(nsource, nsource_names); | |
432 | printk(", nStatus:"); | |
433 | if (dev_priv->card_type < NV_10) | |
434 | nouveau_print_bitfield_names(nstatus, nstatus_names); | |
435 | else | |
436 | nouveau_print_bitfield_names(nstatus, nstatus_names_nv10); | |
437 | printk("\n"); | |
438 | ||
439 | NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x " | |
440 | "Data 0x%08x:0x%08x\n", | |
441 | id, trap->channel, trap->subc, | |
442 | trap->class, trap->mthd, | |
443 | trap->data2, trap->data); | |
444 | } | |
445 | ||
446 | static int | |
447 | nouveau_pgraph_intr_swmthd(struct drm_device *dev, | |
448 | struct nouveau_pgraph_trap *trap) | |
449 | { | |
450 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
451 | ||
452 | if (trap->channel < 0 || | |
453 | trap->channel >= dev_priv->engine.fifo.channels || | |
454 | !dev_priv->fifos[trap->channel]) | |
455 | return -ENODEV; | |
456 | ||
457 | return nouveau_call_method(dev_priv->fifos[trap->channel], | |
458 | trap->class, trap->mthd, trap->data); | |
459 | } | |
460 | ||
461 | static inline void | |
462 | nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource) | |
463 | { | |
464 | struct nouveau_pgraph_trap trap; | |
465 | int unhandled = 0; | |
466 | ||
467 | nouveau_graph_trap_info(dev, &trap); | |
468 | ||
469 | if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { | |
470 | if (nouveau_pgraph_intr_swmthd(dev, &trap)) | |
471 | unhandled = 1; | |
472 | } else { | |
473 | unhandled = 1; | |
474 | } | |
475 | ||
476 | if (unhandled) | |
477 | nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap); | |
478 | } | |
479 | ||
480 | static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20); | |
481 | ||
482 | static int nouveau_ratelimit(void) | |
483 | { | |
484 | return __ratelimit(&nouveau_ratelimit_state); | |
485 | } | |
486 | ||
487 | ||
488 | static inline void | |
489 | nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource) | |
490 | { | |
491 | struct nouveau_pgraph_trap trap; | |
492 | int unhandled = 0; | |
493 | ||
494 | nouveau_graph_trap_info(dev, &trap); | |
495 | trap.nsource = nsource; | |
496 | ||
497 | if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { | |
498 | if (nouveau_pgraph_intr_swmthd(dev, &trap)) | |
499 | unhandled = 1; | |
d051bbb2 LB |
500 | } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { |
501 | uint32_t v = nv_rd32(dev, 0x402000); | |
502 | nv_wr32(dev, 0x402000, v); | |
503 | ||
504 | /* dump the error anyway for now: it's useful for | |
505 | Gallium development */ | |
506 | unhandled = 1; | |
6ee73861 BS |
507 | } else { |
508 | unhandled = 1; | |
509 | } | |
510 | ||
511 | if (unhandled && nouveau_ratelimit()) | |
512 | nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap); | |
513 | } | |
514 | ||
515 | static inline void | |
516 | nouveau_pgraph_intr_context_switch(struct drm_device *dev) | |
517 | { | |
518 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
519 | struct nouveau_engine *engine = &dev_priv->engine; | |
520 | uint32_t chid; | |
521 | ||
522 | chid = engine->fifo.channel_id(dev); | |
523 | NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid); | |
524 | ||
525 | switch (dev_priv->card_type) { | |
526 | case NV_04: | |
527 | nv04_graph_context_switch(dev); | |
528 | break; | |
529 | case NV_10: | |
530 | nv10_graph_context_switch(dev); | |
531 | break; | |
532 | default: | |
533 | NV_ERROR(dev, "Context switch not implemented\n"); | |
534 | break; | |
535 | } | |
536 | } | |
537 | ||
538 | static void | |
539 | nouveau_pgraph_irq_handler(struct drm_device *dev) | |
540 | { | |
541 | uint32_t status; | |
542 | ||
543 | while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) { | |
544 | uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); | |
545 | ||
546 | if (status & NV_PGRAPH_INTR_NOTIFY) { | |
547 | nouveau_pgraph_intr_notify(dev, nsource); | |
548 | ||
549 | status &= ~NV_PGRAPH_INTR_NOTIFY; | |
550 | nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY); | |
551 | } | |
552 | ||
553 | if (status & NV_PGRAPH_INTR_ERROR) { | |
554 | nouveau_pgraph_intr_error(dev, nsource); | |
555 | ||
556 | status &= ~NV_PGRAPH_INTR_ERROR; | |
557 | nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR); | |
558 | } | |
559 | ||
560 | if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { | |
561 | nouveau_pgraph_intr_context_switch(dev); | |
562 | ||
563 | status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; | |
564 | nv_wr32(dev, NV03_PGRAPH_INTR, | |
565 | NV_PGRAPH_INTR_CONTEXT_SWITCH); | |
566 | } | |
567 | ||
568 | if (status) { | |
569 | NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status); | |
570 | nv_wr32(dev, NV03_PGRAPH_INTR, status); | |
571 | } | |
572 | ||
573 | if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0) | |
574 | nv_wr32(dev, NV04_PGRAPH_FIFO, 1); | |
575 | } | |
576 | ||
577 | nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); | |
578 | } | |
579 | ||
580 | static void | |
581 | nv50_pgraph_irq_handler(struct drm_device *dev) | |
582 | { | |
b1d37aa0 | 583 | uint32_t status; |
6ee73861 | 584 | |
b1d37aa0 MM |
585 | while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) { |
586 | uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); | |
6ee73861 | 587 | |
b1d37aa0 MM |
588 | if (status & 0x00000001) { |
589 | nouveau_pgraph_intr_notify(dev, nsource); | |
590 | status &= ~0x00000001; | |
591 | nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); | |
592 | } | |
6ee73861 | 593 | |
b1d37aa0 MM |
594 | if (status & 0x00000010) { |
595 | nouveau_pgraph_intr_error(dev, nsource | | |
596 | NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); | |
6ee73861 | 597 | |
b1d37aa0 MM |
598 | status &= ~0x00000010; |
599 | nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); | |
600 | } | |
6ee73861 | 601 | |
b1d37aa0 MM |
602 | if (status & 0x00001000) { |
603 | nv_wr32(dev, 0x400500, 0x00000000); | |
604 | nv_wr32(dev, NV03_PGRAPH_INTR, | |
605 | NV_PGRAPH_INTR_CONTEXT_SWITCH); | |
606 | nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, | |
607 | NV40_PGRAPH_INTR_EN) & | |
608 | ~NV_PGRAPH_INTR_CONTEXT_SWITCH); | |
609 | nv_wr32(dev, 0x400500, 0x00010001); | |
6ee73861 | 610 | |
b1d37aa0 | 611 | nv50_graph_context_switch(dev); |
6ee73861 | 612 | |
b1d37aa0 MM |
613 | status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; |
614 | } | |
6ee73861 | 615 | |
b1d37aa0 MM |
616 | if (status & 0x00100000) { |
617 | nouveau_pgraph_intr_error(dev, nsource | | |
618 | NV03_PGRAPH_NSOURCE_DATA_ERROR); | |
6ee73861 | 619 | |
b1d37aa0 MM |
620 | status &= ~0x00100000; |
621 | nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); | |
622 | } | |
6ee73861 | 623 | |
b1d37aa0 MM |
624 | if (status & 0x00200000) { |
625 | int r; | |
626 | ||
627 | nouveau_pgraph_intr_error(dev, nsource | | |
628 | NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); | |
629 | ||
630 | NV_ERROR(dev, "magic set 1:\n"); | |
631 | for (r = 0x408900; r <= 0x408910; r += 4) | |
632 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
633 | nv_rd32(dev, r)); | |
634 | nv_wr32(dev, 0x408900, | |
635 | nv_rd32(dev, 0x408904) | 0xc0000000); | |
636 | for (r = 0x408e08; r <= 0x408e24; r += 4) | |
637 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
638 | nv_rd32(dev, r)); | |
639 | nv_wr32(dev, 0x408e08, | |
640 | nv_rd32(dev, 0x408e08) | 0xc0000000); | |
641 | ||
642 | NV_ERROR(dev, "magic set 2:\n"); | |
643 | for (r = 0x409900; r <= 0x409910; r += 4) | |
644 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
645 | nv_rd32(dev, r)); | |
646 | nv_wr32(dev, 0x409900, | |
647 | nv_rd32(dev, 0x409904) | 0xc0000000); | |
648 | for (r = 0x409e08; r <= 0x409e24; r += 4) | |
649 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
650 | nv_rd32(dev, r)); | |
651 | nv_wr32(dev, 0x409e08, | |
652 | nv_rd32(dev, 0x409e08) | 0xc0000000); | |
653 | ||
654 | status &= ~0x00200000; | |
655 | nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource); | |
656 | nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); | |
657 | } | |
6ee73861 | 658 | |
b1d37aa0 MM |
659 | if (status) { |
660 | NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", | |
661 | status); | |
662 | nv_wr32(dev, NV03_PGRAPH_INTR, status); | |
663 | } | |
6ee73861 | 664 | |
b1d37aa0 MM |
665 | { |
666 | const int isb = (1 << 16) | (1 << 0); | |
6ee73861 | 667 | |
b1d37aa0 MM |
668 | if ((nv_rd32(dev, 0x400500) & isb) != isb) |
669 | nv_wr32(dev, 0x400500, | |
670 | nv_rd32(dev, 0x400500) | isb); | |
671 | } | |
6ee73861 BS |
672 | } |
673 | ||
674 | nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); | |
b1d37aa0 | 675 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); |
6ee73861 BS |
676 | } |
677 | ||
678 | static void | |
679 | nouveau_crtc_irq_handler(struct drm_device *dev, int crtc) | |
680 | { | |
681 | if (crtc & 1) | |
682 | nv_wr32(dev, NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); | |
683 | ||
684 | if (crtc & 2) | |
685 | nv_wr32(dev, NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK); | |
686 | } | |
687 | ||
688 | irqreturn_t | |
689 | nouveau_irq_handler(DRM_IRQ_ARGS) | |
690 | { | |
691 | struct drm_device *dev = (struct drm_device *)arg; | |
692 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
693 | uint32_t status, fbdev_flags = 0; | |
694 | ||
695 | status = nv_rd32(dev, NV03_PMC_INTR_0); | |
696 | if (!status) | |
697 | return IRQ_NONE; | |
698 | ||
699 | if (dev_priv->fbdev_info) { | |
700 | fbdev_flags = dev_priv->fbdev_info->flags; | |
701 | dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED; | |
702 | } | |
703 | ||
704 | if (status & NV_PMC_INTR_0_PFIFO_PENDING) { | |
705 | nouveau_fifo_irq_handler(dev); | |
706 | status &= ~NV_PMC_INTR_0_PFIFO_PENDING; | |
707 | } | |
708 | ||
709 | if (status & NV_PMC_INTR_0_PGRAPH_PENDING) { | |
710 | if (dev_priv->card_type >= NV_50) | |
711 | nv50_pgraph_irq_handler(dev); | |
712 | else | |
713 | nouveau_pgraph_irq_handler(dev); | |
714 | ||
715 | status &= ~NV_PMC_INTR_0_PGRAPH_PENDING; | |
716 | } | |
717 | ||
718 | if (status & NV_PMC_INTR_0_CRTCn_PENDING) { | |
719 | nouveau_crtc_irq_handler(dev, (status>>24)&3); | |
720 | status &= ~NV_PMC_INTR_0_CRTCn_PENDING; | |
721 | } | |
722 | ||
723 | if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING | | |
724 | NV_PMC_INTR_0_NV50_I2C_PENDING)) { | |
725 | nv50_display_irq_handler(dev); | |
726 | status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING | | |
727 | NV_PMC_INTR_0_NV50_I2C_PENDING); | |
728 | } | |
729 | ||
730 | if (status) | |
731 | NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status); | |
732 | ||
733 | if (dev_priv->fbdev_info) | |
734 | dev_priv->fbdev_info->flags = fbdev_flags; | |
735 | ||
736 | return IRQ_HANDLED; | |
737 | } |