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6ee73861 BS |
1 | /* |
2 | * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. | |
3 | * Copyright 2005 Stephane Marchesin | |
4 | * | |
5 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
6 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
7 | * This notice must be preserved. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a | |
10 | * copy of this software and associated documentation files (the "Software"), | |
11 | * to deal in the Software without restriction, including without limitation | |
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
13 | * and/or sell copies of the Software, and to permit persons to whom the | |
14 | * Software is furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the next | |
17 | * paragraph) shall be included in all copies or substantial portions of the | |
18 | * Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "drm_sarea.h" | |
36 | #include "nouveau_drv.h" | |
37 | ||
a845fff8 RS |
38 | #define MIN(a,b) a < b ? a : b |
39 | ||
a0af9add FJ |
40 | /* |
41 | * NV10-NV40 tiling helpers | |
42 | */ | |
43 | ||
44 | static void | |
45 | nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, | |
46 | uint32_t size, uint32_t pitch) | |
47 | { | |
48 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
49 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | |
50 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
51 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
9f56b126 | 52 | struct nouveau_tile_reg *tile = &dev_priv->tile[i]; |
a0af9add FJ |
53 | |
54 | tile->addr = addr; | |
55 | tile->size = size; | |
56 | tile->used = !!pitch; | |
57 | nouveau_fence_unref((void **)&tile->fence); | |
58 | ||
a0af9add | 59 | pfifo->reassign(dev, false); |
a0af9add FJ |
60 | pfifo->cache_pull(dev, false); |
61 | ||
62 | nouveau_wait_for_idle(dev); | |
63 | ||
64 | pgraph->set_region_tiling(dev, i, addr, size, pitch); | |
65 | pfb->set_region_tiling(dev, i, addr, size, pitch); | |
66 | ||
67 | pfifo->cache_pull(dev, true); | |
68 | pfifo->reassign(dev, true); | |
69 | } | |
70 | ||
71 | struct nouveau_tile_reg * | |
72 | nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, | |
73 | uint32_t pitch) | |
74 | { | |
75 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
76 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
9f56b126 FJ |
77 | struct nouveau_tile_reg *found = NULL; |
78 | unsigned long i, flags; | |
a0af9add | 79 | |
9f56b126 | 80 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
a0af9add FJ |
81 | |
82 | for (i = 0; i < pfb->num_tiles; i++) { | |
9f56b126 FJ |
83 | struct nouveau_tile_reg *tile = &dev_priv->tile[i]; |
84 | ||
85 | if (tile->used) | |
a0af9add FJ |
86 | /* Tile region in use. */ |
87 | continue; | |
88 | ||
9f56b126 FJ |
89 | if (tile->fence && |
90 | !nouveau_fence_signalled(tile->fence, NULL)) | |
a0af9add FJ |
91 | /* Pending tile region. */ |
92 | continue; | |
93 | ||
9f56b126 FJ |
94 | if (max(tile->addr, addr) < |
95 | min(tile->addr + tile->size, addr + size)) | |
a0af9add FJ |
96 | /* Kill an intersecting tile region. */ |
97 | nv10_mem_set_region_tiling(dev, i, 0, 0, 0); | |
98 | ||
99 | if (pitch && !found) { | |
100 | /* Free tile region. */ | |
101 | nv10_mem_set_region_tiling(dev, i, addr, size, pitch); | |
9f56b126 | 102 | found = tile; |
a0af9add FJ |
103 | } |
104 | } | |
105 | ||
9f56b126 | 106 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
a0af9add FJ |
107 | |
108 | return found; | |
109 | } | |
110 | ||
111 | void | |
112 | nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile, | |
113 | struct nouveau_fence *fence) | |
114 | { | |
115 | if (fence) { | |
116 | /* Mark it as pending. */ | |
117 | tile->fence = fence; | |
118 | nouveau_fence_ref(fence); | |
119 | } | |
120 | ||
121 | tile->used = false; | |
122 | } | |
123 | ||
6ee73861 BS |
124 | /* |
125 | * NV50 VM helpers | |
126 | */ | |
127 | int | |
128 | nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, | |
129 | uint32_t flags, uint64_t phys) | |
130 | { | |
131 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
531e7713 BS |
132 | struct nouveau_gpuobj *pgt; |
133 | unsigned block; | |
134 | int i; | |
6ee73861 | 135 | |
531e7713 BS |
136 | virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1; |
137 | size = (size >> 16) << 1; | |
6c429667 BS |
138 | |
139 | phys |= ((uint64_t)flags << 32); | |
140 | phys |= 1; | |
141 | if (dev_priv->vram_sys_base) { | |
142 | phys += dev_priv->vram_sys_base; | |
143 | phys |= 0x30; | |
144 | } | |
6ee73861 | 145 | |
531e7713 BS |
146 | while (size) { |
147 | unsigned offset_h = upper_32_bits(phys); | |
4c27bd33 | 148 | unsigned offset_l = lower_32_bits(phys); |
531e7713 BS |
149 | unsigned pte, end; |
150 | ||
151 | for (i = 7; i >= 0; i--) { | |
152 | block = 1 << (i + 1); | |
153 | if (size >= block && !(virt & (block - 1))) | |
154 | break; | |
155 | } | |
156 | offset_l |= (i << 7); | |
6ee73861 | 157 | |
531e7713 BS |
158 | phys += block << 15; |
159 | size -= block; | |
6ee73861 | 160 | |
531e7713 BS |
161 | while (block) { |
162 | pgt = dev_priv->vm_vram_pt[virt >> 14]; | |
163 | pte = virt & 0x3ffe; | |
164 | ||
165 | end = pte + block; | |
166 | if (end > 16384) | |
167 | end = 16384; | |
168 | block -= (end - pte); | |
169 | virt += (end - pte); | |
170 | ||
171 | while (pte < end) { | |
b3beb167 BS |
172 | nv_wo32(pgt, (pte * 4) + 0, offset_l); |
173 | nv_wo32(pgt, (pte * 4) + 4, offset_h); | |
174 | pte += 2; | |
531e7713 BS |
175 | } |
176 | } | |
6ee73861 | 177 | } |
f56cb86f | 178 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 179 | |
63187215 BS |
180 | nv50_vm_flush(dev, 5); |
181 | nv50_vm_flush(dev, 0); | |
182 | nv50_vm_flush(dev, 4); | |
183 | nv50_vm_flush(dev, 6); | |
6ee73861 BS |
184 | return 0; |
185 | } | |
186 | ||
187 | void | |
188 | nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) | |
189 | { | |
4c27bd33 BS |
190 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
191 | struct nouveau_gpuobj *pgt; | |
192 | unsigned pages, pte, end; | |
193 | ||
194 | virt -= dev_priv->vm_vram_base; | |
195 | pages = (size >> 16) << 1; | |
196 | ||
4c27bd33 BS |
197 | while (pages) { |
198 | pgt = dev_priv->vm_vram_pt[virt >> 29]; | |
199 | pte = (virt & 0x1ffe0000ULL) >> 15; | |
200 | ||
201 | end = pte + pages; | |
202 | if (end > 16384) | |
203 | end = 16384; | |
204 | pages -= (end - pte); | |
205 | virt += (end - pte) << 15; | |
206 | ||
b3beb167 BS |
207 | while (pte < end) { |
208 | nv_wo32(pgt, (pte * 4), 0); | |
209 | pte++; | |
210 | } | |
4c27bd33 | 211 | } |
f56cb86f | 212 | dev_priv->engine.instmem.flush(dev); |
4c27bd33 | 213 | |
63187215 BS |
214 | nv50_vm_flush(dev, 5); |
215 | nv50_vm_flush(dev, 0); | |
216 | nv50_vm_flush(dev, 4); | |
217 | nv50_vm_flush(dev, 6); | |
6ee73861 BS |
218 | } |
219 | ||
220 | /* | |
221 | * Cleanup everything | |
222 | */ | |
b833ac26 | 223 | void |
fbd2895e | 224 | nouveau_mem_vram_fini(struct drm_device *dev) |
6ee73861 BS |
225 | { |
226 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
227 | ||
ac8fb975 BS |
228 | nouveau_bo_unpin(dev_priv->vga_ram); |
229 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
230 | ||
6ee73861 BS |
231 | ttm_bo_device_release(&dev_priv->ttm.bdev); |
232 | ||
233 | nouveau_ttm_global_release(dev_priv); | |
234 | ||
fbd2895e BS |
235 | if (dev_priv->fb_mtrr >= 0) { |
236 | drm_mtrr_del(dev_priv->fb_mtrr, | |
237 | pci_resource_start(dev->pdev, 1), | |
238 | pci_resource_len(dev->pdev, 1), DRM_MTRR_WC); | |
239 | dev_priv->fb_mtrr = -1; | |
240 | } | |
241 | } | |
242 | ||
243 | void | |
244 | nouveau_mem_gart_fini(struct drm_device *dev) | |
245 | { | |
246 | nouveau_sgdma_takedown(dev); | |
247 | ||
cd0b072f | 248 | if (drm_core_has_AGP(dev) && dev->agp) { |
6ee73861 BS |
249 | struct drm_agp_mem *entry, *tempe; |
250 | ||
251 | /* Remove AGP resources, but leave dev->agp | |
252 | intact until drv_cleanup is called. */ | |
253 | list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) { | |
254 | if (entry->bound) | |
255 | drm_unbind_agp(entry->memory); | |
256 | drm_free_agp(entry->memory, entry->pages); | |
257 | kfree(entry); | |
258 | } | |
259 | INIT_LIST_HEAD(&dev->agp->memory); | |
260 | ||
261 | if (dev->agp->acquired) | |
262 | drm_agp_release(dev); | |
263 | ||
264 | dev->agp->acquired = 0; | |
265 | dev->agp->enabled = 0; | |
266 | } | |
6ee73861 BS |
267 | } |
268 | ||
6ee73861 | 269 | static uint32_t |
a76fb4e8 BS |
270 | nouveau_mem_detect_nv04(struct drm_device *dev) |
271 | { | |
3c7066bc | 272 | uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0); |
a76fb4e8 BS |
273 | |
274 | if (boot0 & 0x00000100) | |
275 | return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; | |
276 | ||
3c7066bc FJ |
277 | switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { |
278 | case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: | |
a76fb4e8 | 279 | return 32 * 1024 * 1024; |
3c7066bc | 280 | case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: |
a76fb4e8 | 281 | return 16 * 1024 * 1024; |
3c7066bc | 282 | case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: |
a76fb4e8 | 283 | return 8 * 1024 * 1024; |
3c7066bc | 284 | case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: |
a76fb4e8 BS |
285 | return 4 * 1024 * 1024; |
286 | } | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static uint32_t | |
292 | nouveau_mem_detect_nforce(struct drm_device *dev) | |
6ee73861 BS |
293 | { |
294 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
295 | struct pci_dev *bridge; | |
296 | uint32_t mem; | |
297 | ||
298 | bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); | |
299 | if (!bridge) { | |
300 | NV_ERROR(dev, "no bridge device\n"); | |
301 | return 0; | |
302 | } | |
303 | ||
a76fb4e8 | 304 | if (dev_priv->flags & NV_NFORCE) { |
6ee73861 BS |
305 | pci_read_config_dword(bridge, 0x7C, &mem); |
306 | return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; | |
307 | } else | |
a76fb4e8 | 308 | if (dev_priv->flags & NV_NFORCE2) { |
6ee73861 BS |
309 | pci_read_config_dword(bridge, 0x84, &mem); |
310 | return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; | |
311 | } | |
312 | ||
313 | NV_ERROR(dev, "impossible!\n"); | |
314 | return 0; | |
315 | } | |
316 | ||
6c3d7ef2 BS |
317 | static void |
318 | nv50_vram_preinit(struct drm_device *dev) | |
319 | { | |
320 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
321 | int i, parts, colbits, rowbitsa, rowbitsb, banks; | |
322 | u64 rowsize, predicted; | |
323 | u32 r0, r4, rt, ru; | |
324 | ||
325 | r0 = nv_rd32(dev, 0x100200); | |
326 | r4 = nv_rd32(dev, 0x100204); | |
327 | rt = nv_rd32(dev, 0x100250); | |
328 | ru = nv_rd32(dev, 0x001540); | |
329 | NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru); | |
330 | ||
331 | for (i = 0, parts = 0; i < 8; i++) { | |
332 | if (ru & (0x00010000 << i)) | |
333 | parts++; | |
334 | } | |
335 | ||
336 | colbits = (r4 & 0x0000f000) >> 12; | |
337 | rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; | |
338 | rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; | |
339 | banks = ((r4 & 0x01000000) ? 8 : 4); | |
340 | ||
341 | rowsize = parts * banks * (1 << colbits) * 8; | |
342 | predicted = rowsize << rowbitsa; | |
343 | if (r0 & 0x00000004) | |
344 | predicted += rowsize << rowbitsb; | |
345 | ||
346 | if (predicted != dev_priv->vram_size) { | |
347 | NV_WARN(dev, "memory controller reports %dMiB VRAM\n", | |
348 | (u32)(dev_priv->vram_size >> 20)); | |
349 | NV_WARN(dev, "we calculated %dMiB VRAM\n", | |
350 | (u32)(predicted >> 20)); | |
351 | } | |
352 | ||
353 | dev_priv->vram_rblock_size = rowsize >> 12; | |
354 | if (rt & 1) | |
355 | dev_priv->vram_rblock_size *= 3; | |
356 | ||
357 | NV_DEBUG(dev, "rblock %lld bytes\n", | |
358 | (u64)dev_priv->vram_rblock_size << 12); | |
359 | } | |
360 | ||
361 | static void | |
362 | nvaa_vram_preinit(struct drm_device *dev) | |
363 | { | |
364 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
365 | ||
366 | /* To our knowledge, there's no large scale reordering of pages | |
367 | * that occurs on IGP chipsets. | |
368 | */ | |
369 | dev_priv->vram_rblock_size = 1; | |
370 | } | |
371 | ||
fbd2895e | 372 | static int |
a76fb4e8 | 373 | nouveau_mem_detect(struct drm_device *dev) |
6ee73861 BS |
374 | { |
375 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a76fb4e8 BS |
376 | |
377 | if (dev_priv->card_type == NV_04) { | |
378 | dev_priv->vram_size = nouveau_mem_detect_nv04(dev); | |
379 | } else | |
380 | if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { | |
381 | dev_priv->vram_size = nouveau_mem_detect_nforce(dev); | |
7a2e4e03 BS |
382 | } else |
383 | if (dev_priv->card_type < NV_50) { | |
3c7066bc FJ |
384 | dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
385 | dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; | |
c556d989 BS |
386 | } else |
387 | if (dev_priv->card_type < NV_C0) { | |
3c7066bc | 388 | dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
7a2e4e03 | 389 | dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; |
6e86e041 | 390 | dev_priv->vram_size &= 0xffffffff00ll; |
6c3d7ef2 BS |
391 | |
392 | switch (dev_priv->chipset) { | |
393 | case 0xaa: | |
394 | case 0xac: | |
395 | case 0xaf: | |
8b281db5 BS |
396 | dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10); |
397 | dev_priv->vram_sys_base <<= 12; | |
6c3d7ef2 BS |
398 | nvaa_vram_preinit(dev); |
399 | break; | |
400 | default: | |
401 | nv50_vram_preinit(dev); | |
402 | break; | |
fb4f5621 | 403 | } |
c556d989 BS |
404 | } else { |
405 | dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20; | |
406 | dev_priv->vram_size *= nv_rd32(dev, 0x121c74); | |
6ee73861 BS |
407 | } |
408 | ||
a76fb4e8 BS |
409 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); |
410 | if (dev_priv->vram_sys_base) { | |
411 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", | |
412 | dev_priv->vram_sys_base); | |
413 | } | |
414 | ||
415 | if (dev_priv->vram_size) | |
416 | return 0; | |
417 | return -ENOMEM; | |
6ee73861 BS |
418 | } |
419 | ||
71d06186 FJ |
420 | #if __OS_HAS_AGP |
421 | static unsigned long | |
422 | get_agp_mode(struct drm_device *dev, unsigned long mode) | |
423 | { | |
424 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
425 | ||
426 | /* | |
427 | * FW seems to be broken on nv18, it makes the card lock up | |
428 | * randomly. | |
429 | */ | |
430 | if (dev_priv->chipset == 0x18) | |
431 | mode &= ~PCI_AGP_COMMAND_FW; | |
432 | ||
de5899bd FJ |
433 | /* |
434 | * AGP mode set in the command line. | |
435 | */ | |
436 | if (nouveau_agpmode > 0) { | |
437 | bool agpv3 = mode & 0x8; | |
438 | int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode; | |
439 | ||
440 | mode = (mode & ~0x7) | (rate & 0x7); | |
441 | } | |
442 | ||
71d06186 FJ |
443 | return mode; |
444 | } | |
445 | #endif | |
446 | ||
e04d8e82 FJ |
447 | int |
448 | nouveau_mem_reset_agp(struct drm_device *dev) | |
6ee73861 | 449 | { |
e04d8e82 FJ |
450 | #if __OS_HAS_AGP |
451 | uint32_t saved_pci_nv_1, pmc_enable; | |
452 | int ret; | |
453 | ||
454 | /* First of all, disable fast writes, otherwise if it's | |
455 | * already enabled in the AGP bridge and we disable the card's | |
456 | * AGP controller we might be locking ourselves out of it. */ | |
316f60a1 FJ |
457 | if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) | |
458 | dev->agp->mode) & PCI_AGP_COMMAND_FW) { | |
e04d8e82 FJ |
459 | struct drm_agp_info info; |
460 | struct drm_agp_mode mode; | |
461 | ||
462 | ret = drm_agp_info(dev, &info); | |
463 | if (ret) | |
464 | return ret; | |
465 | ||
71d06186 | 466 | mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW; |
e04d8e82 FJ |
467 | ret = drm_agp_enable(dev, mode); |
468 | if (ret) | |
469 | return ret; | |
470 | } | |
6ee73861 BS |
471 | |
472 | saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1); | |
6ee73861 BS |
473 | |
474 | /* clear busmaster bit */ | |
475 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); | |
e04d8e82 FJ |
476 | /* disable AGP */ |
477 | nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0); | |
6ee73861 BS |
478 | |
479 | /* power cycle pgraph, if enabled */ | |
480 | pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); | |
481 | if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { | |
482 | nv_wr32(dev, NV03_PMC_ENABLE, | |
483 | pmc_enable & ~NV_PMC_ENABLE_PGRAPH); | |
484 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | | |
485 | NV_PMC_ENABLE_PGRAPH); | |
486 | } | |
487 | ||
488 | /* and restore (gives effect of resetting AGP) */ | |
6ee73861 | 489 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); |
b694dfb2 | 490 | #endif |
6ee73861 | 491 | |
e04d8e82 FJ |
492 | return 0; |
493 | } | |
494 | ||
6ee73861 BS |
495 | int |
496 | nouveau_mem_init_agp(struct drm_device *dev) | |
497 | { | |
b694dfb2 | 498 | #if __OS_HAS_AGP |
6ee73861 BS |
499 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
500 | struct drm_agp_info info; | |
501 | struct drm_agp_mode mode; | |
502 | int ret; | |
503 | ||
6ee73861 BS |
504 | if (!dev->agp->acquired) { |
505 | ret = drm_agp_acquire(dev); | |
506 | if (ret) { | |
507 | NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); | |
508 | return ret; | |
509 | } | |
510 | } | |
511 | ||
2b495268 FJ |
512 | nouveau_mem_reset_agp(dev); |
513 | ||
6ee73861 BS |
514 | ret = drm_agp_info(dev, &info); |
515 | if (ret) { | |
516 | NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); | |
517 | return ret; | |
518 | } | |
519 | ||
520 | /* see agp.h for the AGPSTAT_* modes available */ | |
71d06186 | 521 | mode.mode = get_agp_mode(dev, info.mode); |
6ee73861 BS |
522 | ret = drm_agp_enable(dev, mode); |
523 | if (ret) { | |
524 | NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); | |
525 | return ret; | |
526 | } | |
527 | ||
528 | dev_priv->gart_info.type = NOUVEAU_GART_AGP; | |
529 | dev_priv->gart_info.aper_base = info.aperture_base; | |
530 | dev_priv->gart_info.aper_size = info.aperture_size; | |
b694dfb2 | 531 | #endif |
6ee73861 BS |
532 | return 0; |
533 | } | |
534 | ||
535 | int | |
fbd2895e | 536 | nouveau_mem_vram_init(struct drm_device *dev) |
6ee73861 BS |
537 | { |
538 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
539 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
fbd2895e | 540 | int ret, dma_bits; |
6ee73861 BS |
541 | |
542 | if (dev_priv->card_type >= NV_50 && | |
543 | pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) | |
544 | dma_bits = 40; | |
fbd2895e BS |
545 | else |
546 | dma_bits = 32; | |
6ee73861 BS |
547 | |
548 | ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); | |
fbd2895e | 549 | if (ret) |
6ee73861 | 550 | return ret; |
fbd2895e BS |
551 | |
552 | ret = nouveau_mem_detect(dev); | |
553 | if (ret) | |
554 | return ret; | |
555 | ||
556 | dev_priv->fb_phys = pci_resource_start(dev->pdev, 1); | |
6ee73861 BS |
557 | |
558 | ret = nouveau_ttm_global_init(dev_priv); | |
559 | if (ret) | |
560 | return ret; | |
561 | ||
562 | ret = ttm_bo_device_init(&dev_priv->ttm.bdev, | |
563 | dev_priv->ttm.bo_global_ref.ref.object, | |
564 | &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, | |
565 | dma_bits <= 32 ? true : false); | |
566 | if (ret) { | |
567 | NV_ERROR(dev, "Error initialising bo driver: %d\n", ret); | |
568 | return ret; | |
569 | } | |
570 | ||
a76fb4e8 | 571 | dev_priv->fb_available_size = dev_priv->vram_size; |
6ee73861 | 572 | dev_priv->fb_mappable_pages = dev_priv->fb_available_size; |
01d73a69 JC |
573 | if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1)) |
574 | dev_priv->fb_mappable_pages = | |
575 | pci_resource_len(dev->pdev, 1); | |
6ee73861 BS |
576 | dev_priv->fb_mappable_pages >>= PAGE_SHIFT; |
577 | ||
fbd2895e BS |
578 | /* reserve space at end of VRAM for PRAMIN */ |
579 | if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 || | |
580 | dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) | |
581 | dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024); | |
582 | else | |
583 | if (dev_priv->card_type >= NV_40) | |
584 | dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024); | |
585 | else | |
586 | dev_priv->ramin_rsvd_vram = (512 * 1024); | |
587 | ||
6ee73861 BS |
588 | dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; |
589 | dev_priv->fb_aper_free = dev_priv->fb_available_size; | |
590 | ||
591 | /* mappable vram */ | |
592 | ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM, | |
593 | dev_priv->fb_available_size >> PAGE_SHIFT); | |
594 | if (ret) { | |
595 | NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret); | |
596 | return ret; | |
597 | } | |
598 | ||
ac8fb975 BS |
599 | ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM, |
600 | 0, 0, true, true, &dev_priv->vga_ram); | |
601 | if (ret == 0) | |
602 | ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM); | |
603 | if (ret) { | |
604 | NV_WARN(dev, "failed to reserve VGA memory\n"); | |
605 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
606 | } | |
607 | ||
fbd2895e BS |
608 | dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1), |
609 | pci_resource_len(dev->pdev, 1), | |
610 | DRM_MTRR_WC); | |
611 | return 0; | |
612 | } | |
613 | ||
614 | int | |
615 | nouveau_mem_gart_init(struct drm_device *dev) | |
616 | { | |
617 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
618 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
619 | int ret; | |
620 | ||
621 | dev_priv->gart_info.type = NOUVEAU_GART_NONE; | |
622 | ||
6ee73861 | 623 | #if !defined(__powerpc__) && !defined(__ia64__) |
de5899bd | 624 | if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) { |
6ee73861 BS |
625 | ret = nouveau_mem_init_agp(dev); |
626 | if (ret) | |
627 | NV_ERROR(dev, "Error initialising AGP: %d\n", ret); | |
628 | } | |
629 | #endif | |
630 | ||
631 | if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { | |
632 | ret = nouveau_sgdma_init(dev); | |
633 | if (ret) { | |
634 | NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret); | |
635 | return ret; | |
636 | } | |
637 | } | |
638 | ||
639 | NV_INFO(dev, "%d MiB GART (aperture)\n", | |
640 | (int)(dev_priv->gart_info.aper_size >> 20)); | |
641 | dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size; | |
642 | ||
643 | ret = ttm_bo_init_mm(bdev, TTM_PL_TT, | |
644 | dev_priv->gart_info.aper_size >> PAGE_SHIFT); | |
645 | if (ret) { | |
646 | NV_ERROR(dev, "Failed TT mm init: %d\n", ret); | |
647 | return ret; | |
648 | } | |
649 | ||
6ee73861 BS |
650 | return 0; |
651 | } | |
652 | ||
7760fcb0 RS |
653 | void |
654 | nouveau_mem_timing_init(struct drm_device *dev) | |
655 | { | |
656 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
657 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | |
658 | struct nouveau_pm_memtimings *memtimings = &pm->memtimings; | |
659 | struct nvbios *bios = &dev_priv->vbios; | |
660 | struct bit_entry P; | |
661 | u8 tUNK_0, tUNK_1, tUNK_2; | |
662 | u8 tRP; /* Byte 3 */ | |
663 | u8 tRAS; /* Byte 5 */ | |
664 | u8 tRFC; /* Byte 7 */ | |
665 | u8 tRC; /* Byte 9 */ | |
666 | u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; | |
667 | u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; | |
668 | u8 *mem = NULL, *entry; | |
669 | int i, recordlen, entries; | |
670 | ||
671 | if (bios->type == NVBIOS_BIT) { | |
672 | if (bit_table(dev, 'P', &P)) | |
673 | return; | |
674 | ||
675 | if (P.version == 1) | |
676 | mem = ROMPTR(bios, P.data[4]); | |
677 | else | |
678 | if (P.version == 2) | |
679 | mem = ROMPTR(bios, P.data[8]); | |
680 | else { | |
681 | NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); | |
682 | } | |
683 | } else { | |
684 | NV_DEBUG(dev, "BMP version too old for memory\n"); | |
685 | return; | |
686 | } | |
687 | ||
688 | if (!mem) { | |
689 | NV_DEBUG(dev, "memory timing table pointer invalid\n"); | |
690 | return; | |
691 | } | |
692 | ||
693 | if (mem[0] != 0x10) { | |
694 | NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]); | |
695 | return; | |
696 | } | |
697 | ||
698 | /* validate record length */ | |
699 | entries = mem[2]; | |
700 | recordlen = mem[3]; | |
701 | if (recordlen < 15) { | |
702 | NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]); | |
703 | return; | |
704 | } | |
705 | ||
706 | /* parse vbios entries into common format */ | |
707 | memtimings->timing = | |
708 | kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); | |
709 | if (!memtimings->timing) | |
710 | return; | |
711 | ||
712 | entry = mem + mem[1]; | |
713 | for (i = 0; i < entries; i++, entry += recordlen) { | |
714 | struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; | |
715 | if (entry[0] == 0) | |
716 | continue; | |
717 | ||
718 | tUNK_18 = 1; | |
719 | tUNK_19 = 1; | |
720 | tUNK_20 = 0; | |
721 | tUNK_21 = 0; | |
a845fff8 RS |
722 | switch (MIN(recordlen,21)) { |
723 | case 21: | |
7760fcb0 | 724 | tUNK_21 = entry[21]; |
a845fff8 | 725 | case 20: |
7760fcb0 | 726 | tUNK_20 = entry[20]; |
a845fff8 | 727 | case 19: |
7760fcb0 | 728 | tUNK_19 = entry[19]; |
a845fff8 | 729 | case 18: |
7760fcb0 RS |
730 | tUNK_18 = entry[18]; |
731 | default: | |
732 | tUNK_0 = entry[0]; | |
733 | tUNK_1 = entry[1]; | |
734 | tUNK_2 = entry[2]; | |
735 | tRP = entry[3]; | |
736 | tRAS = entry[5]; | |
737 | tRFC = entry[7]; | |
738 | tRC = entry[9]; | |
739 | tUNK_10 = entry[10]; | |
740 | tUNK_11 = entry[11]; | |
741 | tUNK_12 = entry[12]; | |
742 | tUNK_13 = entry[13]; | |
743 | tUNK_14 = entry[14]; | |
744 | break; | |
745 | } | |
746 | ||
747 | timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP); | |
748 | ||
749 | /* XXX: I don't trust the -1's and +1's... they must come | |
750 | * from somewhere! */ | |
751 | timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 | | |
752 | tUNK_18 << 16 | | |
753 | (tUNK_1 + tUNK_19 + 1) << 8 | | |
754 | (tUNK_2 - 1)); | |
755 | ||
756 | timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); | |
757 | if(recordlen > 19) { | |
758 | timing->reg_100228 += (tUNK_19 - 1) << 24; | |
759 | } else { | |
760 | timing->reg_100228 += tUNK_12 << 24; | |
761 | } | |
762 | ||
763 | /* XXX: reg_10022c */ | |
764 | ||
765 | timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 | | |
766 | tUNK_13 << 8 | tUNK_13); | |
767 | ||
768 | /* XXX: +6? */ | |
769 | timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC); | |
770 | if(tUNK_10 > tUNK_11) { | |
771 | timing->reg_100234 += tUNK_10 << 16; | |
772 | } else { | |
773 | timing->reg_100234 += tUNK_11 << 16; | |
774 | } | |
775 | ||
776 | /* XXX; reg_100238, reg_10023c */ | |
777 | NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i, | |
778 | timing->reg_100220, timing->reg_100224, | |
779 | timing->reg_100228, timing->reg_10022c); | |
780 | NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n", | |
781 | timing->reg_100230, timing->reg_100234, | |
782 | timing->reg_100238, timing->reg_10023c); | |
783 | } | |
784 | ||
785 | memtimings->nr_timing = entries; | |
786 | memtimings->supported = true; | |
787 | } | |
788 | ||
789 | void | |
790 | nouveau_mem_timing_fini(struct drm_device *dev) | |
791 | { | |
792 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
793 | struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; | |
794 | ||
795 | kfree(mem->timing); | |
796 | } |