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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2006 Ben Skeggs. | |
3 | * | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining | |
7 | * a copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sublicense, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial | |
16 | * portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
19 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
21 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
22 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
23 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
24 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Authors: | |
30 | * Ben Skeggs <darktama@iinet.net.au> | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
479dcaea | 37 | #include "nouveau_ramht.h" |
20abd163 | 38 | #include "nouveau_software.h" |
4c136142 | 39 | #include "nouveau_vm.h" |
cdccc70e | 40 | #include "nv50_display.h" |
6ee73861 | 41 | |
b8c157d3 BS |
42 | struct nouveau_gpuobj_method { |
43 | struct list_head head; | |
44 | u32 mthd; | |
45 | int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data); | |
46 | }; | |
47 | ||
48 | struct nouveau_gpuobj_class { | |
49 | struct list_head head; | |
50 | struct list_head methods; | |
51 | u32 id; | |
52 | u32 engine; | |
53 | }; | |
54 | ||
55 | int | |
56 | nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine) | |
57 | { | |
58 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59 | struct nouveau_gpuobj_class *oc; | |
60 | ||
61 | oc = kzalloc(sizeof(*oc), GFP_KERNEL); | |
62 | if (!oc) | |
63 | return -ENOMEM; | |
64 | ||
65 | INIT_LIST_HEAD(&oc->methods); | |
66 | oc->id = class; | |
67 | oc->engine = engine; | |
68 | list_add(&oc->head, &dev_priv->classes); | |
69 | return 0; | |
70 | } | |
71 | ||
72 | int | |
73 | nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd, | |
74 | int (*exec)(struct nouveau_channel *, u32, u32, u32)) | |
75 | { | |
76 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
77 | struct nouveau_gpuobj_method *om; | |
78 | struct nouveau_gpuobj_class *oc; | |
79 | ||
80 | list_for_each_entry(oc, &dev_priv->classes, head) { | |
81 | if (oc->id == class) | |
82 | goto found; | |
83 | } | |
84 | ||
85 | return -EINVAL; | |
86 | ||
87 | found: | |
88 | om = kzalloc(sizeof(*om), GFP_KERNEL); | |
89 | if (!om) | |
90 | return -ENOMEM; | |
91 | ||
92 | om->mthd = mthd; | |
93 | om->exec = exec; | |
94 | list_add(&om->head, &oc->methods); | |
95 | return 0; | |
96 | } | |
97 | ||
98 | int | |
99 | nouveau_gpuobj_mthd_call(struct nouveau_channel *chan, | |
100 | u32 class, u32 mthd, u32 data) | |
101 | { | |
102 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
103 | struct nouveau_gpuobj_method *om; | |
104 | struct nouveau_gpuobj_class *oc; | |
105 | ||
106 | list_for_each_entry(oc, &dev_priv->classes, head) { | |
107 | if (oc->id != class) | |
108 | continue; | |
109 | ||
110 | list_for_each_entry(om, &oc->methods, head) { | |
111 | if (om->mthd == mthd) | |
112 | return om->exec(chan, class, mthd, data); | |
113 | } | |
114 | } | |
115 | ||
116 | return -ENOENT; | |
117 | } | |
118 | ||
274fec93 BS |
119 | int |
120 | nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid, | |
121 | u32 class, u32 mthd, u32 data) | |
122 | { | |
123 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
124 | struct nouveau_channel *chan = NULL; | |
125 | unsigned long flags; | |
126 | int ret = -EINVAL; | |
127 | ||
128 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
9a11dd65 | 129 | if (chid >= 0 && chid < dev_priv->engine.fifo.channels) |
274fec93 BS |
130 | chan = dev_priv->channels.ptr[chid]; |
131 | if (chan) | |
132 | ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data); | |
133 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
134 | return ret; | |
135 | } | |
136 | ||
6ee73861 BS |
137 | int |
138 | nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, | |
139 | uint32_t size, int align, uint32_t flags, | |
140 | struct nouveau_gpuobj **gpuobj_ret) | |
141 | { | |
142 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
e41115d0 | 143 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; |
6ee73861 | 144 | struct nouveau_gpuobj *gpuobj; |
5125bfd8 | 145 | struct drm_mm_node *ramin = NULL; |
e41115d0 | 146 | int ret, i; |
6ee73861 BS |
147 | |
148 | NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n", | |
149 | chan ? chan->id : -1, size, align, flags); | |
150 | ||
6ee73861 BS |
151 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); |
152 | if (!gpuobj) | |
153 | return -ENOMEM; | |
154 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 155 | gpuobj->dev = dev; |
6ee73861 | 156 | gpuobj->flags = flags; |
eb9bcbdc | 157 | kref_init(&gpuobj->refcount); |
43efc9ce | 158 | gpuobj->size = size; |
6ee73861 | 159 | |
e05d7eae | 160 | spin_lock(&dev_priv->ramin_lock); |
6ee73861 | 161 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); |
e05d7eae | 162 | spin_unlock(&dev_priv->ramin_lock); |
6ee73861 | 163 | |
6e32fedc | 164 | if (!(flags & NVOBJ_FLAG_VM) && chan) { |
5125bfd8 BS |
165 | ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0); |
166 | if (ramin) | |
167 | ramin = drm_mm_get_block(ramin, size, align); | |
5125bfd8 BS |
168 | if (!ramin) { |
169 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
170 | return -ENOMEM; | |
171 | } | |
6ee73861 | 172 | |
e41115d0 BS |
173 | gpuobj->pinst = chan->ramin->pinst; |
174 | if (gpuobj->pinst != ~0) | |
175 | gpuobj->pinst += ramin->start; | |
b833ac26 | 176 | |
ca130c22 | 177 | gpuobj->cinst = ramin->start; |
e41115d0 BS |
178 | gpuobj->vinst = ramin->start + chan->ramin->vinst; |
179 | gpuobj->node = ramin; | |
180 | } else { | |
6e32fedc | 181 | ret = instmem->get(gpuobj, chan, size, align); |
6ee73861 | 182 | if (ret) { |
a8eaebc6 | 183 | nouveau_gpuobj_ref(NULL, &gpuobj); |
6ee73861 BS |
184 | return ret; |
185 | } | |
5125bfd8 | 186 | |
e41115d0 | 187 | ret = -ENOSYS; |
a11c3198 | 188 | if (!(flags & NVOBJ_FLAG_DONT_MAP)) |
e41115d0 BS |
189 | ret = instmem->map(gpuobj); |
190 | if (ret) | |
5125bfd8 | 191 | gpuobj->pinst = ~0; |
e41115d0 BS |
192 | |
193 | gpuobj->cinst = NVOBJ_CINST_GLOBAL; | |
de3a6c0a BS |
194 | } |
195 | ||
6ee73861 | 196 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
43efc9ce | 197 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 198 | nv_wo32(gpuobj, i, 0); |
e41115d0 | 199 | instmem->flush(dev); |
6ee73861 BS |
200 | } |
201 | ||
a8eaebc6 | 202 | |
6ee73861 BS |
203 | *gpuobj_ret = gpuobj; |
204 | return 0; | |
205 | } | |
206 | ||
207 | int | |
fbd2895e | 208 | nouveau_gpuobj_init(struct drm_device *dev) |
6ee73861 BS |
209 | { |
210 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
211 | ||
212 | NV_DEBUG(dev, "\n"); | |
213 | ||
214 | INIT_LIST_HEAD(&dev_priv->gpuobj_list); | |
bd2e597d | 215 | INIT_LIST_HEAD(&dev_priv->classes); |
5125bfd8 BS |
216 | spin_lock_init(&dev_priv->ramin_lock); |
217 | dev_priv->ramin_base = ~0; | |
6ee73861 BS |
218 | |
219 | return 0; | |
220 | } | |
221 | ||
6ee73861 BS |
222 | void |
223 | nouveau_gpuobj_takedown(struct drm_device *dev) | |
224 | { | |
225 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
b8c157d3 BS |
226 | struct nouveau_gpuobj_method *om, *tm; |
227 | struct nouveau_gpuobj_class *oc, *tc; | |
6ee73861 BS |
228 | |
229 | NV_DEBUG(dev, "\n"); | |
6ee73861 | 230 | |
b8c157d3 BS |
231 | list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) { |
232 | list_for_each_entry_safe(om, tm, &oc->methods, head) { | |
233 | list_del(&om->head); | |
234 | kfree(om); | |
235 | } | |
236 | list_del(&oc->head); | |
237 | kfree(oc); | |
238 | } | |
239 | ||
eb9bcbdc | 240 | BUG_ON(!list_empty(&dev_priv->gpuobj_list)); |
6ee73861 BS |
241 | } |
242 | ||
185abecc | 243 | |
eb9bcbdc BS |
244 | static void |
245 | nouveau_gpuobj_del(struct kref *ref) | |
6ee73861 | 246 | { |
eb9bcbdc BS |
247 | struct nouveau_gpuobj *gpuobj = |
248 | container_of(ref, struct nouveau_gpuobj, refcount); | |
a8eaebc6 | 249 | struct drm_device *dev = gpuobj->dev; |
6ee73861 | 250 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
e41115d0 | 251 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; |
6ee73861 BS |
252 | int i; |
253 | ||
a8eaebc6 | 254 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); |
6ee73861 | 255 | |
e41115d0 | 256 | if (gpuobj->node && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) { |
43efc9ce | 257 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 258 | nv_wo32(gpuobj, i, 0); |
e41115d0 | 259 | instmem->flush(dev); |
6ee73861 BS |
260 | } |
261 | ||
262 | if (gpuobj->dtor) | |
263 | gpuobj->dtor(dev, gpuobj); | |
264 | ||
e41115d0 BS |
265 | if (gpuobj->cinst == NVOBJ_CINST_GLOBAL) { |
266 | if (gpuobj->node) { | |
267 | instmem->unmap(gpuobj); | |
268 | instmem->put(gpuobj); | |
269 | } | |
270 | } else { | |
271 | if (gpuobj->node) { | |
272 | spin_lock(&dev_priv->ramin_lock); | |
273 | drm_mm_put_block(gpuobj->node); | |
274 | spin_unlock(&dev_priv->ramin_lock); | |
275 | } | |
276 | } | |
6ee73861 | 277 | |
e05d7eae | 278 | spin_lock(&dev_priv->ramin_lock); |
6ee73861 | 279 | list_del(&gpuobj->list); |
e05d7eae | 280 | spin_unlock(&dev_priv->ramin_lock); |
6ee73861 | 281 | |
6ee73861 | 282 | kfree(gpuobj); |
6ee73861 BS |
283 | } |
284 | ||
a8eaebc6 BS |
285 | void |
286 | nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr) | |
6ee73861 | 287 | { |
a8eaebc6 | 288 | if (ref) |
eb9bcbdc | 289 | kref_get(&ref->refcount); |
6ee73861 | 290 | |
eb9bcbdc BS |
291 | if (*ptr) |
292 | kref_put(&(*ptr)->refcount, nouveau_gpuobj_del); | |
6ee73861 | 293 | |
a8eaebc6 | 294 | *ptr = ref; |
6ee73861 BS |
295 | } |
296 | ||
297 | int | |
43efc9ce BS |
298 | nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst, |
299 | u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj) | |
6ee73861 BS |
300 | { |
301 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
302 | struct nouveau_gpuobj *gpuobj = NULL; | |
303 | int i; | |
304 | ||
305 | NV_DEBUG(dev, | |
43efc9ce BS |
306 | "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n", |
307 | pinst, vinst, size, flags); | |
6ee73861 BS |
308 | |
309 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
310 | if (!gpuobj) | |
311 | return -ENOMEM; | |
312 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 313 | gpuobj->dev = dev; |
43efc9ce | 314 | gpuobj->flags = flags; |
eb9bcbdc | 315 | kref_init(&gpuobj->refcount); |
43efc9ce BS |
316 | gpuobj->size = size; |
317 | gpuobj->pinst = pinst; | |
e41115d0 | 318 | gpuobj->cinst = NVOBJ_CINST_GLOBAL; |
43efc9ce | 319 | gpuobj->vinst = vinst; |
de3a6c0a | 320 | |
6ee73861 | 321 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
43efc9ce | 322 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 323 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 324 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
325 | } |
326 | ||
e05d7eae | 327 | spin_lock(&dev_priv->ramin_lock); |
43efc9ce | 328 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); |
e05d7eae | 329 | spin_unlock(&dev_priv->ramin_lock); |
43efc9ce | 330 | *pgpuobj = gpuobj; |
6ee73861 BS |
331 | return 0; |
332 | } | |
333 | ||
7f4a195f BS |
334 | void |
335 | nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class, | |
336 | u64 base, u64 size, int target, int access, | |
337 | u32 type, u32 comp) | |
6ee73861 | 338 | { |
7f4a195f BS |
339 | struct drm_nouveau_private *dev_priv = obj->dev->dev_private; |
340 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; | |
341 | u32 flags0; | |
6ee73861 | 342 | |
7f4a195f BS |
343 | flags0 = (comp << 29) | (type << 22) | class; |
344 | flags0 |= 0x00100000; | |
345 | ||
346 | switch (access) { | |
347 | case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break; | |
348 | case NV_MEM_ACCESS_RW: | |
349 | case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break; | |
350 | default: | |
351 | break; | |
352 | } | |
6ee73861 BS |
353 | |
354 | switch (target) { | |
7f4a195f BS |
355 | case NV_MEM_TARGET_VRAM: |
356 | flags0 |= 0x00010000; | |
357 | break; | |
358 | case NV_MEM_TARGET_PCI: | |
359 | flags0 |= 0x00020000; | |
360 | break; | |
361 | case NV_MEM_TARGET_PCI_NOSNOOP: | |
362 | flags0 |= 0x00030000; | |
6ee73861 | 363 | break; |
7f4a195f | 364 | case NV_MEM_TARGET_GART: |
b571fe21 | 365 | base += dev_priv->gart_info.aper_base; |
6ee73861 | 366 | default: |
7f4a195f | 367 | flags0 &= ~0x00100000; |
6ee73861 BS |
368 | break; |
369 | } | |
370 | ||
7f4a195f BS |
371 | /* convert to base + limit */ |
372 | size = (base + size) - 1; | |
6ee73861 | 373 | |
7f4a195f BS |
374 | nv_wo32(obj, offset + 0x00, flags0); |
375 | nv_wo32(obj, offset + 0x04, lower_32_bits(size)); | |
376 | nv_wo32(obj, offset + 0x08, lower_32_bits(base)); | |
377 | nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 | | |
378 | upper_32_bits(base)); | |
379 | nv_wo32(obj, offset + 0x10, 0x00000000); | |
380 | nv_wo32(obj, offset + 0x14, 0x00000000); | |
6ee73861 | 381 | |
7f4a195f BS |
382 | pinstmem->flush(obj->dev); |
383 | } | |
6ee73861 | 384 | |
7f4a195f BS |
385 | int |
386 | nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size, | |
387 | int target, int access, u32 type, u32 comp, | |
388 | struct nouveau_gpuobj **pobj) | |
389 | { | |
390 | struct drm_device *dev = chan->dev; | |
391 | int ret; | |
6ee73861 | 392 | |
a0fd9b9f | 393 | ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj); |
7f4a195f BS |
394 | if (ret) |
395 | return ret; | |
6ee73861 | 396 | |
7f4a195f BS |
397 | nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target, |
398 | access, type, comp); | |
6ee73861 BS |
399 | return 0; |
400 | } | |
401 | ||
402 | int | |
7f4a195f BS |
403 | nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, |
404 | u64 size, int access, int target, | |
405 | struct nouveau_gpuobj **pobj) | |
6ee73861 | 406 | { |
7f4a195f | 407 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
6ee73861 | 408 | struct drm_device *dev = chan->dev; |
7f4a195f | 409 | struct nouveau_gpuobj *obj; |
fd70b6cd | 410 | u32 flags0, flags2; |
6ee73861 BS |
411 | int ret; |
412 | ||
7f4a195f BS |
413 | if (dev_priv->card_type >= NV_50) { |
414 | u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0; | |
415 | u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0; | |
416 | ||
417 | return nv50_gpuobj_dma_new(chan, class, base, size, | |
418 | target, access, type, comp, pobj); | |
419 | } | |
420 | ||
421 | if (target == NV_MEM_TARGET_GART) { | |
58e6c7a9 BS |
422 | struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma; |
423 | ||
424 | if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) { | |
425 | if (base == 0) { | |
426 | nouveau_gpuobj_ref(gart, pobj); | |
427 | return 0; | |
428 | } | |
429 | ||
430 | base = nouveau_sgdma_get_physical(dev, base); | |
7f4a195f | 431 | target = NV_MEM_TARGET_PCI; |
7f4a195f | 432 | } else { |
58e6c7a9 BS |
433 | base += dev_priv->gart_info.aper_base; |
434 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) | |
435 | target = NV_MEM_TARGET_PCI_NOSNOOP; | |
436 | else | |
437 | target = NV_MEM_TARGET_PCI; | |
6ee73861 | 438 | } |
6ee73861 BS |
439 | } |
440 | ||
7f4a195f BS |
441 | flags0 = class; |
442 | flags0 |= 0x00003000; /* PT present, PT linear */ | |
443 | flags2 = 0; | |
444 | ||
445 | switch (target) { | |
446 | case NV_MEM_TARGET_PCI: | |
447 | flags0 |= 0x00020000; | |
448 | break; | |
449 | case NV_MEM_TARGET_PCI_NOSNOOP: | |
450 | flags0 |= 0x00030000; | |
451 | break; | |
452 | default: | |
453 | break; | |
454 | } | |
455 | ||
456 | switch (access) { | |
457 | case NV_MEM_ACCESS_RO: | |
458 | flags0 |= 0x00004000; | |
459 | break; | |
460 | case NV_MEM_ACCESS_WO: | |
461 | flags0 |= 0x00008000; | |
462 | default: | |
463 | flags2 |= 0x00000002; | |
464 | break; | |
465 | } | |
466 | ||
467 | flags0 |= (base & 0x00000fff) << 20; | |
468 | flags2 |= (base & 0xfffff000); | |
469 | ||
a0fd9b9f | 470 | ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj); |
7f4a195f BS |
471 | if (ret) |
472 | return ret; | |
473 | ||
474 | nv_wo32(obj, 0x00, flags0); | |
475 | nv_wo32(obj, 0x04, size - 1); | |
476 | nv_wo32(obj, 0x08, flags2); | |
477 | nv_wo32(obj, 0x0c, flags2); | |
478 | ||
479 | obj->engine = NVOBJ_ENGINE_SW; | |
480 | obj->class = class; | |
481 | *pobj = obj; | |
482 | return 0; | |
6ee73861 BS |
483 | } |
484 | ||
6ee73861 | 485 | int |
ceac3099 | 486 | nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) |
6ee73861 | 487 | { |
a6a1a380 | 488 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
6ee73861 | 489 | struct drm_device *dev = chan->dev; |
b8c157d3 | 490 | struct nouveau_gpuobj_class *oc; |
6ee73861 BS |
491 | int ret; |
492 | ||
493 | NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class); | |
494 | ||
b8c157d3 | 495 | list_for_each_entry(oc, &dev_priv->classes, head) { |
a82dd49f | 496 | struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine]; |
a6a1a380 | 497 | |
a82dd49f BS |
498 | if (oc->id != class) |
499 | continue; | |
a6a1a380 | 500 | |
a82dd49f BS |
501 | if (!chan->engctx[oc->engine]) { |
502 | ret = eng->context_new(chan, oc->engine); | |
503 | if (ret) | |
504 | return ret; | |
2703c21a | 505 | } |
6ee73861 | 506 | |
a82dd49f | 507 | return eng->object_new(chan, oc->engine, handle, class); |
6ee73861 | 508 | } |
ceac3099 | 509 | |
a82dd49f BS |
510 | NV_ERROR(dev, "illegal object class: 0x%x\n", class); |
511 | return -EINVAL; | |
6ee73861 BS |
512 | } |
513 | ||
6ee73861 BS |
514 | static int |
515 | nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |
516 | { | |
517 | struct drm_device *dev = chan->dev; | |
518 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
6ee73861 BS |
519 | uint32_t size; |
520 | uint32_t base; | |
521 | int ret; | |
522 | ||
523 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
524 | ||
525 | /* Base amount for object storage (4KiB enough?) */ | |
bd2e597d | 526 | size = 0x2000; |
6ee73861 BS |
527 | base = 0; |
528 | ||
6ee73861 BS |
529 | if (dev_priv->card_type == NV_50) { |
530 | /* Various fixed table thingos */ | |
531 | size += 0x1400; /* mostly unknown stuff */ | |
532 | size += 0x4000; /* vm pd */ | |
533 | base = 0x6000; | |
534 | /* RAMHT, not sure about setting size yet, 32KiB to be safe */ | |
535 | size += 0x8000; | |
536 | /* RAMFC */ | |
537 | size += 0x1000; | |
6ee73861 BS |
538 | } |
539 | ||
a8eaebc6 | 540 | ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin); |
6ee73861 BS |
541 | if (ret) { |
542 | NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret); | |
543 | return ret; | |
544 | } | |
6ee73861 | 545 | |
1a97b4ac | 546 | ret = drm_mm_init(&chan->ramin_heap, base, size - base); |
6ee73861 BS |
547 | if (ret) { |
548 | NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret); | |
a8eaebc6 | 549 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
550 | return ret; |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
5de8037a BS |
556 | static int |
557 | nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm) | |
558 | { | |
e432d48f | 559 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
5de8037a BS |
560 | struct drm_device *dev = chan->dev; |
561 | struct nouveau_gpuobj *pgd = NULL; | |
562 | struct nouveau_vm_pgd *vpgd; | |
563 | int ret, i; | |
564 | ||
565 | ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0, &chan->ramin); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | /* create page directory for this vm if none currently exists, | |
570 | * will be destroyed automagically when last reference to the | |
571 | * vm is removed | |
572 | */ | |
573 | if (list_empty(&vm->pgd_list)) { | |
574 | ret = nouveau_gpuobj_new(dev, NULL, 65536, 0x1000, 0, &pgd); | |
575 | if (ret) | |
576 | return ret; | |
577 | } | |
578 | nouveau_vm_ref(vm, &chan->vm, pgd); | |
579 | nouveau_gpuobj_ref(NULL, &pgd); | |
580 | ||
581 | /* point channel at vm's page directory */ | |
582 | vpgd = list_first_entry(&vm->pgd_list, struct nouveau_vm_pgd, head); | |
583 | nv_wo32(chan->ramin, 0x0200, lower_32_bits(vpgd->obj->vinst)); | |
584 | nv_wo32(chan->ramin, 0x0204, upper_32_bits(vpgd->obj->vinst)); | |
585 | nv_wo32(chan->ramin, 0x0208, 0xffffffff); | |
586 | nv_wo32(chan->ramin, 0x020c, 0x000000ff); | |
587 | ||
588 | /* map display semaphore buffers into channel's vm */ | |
3376ee37 BS |
589 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
590 | struct nouveau_bo *bo; | |
591 | if (dev_priv->card_type >= NV_D0) | |
592 | bo = nvd0_display_crtc_sema(dev, i); | |
593 | else | |
594 | bo = nv50_display(dev)->crtc[i].sem.bo; | |
595 | ||
596 | ret = nouveau_bo_vma_add(bo, chan->vm, &chan->dispc_vma[i]); | |
5de8037a BS |
597 | if (ret) |
598 | return ret; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
6ee73861 BS |
604 | int |
605 | nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |
606 | uint32_t vram_h, uint32_t tt_h) | |
607 | { | |
608 | struct drm_device *dev = chan->dev; | |
609 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
0320d791 BS |
610 | struct nouveau_fpriv *fpriv = nouveau_fpriv(chan->file_priv); |
611 | struct nouveau_vm *vm = fpriv ? fpriv->vm : dev_priv->chan_vm; | |
6ee73861 | 612 | struct nouveau_gpuobj *vram = NULL, *tt = NULL; |
cdccc70e | 613 | int ret, i; |
6ee73861 | 614 | |
6ee73861 | 615 | NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); |
2e9733ff | 616 | if (dev_priv->card_type >= NV_C0) |
5de8037a | 617 | return nvc0_gpuobj_channel_init(chan, vm); |
effd6e06 | 618 | |
816544b2 BS |
619 | /* Allocate a chunk of memory for per-channel object storage */ |
620 | ret = nouveau_gpuobj_channel_init_pramin(chan); | |
621 | if (ret) { | |
622 | NV_ERROR(dev, "init pramin\n"); | |
623 | return ret; | |
6ee73861 BS |
624 | } |
625 | ||
effd6e06 | 626 | /* NV50 VM |
6ee73861 | 627 | * - Allocate per-channel page-directory |
4c136142 | 628 | * - Link with shared channel VM |
6ee73861 | 629 | */ |
0320d791 | 630 | if (vm) { |
5125bfd8 BS |
631 | u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200; |
632 | u64 vm_vinst = chan->ramin->vinst + pgd_offs; | |
633 | u32 vm_pinst = chan->ramin->pinst; | |
6ee73861 | 634 | |
5125bfd8 BS |
635 | if (vm_pinst != ~0) |
636 | vm_pinst += pgd_offs; | |
6ee73861 | 637 | |
5125bfd8 | 638 | ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000, |
a8eaebc6 | 639 | 0, &chan->vm_pd); |
f56cb86f | 640 | if (ret) |
6ee73861 | 641 | return ret; |
6ee73861 | 642 | |
0320d791 | 643 | nouveau_vm_ref(vm, &chan->vm, chan->vm_pd); |
6ee73861 BS |
644 | } |
645 | ||
646 | /* RAMHT */ | |
647 | if (dev_priv->card_type < NV_50) { | |
a8eaebc6 BS |
648 | nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL); |
649 | } else { | |
650 | struct nouveau_gpuobj *ramht = NULL; | |
651 | ||
652 | ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16, | |
653 | NVOBJ_FLAG_ZERO_ALLOC, &ramht); | |
6ee73861 BS |
654 | if (ret) |
655 | return ret; | |
a8eaebc6 BS |
656 | |
657 | ret = nouveau_ramht_new(dev, ramht, &chan->ramht); | |
658 | nouveau_gpuobj_ref(NULL, &ramht); | |
6ee73861 BS |
659 | if (ret) |
660 | return ret; | |
cdccc70e BS |
661 | |
662 | /* dma objects for display sync channel semaphore blocks */ | |
1575b364 | 663 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
cdccc70e BS |
664 | struct nouveau_gpuobj *sem = NULL; |
665 | struct nv50_display_crtc *dispc = | |
666 | &nv50_display(dev)->crtc[i]; | |
180cc306 | 667 | u64 offset = dispc->sem.bo->bo.offset; |
cdccc70e BS |
668 | |
669 | ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff, | |
670 | NV_MEM_ACCESS_RW, | |
671 | NV_MEM_TARGET_VRAM, &sem); | |
672 | if (ret) | |
673 | return ret; | |
674 | ||
675 | ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, sem); | |
676 | nouveau_gpuobj_ref(NULL, &sem); | |
677 | if (ret) | |
678 | return ret; | |
679 | } | |
6ee73861 BS |
680 | } |
681 | ||
682 | /* VRAM ctxdma */ | |
683 | if (dev_priv->card_type >= NV_50) { | |
684 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
4c136142 | 685 | 0, (1ULL << 40), NV_MEM_ACCESS_RW, |
7f4a195f | 686 | NV_MEM_TARGET_VM, &vram); |
6ee73861 BS |
687 | if (ret) { |
688 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
689 | return ret; | |
690 | } | |
691 | } else { | |
692 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
a8eaebc6 | 693 | 0, dev_priv->fb_available_size, |
7f4a195f BS |
694 | NV_MEM_ACCESS_RW, |
695 | NV_MEM_TARGET_VRAM, &vram); | |
6ee73861 BS |
696 | if (ret) { |
697 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
698 | return ret; | |
699 | } | |
700 | } | |
701 | ||
a8eaebc6 BS |
702 | ret = nouveau_ramht_insert(chan, vram_h, vram); |
703 | nouveau_gpuobj_ref(NULL, &vram); | |
6ee73861 | 704 | if (ret) { |
a8eaebc6 | 705 | NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
706 | return ret; |
707 | } | |
708 | ||
709 | /* TT memory ctxdma */ | |
710 | if (dev_priv->card_type >= NV_50) { | |
a8eaebc6 | 711 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, |
4c136142 | 712 | 0, (1ULL << 40), NV_MEM_ACCESS_RW, |
7f4a195f | 713 | NV_MEM_TARGET_VM, &tt); |
6ee73861 | 714 | } else { |
7f4a195f BS |
715 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, |
716 | 0, dev_priv->gart_info.aper_size, | |
717 | NV_MEM_ACCESS_RW, | |
718 | NV_MEM_TARGET_GART, &tt); | |
6ee73861 BS |
719 | } |
720 | ||
721 | if (ret) { | |
722 | NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret); | |
723 | return ret; | |
724 | } | |
725 | ||
a8eaebc6 BS |
726 | ret = nouveau_ramht_insert(chan, tt_h, tt); |
727 | nouveau_gpuobj_ref(NULL, &tt); | |
6ee73861 | 728 | if (ret) { |
a8eaebc6 | 729 | NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
730 | return ret; |
731 | } | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
736 | void | |
737 | nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) | |
738 | { | |
6ee73861 | 739 | struct drm_device *dev = chan->dev; |
bf08bcc6 | 740 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
3d483d57 | 741 | int i; |
6ee73861 BS |
742 | |
743 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
744 | ||
3376ee37 BS |
745 | if (dev_priv->card_type >= NV_D0) { |
746 | for (i = 0; i < dev->mode_config.num_crtc; i++) { | |
747 | struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i); | |
748 | nouveau_bo_vma_del(bo, &chan->dispc_vma[i]); | |
749 | } | |
750 | } else | |
751 | if (dev_priv->card_type >= NV_50) { | |
bf08bcc6 | 752 | struct nv50_display *disp = nv50_display(dev); |
1575b364 | 753 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
bf08bcc6 BS |
754 | struct nv50_display_crtc *dispc = &disp->crtc[i]; |
755 | nouveau_bo_vma_del(dispc->sem.bo, &chan->dispc_vma[i]); | |
756 | } | |
3d483d57 | 757 | } |
6ee73861 | 758 | |
e432d48f BS |
759 | nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd); |
760 | nouveau_gpuobj_ref(NULL, &chan->vm_pd); | |
761 | ||
31a5b8ce | 762 | if (drm_mm_initialized(&chan->ramin_heap)) |
b833ac26 | 763 | drm_mm_takedown(&chan->ramin_heap); |
a8eaebc6 | 764 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
765 | } |
766 | ||
767 | int | |
768 | nouveau_gpuobj_suspend(struct drm_device *dev) | |
769 | { | |
770 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
771 | struct nouveau_gpuobj *gpuobj; | |
772 | int i; | |
773 | ||
6ee73861 | 774 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { |
e41115d0 | 775 | if (gpuobj->cinst != NVOBJ_CINST_GLOBAL) |
6ee73861 BS |
776 | continue; |
777 | ||
dc1e5c0d BS |
778 | gpuobj->suspend = vmalloc(gpuobj->size); |
779 | if (!gpuobj->suspend) { | |
6ee73861 BS |
780 | nouveau_gpuobj_resume(dev); |
781 | return -ENOMEM; | |
782 | } | |
783 | ||
43efc9ce | 784 | for (i = 0; i < gpuobj->size; i += 4) |
dc1e5c0d | 785 | gpuobj->suspend[i/4] = nv_ro32(gpuobj, i); |
6ee73861 BS |
786 | } |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
6ee73861 BS |
791 | void |
792 | nouveau_gpuobj_resume(struct drm_device *dev) | |
793 | { | |
794 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
795 | struct nouveau_gpuobj *gpuobj; | |
796 | int i; | |
797 | ||
6ee73861 | 798 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { |
dc1e5c0d | 799 | if (!gpuobj->suspend) |
6ee73861 BS |
800 | continue; |
801 | ||
43efc9ce | 802 | for (i = 0; i < gpuobj->size; i += 4) |
dc1e5c0d BS |
803 | nv_wo32(gpuobj, i, gpuobj->suspend[i/4]); |
804 | ||
805 | vfree(gpuobj->suspend); | |
806 | gpuobj->suspend = NULL; | |
6ee73861 BS |
807 | } |
808 | ||
dc1e5c0d | 809 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
810 | } |
811 | ||
812 | int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, | |
813 | struct drm_file *file_priv) | |
814 | { | |
6ee73861 | 815 | struct drm_nouveau_grobj_alloc *init = data; |
6ee73861 BS |
816 | struct nouveau_channel *chan; |
817 | int ret; | |
818 | ||
6ee73861 BS |
819 | if (init->handle == ~0) |
820 | return -EINVAL; | |
821 | ||
20abd163 BS |
822 | /* compatibility with userspace that assumes 506e for all chipsets */ |
823 | if (init->class == 0x506e) { | |
824 | init->class = nouveau_software_class(dev); | |
825 | if (init->class == 0x906e) | |
826 | return 0; | |
827 | } else | |
828 | if (init->class == 0x906e) { | |
829 | NV_ERROR(dev, "906e not supported yet\n"); | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
e8a863c1 | 833 | chan = nouveau_channel_get(file_priv, init->channel); |
cff5c133 BS |
834 | if (IS_ERR(chan)) |
835 | return PTR_ERR(chan); | |
836 | ||
837 | if (nouveau_ramht_find(chan, init->handle)) { | |
838 | ret = -EEXIST; | |
839 | goto out; | |
840 | } | |
6ee73861 | 841 | |
ceac3099 | 842 | ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class); |
6ee73861 BS |
843 | if (ret) { |
844 | NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n", | |
845 | ret, init->channel, init->handle); | |
6ee73861 BS |
846 | } |
847 | ||
cff5c133 BS |
848 | out: |
849 | nouveau_channel_put(&chan); | |
850 | return ret; | |
6ee73861 BS |
851 | } |
852 | ||
853 | int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, | |
854 | struct drm_file *file_priv) | |
855 | { | |
856 | struct drm_nouveau_gpuobj_free *objfree = data; | |
6ee73861 | 857 | struct nouveau_channel *chan; |
18a16a76 | 858 | int ret; |
6ee73861 | 859 | |
e8a863c1 | 860 | chan = nouveau_channel_get(file_priv, objfree->channel); |
cff5c133 BS |
861 | if (IS_ERR(chan)) |
862 | return PTR_ERR(chan); | |
6ee73861 | 863 | |
6dccd311 FJ |
864 | /* Synchronize with the user channel */ |
865 | nouveau_channel_idle(chan); | |
866 | ||
18a16a76 | 867 | ret = nouveau_ramht_remove(chan, objfree->handle); |
cff5c133 BS |
868 | nouveau_channel_put(&chan); |
869 | return ret; | |
6ee73861 | 870 | } |
b3beb167 BS |
871 | |
872 | u32 | |
873 | nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) | |
874 | { | |
5125bfd8 BS |
875 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
876 | struct drm_device *dev = gpuobj->dev; | |
04eb34a4 | 877 | unsigned long flags; |
5125bfd8 BS |
878 | |
879 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
880 | u64 ptr = gpuobj->vinst + offset; | |
881 | u32 base = ptr >> 16; | |
882 | u32 val; | |
883 | ||
04eb34a4 | 884 | spin_lock_irqsave(&dev_priv->vm_lock, flags); |
5125bfd8 BS |
885 | if (dev_priv->ramin_base != base) { |
886 | dev_priv->ramin_base = base; | |
887 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
888 | } | |
889 | val = nv_rd32(dev, 0x700000 + (ptr & 0xffff)); | |
04eb34a4 | 890 | spin_unlock_irqrestore(&dev_priv->vm_lock, flags); |
5125bfd8 BS |
891 | return val; |
892 | } | |
893 | ||
894 | return nv_ri32(dev, gpuobj->pinst + offset); | |
b3beb167 BS |
895 | } |
896 | ||
897 | void | |
898 | nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val) | |
899 | { | |
5125bfd8 BS |
900 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
901 | struct drm_device *dev = gpuobj->dev; | |
04eb34a4 | 902 | unsigned long flags; |
5125bfd8 BS |
903 | |
904 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
905 | u64 ptr = gpuobj->vinst + offset; | |
906 | u32 base = ptr >> 16; | |
907 | ||
04eb34a4 | 908 | spin_lock_irqsave(&dev_priv->vm_lock, flags); |
5125bfd8 BS |
909 | if (dev_priv->ramin_base != base) { |
910 | dev_priv->ramin_base = base; | |
911 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
912 | } | |
913 | nv_wr32(dev, 0x700000 + (ptr & 0xffff), val); | |
04eb34a4 | 914 | spin_unlock_irqrestore(&dev_priv->vm_lock, flags); |
5125bfd8 BS |
915 | return; |
916 | } | |
917 | ||
918 | nv_wi32(dev, gpuobj->pinst + offset, val); | |
b3beb167 | 919 | } |