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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6ee73861 BS |
28 | #include "drmP.h" |
29 | #include "drm.h" | |
30 | #include "drm_sarea.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include <linux/vgaarb.h> | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
34 | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
38651674 | 37 | #include "nouveau_fbcon.h" |
02a841d4 BS |
38 | #include <core/ramht.h> |
39 | #include <subdev/gpio.h> | |
330c5988 | 40 | #include "nouveau_pm.h" |
6ee73861 | 41 | #include "nv50_display.h" |
02a841d4 | 42 | #include <engine/fifo.h> |
5e120f6e | 43 | #include "nouveau_fence.h" |
20abd163 | 44 | #include "nouveau_software.h" |
6ee73861 | 45 | |
6ee73861 | 46 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 47 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
48 | |
49 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
50 | { | |
51 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
52 | struct nouveau_engine *engine = &dev_priv->engine; | |
53 | ||
54 | switch (dev_priv->chipset & 0xf0) { | |
55 | case 0x00: | |
56 | engine->instmem.init = nv04_instmem_init; | |
57 | engine->instmem.takedown = nv04_instmem_takedown; | |
58 | engine->instmem.suspend = nv04_instmem_suspend; | |
59 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
60 | engine->instmem.get = nv04_instmem_get; |
61 | engine->instmem.put = nv04_instmem_put; | |
62 | engine->instmem.map = nv04_instmem_map; | |
63 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 64 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
65 | engine->mc.init = nv04_mc_init; |
66 | engine->mc.takedown = nv04_mc_takedown; | |
67 | engine->timer.init = nv04_timer_init; | |
68 | engine->timer.read = nv04_timer_read; | |
69 | engine->timer.takedown = nv04_timer_takedown; | |
70 | engine->fb.init = nv04_fb_init; | |
71 | engine->fb.takedown = nv04_fb_takedown; | |
c88c2e06 FJ |
72 | engine->display.early_init = nv04_display_early_init; |
73 | engine->display.late_takedown = nv04_display_late_takedown; | |
74 | engine->display.create = nv04_display_create; | |
c88c2e06 | 75 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
76 | engine->display.init = nv04_display_init; |
77 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
78 | engine->pm.clocks_get = nv04_pm_clocks_get; |
79 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
80 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c | 81 | engine->vram.init = nv04_fb_vram_init; |
24f246ac | 82 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 83 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
84 | break; |
85 | case 0x10: | |
86 | engine->instmem.init = nv04_instmem_init; | |
87 | engine->instmem.takedown = nv04_instmem_takedown; | |
88 | engine->instmem.suspend = nv04_instmem_suspend; | |
89 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
90 | engine->instmem.get = nv04_instmem_get; |
91 | engine->instmem.put = nv04_instmem_put; | |
92 | engine->instmem.map = nv04_instmem_map; | |
93 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 94 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
95 | engine->mc.init = nv04_mc_init; |
96 | engine->mc.takedown = nv04_mc_takedown; | |
97 | engine->timer.init = nv04_timer_init; | |
98 | engine->timer.read = nv04_timer_read; | |
99 | engine->timer.takedown = nv04_timer_takedown; | |
100 | engine->fb.init = nv10_fb_init; | |
101 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
102 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
103 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
104 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
c88c2e06 FJ |
105 | engine->display.early_init = nv04_display_early_init; |
106 | engine->display.late_takedown = nv04_display_late_takedown; | |
107 | engine->display.create = nv04_display_create; | |
c88c2e06 | 108 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
109 | engine->display.init = nv04_display_init; |
110 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
111 | engine->gpio.drive = nv10_gpio_drive; |
112 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
113 | engine->pm.clocks_get = nv04_pm_clocks_get; |
114 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
115 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c BS |
116 | if (dev_priv->chipset == 0x1a || |
117 | dev_priv->chipset == 0x1f) | |
118 | engine->vram.init = nv1a_fb_vram_init; | |
119 | else | |
120 | engine->vram.init = nv10_fb_vram_init; | |
24f246ac | 121 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 122 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
123 | break; |
124 | case 0x20: | |
125 | engine->instmem.init = nv04_instmem_init; | |
126 | engine->instmem.takedown = nv04_instmem_takedown; | |
127 | engine->instmem.suspend = nv04_instmem_suspend; | |
128 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
129 | engine->instmem.get = nv04_instmem_get; |
130 | engine->instmem.put = nv04_instmem_put; | |
131 | engine->instmem.map = nv04_instmem_map; | |
132 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 133 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
134 | engine->mc.init = nv04_mc_init; |
135 | engine->mc.takedown = nv04_mc_takedown; | |
136 | engine->timer.init = nv04_timer_init; | |
137 | engine->timer.read = nv04_timer_read; | |
138 | engine->timer.takedown = nv04_timer_takedown; | |
d81c19e3 BS |
139 | engine->fb.init = nv20_fb_init; |
140 | engine->fb.takedown = nv20_fb_takedown; | |
141 | engine->fb.init_tile_region = nv20_fb_init_tile_region; | |
142 | engine->fb.set_tile_region = nv20_fb_set_tile_region; | |
143 | engine->fb.free_tile_region = nv20_fb_free_tile_region; | |
c88c2e06 FJ |
144 | engine->display.early_init = nv04_display_early_init; |
145 | engine->display.late_takedown = nv04_display_late_takedown; | |
146 | engine->display.create = nv04_display_create; | |
c88c2e06 | 147 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
148 | engine->display.init = nv04_display_init; |
149 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
150 | engine->gpio.drive = nv10_gpio_drive; |
151 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
152 | engine->pm.clocks_get = nv04_pm_clocks_get; |
153 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
154 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
d81c19e3 | 155 | engine->vram.init = nv20_fb_vram_init; |
24f246ac | 156 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 157 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
158 | break; |
159 | case 0x30: | |
160 | engine->instmem.init = nv04_instmem_init; | |
161 | engine->instmem.takedown = nv04_instmem_takedown; | |
162 | engine->instmem.suspend = nv04_instmem_suspend; | |
163 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
164 | engine->instmem.get = nv04_instmem_get; |
165 | engine->instmem.put = nv04_instmem_put; | |
166 | engine->instmem.map = nv04_instmem_map; | |
167 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 168 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
169 | engine->mc.init = nv04_mc_init; |
170 | engine->mc.takedown = nv04_mc_takedown; | |
171 | engine->timer.init = nv04_timer_init; | |
172 | engine->timer.read = nv04_timer_read; | |
173 | engine->timer.takedown = nv04_timer_takedown; | |
8bded189 FJ |
174 | engine->fb.init = nv30_fb_init; |
175 | engine->fb.takedown = nv30_fb_takedown; | |
a5cf68b0 FJ |
176 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
177 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
178 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
c88c2e06 FJ |
179 | engine->display.early_init = nv04_display_early_init; |
180 | engine->display.late_takedown = nv04_display_late_takedown; | |
181 | engine->display.create = nv04_display_create; | |
c88c2e06 | 182 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
183 | engine->display.init = nv04_display_init; |
184 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
185 | engine->gpio.drive = nv10_gpio_drive; |
186 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
187 | engine->pm.clocks_get = nv04_pm_clocks_get; |
188 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
189 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
442b626e BS |
190 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
191 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d81c19e3 | 192 | engine->vram.init = nv20_fb_vram_init; |
24f246ac | 193 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 194 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
195 | break; |
196 | case 0x40: | |
197 | case 0x60: | |
198 | engine->instmem.init = nv04_instmem_init; | |
199 | engine->instmem.takedown = nv04_instmem_takedown; | |
200 | engine->instmem.suspend = nv04_instmem_suspend; | |
201 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
202 | engine->instmem.get = nv04_instmem_get; |
203 | engine->instmem.put = nv04_instmem_put; | |
204 | engine->instmem.map = nv04_instmem_map; | |
205 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 206 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
207 | engine->mc.init = nv40_mc_init; |
208 | engine->mc.takedown = nv40_mc_takedown; | |
209 | engine->timer.init = nv04_timer_init; | |
210 | engine->timer.read = nv04_timer_read; | |
211 | engine->timer.takedown = nv04_timer_takedown; | |
212 | engine->fb.init = nv40_fb_init; | |
213 | engine->fb.takedown = nv40_fb_takedown; | |
a5cf68b0 FJ |
214 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
215 | engine->fb.set_tile_region = nv40_fb_set_tile_region; | |
216 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
c88c2e06 FJ |
217 | engine->display.early_init = nv04_display_early_init; |
218 | engine->display.late_takedown = nv04_display_late_takedown; | |
219 | engine->display.create = nv04_display_create; | |
c88c2e06 | 220 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
221 | engine->display.init = nv04_display_init; |
222 | engine->display.fini = nv04_display_fini; | |
47e5d5cb BS |
223 | engine->gpio.init = nv10_gpio_init; |
224 | engine->gpio.fini = nv10_gpio_fini; | |
a0b25635 BS |
225 | engine->gpio.drive = nv10_gpio_drive; |
226 | engine->gpio.sense = nv10_gpio_sense; | |
47e5d5cb | 227 | engine->gpio.irq_enable = nv10_gpio_irq_enable; |
1262a206 BS |
228 | engine->pm.clocks_get = nv40_pm_clocks_get; |
229 | engine->pm.clocks_pre = nv40_pm_clocks_pre; | |
230 | engine->pm.clocks_set = nv40_pm_clocks_set; | |
442b626e BS |
231 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
232 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 | 233 | engine->pm.temp_get = nv40_temp_get; |
69346180 BS |
234 | engine->pm.pwm_get = nv40_pm_pwm_get; |
235 | engine->pm.pwm_set = nv40_pm_pwm_set; | |
ff92a6cd | 236 | engine->vram.init = nv40_fb_vram_init; |
24f246ac | 237 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 238 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
239 | break; |
240 | case 0x50: | |
241 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
242 | case 0x90: | |
d9f61c2d | 243 | case 0xa0: |
6ee73861 BS |
244 | engine->instmem.init = nv50_instmem_init; |
245 | engine->instmem.takedown = nv50_instmem_takedown; | |
246 | engine->instmem.suspend = nv50_instmem_suspend; | |
247 | engine->instmem.resume = nv50_instmem_resume; | |
e41115d0 BS |
248 | engine->instmem.get = nv50_instmem_get; |
249 | engine->instmem.put = nv50_instmem_put; | |
250 | engine->instmem.map = nv50_instmem_map; | |
251 | engine->instmem.unmap = nv50_instmem_unmap; | |
734ee835 BS |
252 | if (dev_priv->chipset == 0x50) |
253 | engine->instmem.flush = nv50_instmem_flush; | |
254 | else | |
255 | engine->instmem.flush = nv84_instmem_flush; | |
6ee73861 BS |
256 | engine->mc.init = nv50_mc_init; |
257 | engine->mc.takedown = nv50_mc_takedown; | |
258 | engine->timer.init = nv04_timer_init; | |
259 | engine->timer.read = nv04_timer_read; | |
260 | engine->timer.takedown = nv04_timer_takedown; | |
304424e1 MK |
261 | engine->fb.init = nv50_fb_init; |
262 | engine->fb.takedown = nv50_fb_takedown; | |
c88c2e06 FJ |
263 | engine->display.early_init = nv50_display_early_init; |
264 | engine->display.late_takedown = nv50_display_late_takedown; | |
265 | engine->display.create = nv50_display_create; | |
c88c2e06 | 266 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
267 | engine->display.init = nv50_display_init; |
268 | engine->display.fini = nv50_display_fini; | |
ee2e0131 | 269 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
270 | engine->gpio.fini = nv50_gpio_fini; |
271 | engine->gpio.drive = nv50_gpio_drive; | |
272 | engine->gpio.sense = nv50_gpio_sense; | |
ee2e0131 | 273 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
fade7ad5 | 274 | switch (dev_priv->chipset) { |
bd2e597d BS |
275 | case 0x84: |
276 | case 0x86: | |
277 | case 0x92: | |
278 | case 0x94: | |
279 | case 0x96: | |
280 | case 0x98: | |
281 | case 0xa0: | |
5f80198e BS |
282 | case 0xaa: |
283 | case 0xac: | |
bd2e597d | 284 | case 0x50: |
f3fbaf34 BS |
285 | engine->pm.clocks_get = nv50_pm_clocks_get; |
286 | engine->pm.clocks_pre = nv50_pm_clocks_pre; | |
287 | engine->pm.clocks_set = nv50_pm_clocks_set; | |
fade7ad5 | 288 | break; |
bd2e597d | 289 | default: |
ca94a71f BS |
290 | engine->pm.clocks_get = nva3_pm_clocks_get; |
291 | engine->pm.clocks_pre = nva3_pm_clocks_pre; | |
292 | engine->pm.clocks_set = nva3_pm_clocks_set; | |
bd2e597d | 293 | break; |
fade7ad5 | 294 | } |
02c30ca0 BS |
295 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
296 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 FJ |
297 | if (dev_priv->chipset >= 0x84) |
298 | engine->pm.temp_get = nv84_temp_get; | |
299 | else | |
300 | engine->pm.temp_get = nv40_temp_get; | |
5a4267ab BS |
301 | engine->pm.pwm_get = nv50_pm_pwm_get; |
302 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
60d2a88a | 303 | engine->vram.init = nv50_vram_init; |
24f246ac | 304 | engine->vram.takedown = nv50_vram_fini; |
60d2a88a BS |
305 | engine->vram.get = nv50_vram_new; |
306 | engine->vram.put = nv50_vram_del; | |
307 | engine->vram.flags_valid = nv50_vram_flags_valid; | |
6ee73861 | 308 | break; |
d9f61c2d | 309 | case 0xc0: |
4b223eef BS |
310 | engine->instmem.init = nvc0_instmem_init; |
311 | engine->instmem.takedown = nvc0_instmem_takedown; | |
312 | engine->instmem.suspend = nvc0_instmem_suspend; | |
313 | engine->instmem.resume = nvc0_instmem_resume; | |
8984e046 BS |
314 | engine->instmem.get = nv50_instmem_get; |
315 | engine->instmem.put = nv50_instmem_put; | |
316 | engine->instmem.map = nv50_instmem_map; | |
317 | engine->instmem.unmap = nv50_instmem_unmap; | |
318 | engine->instmem.flush = nv84_instmem_flush; | |
4b223eef BS |
319 | engine->mc.init = nv50_mc_init; |
320 | engine->mc.takedown = nv50_mc_takedown; | |
321 | engine->timer.init = nv04_timer_init; | |
322 | engine->timer.read = nv04_timer_read; | |
323 | engine->timer.takedown = nv04_timer_takedown; | |
324 | engine->fb.init = nvc0_fb_init; | |
325 | engine->fb.takedown = nvc0_fb_takedown; | |
4b223eef BS |
326 | engine->display.early_init = nv50_display_early_init; |
327 | engine->display.late_takedown = nv50_display_late_takedown; | |
328 | engine->display.create = nv50_display_create; | |
4b223eef | 329 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
330 | engine->display.init = nv50_display_init; |
331 | engine->display.fini = nv50_display_fini; | |
4b223eef | 332 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
333 | engine->gpio.fini = nv50_gpio_fini; |
334 | engine->gpio.drive = nv50_gpio_drive; | |
335 | engine->gpio.sense = nv50_gpio_sense; | |
4b223eef | 336 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
8984e046 | 337 | engine->vram.init = nvc0_vram_init; |
24f246ac | 338 | engine->vram.takedown = nv50_vram_fini; |
8984e046 BS |
339 | engine->vram.get = nvc0_vram_new; |
340 | engine->vram.put = nv50_vram_del; | |
341 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
74cfad18 | 342 | engine->pm.temp_get = nv84_temp_get; |
354d0781 | 343 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
344 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
345 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
3c71c233 | 346 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
da1dc4cf | 347 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
5a4267ab BS |
348 | engine->pm.pwm_get = nv50_pm_pwm_get; |
349 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
4b223eef | 350 | break; |
d9f61c2d BS |
351 | case 0xd0: |
352 | engine->instmem.init = nvc0_instmem_init; | |
353 | engine->instmem.takedown = nvc0_instmem_takedown; | |
354 | engine->instmem.suspend = nvc0_instmem_suspend; | |
355 | engine->instmem.resume = nvc0_instmem_resume; | |
356 | engine->instmem.get = nv50_instmem_get; | |
357 | engine->instmem.put = nv50_instmem_put; | |
358 | engine->instmem.map = nv50_instmem_map; | |
359 | engine->instmem.unmap = nv50_instmem_unmap; | |
360 | engine->instmem.flush = nv84_instmem_flush; | |
361 | engine->mc.init = nv50_mc_init; | |
362 | engine->mc.takedown = nv50_mc_takedown; | |
363 | engine->timer.init = nv04_timer_init; | |
364 | engine->timer.read = nv04_timer_read; | |
365 | engine->timer.takedown = nv04_timer_takedown; | |
366 | engine->fb.init = nvc0_fb_init; | |
367 | engine->fb.takedown = nvc0_fb_takedown; | |
d9f61c2d BS |
368 | engine->display.early_init = nouveau_stub_init; |
369 | engine->display.late_takedown = nouveau_stub_takedown; | |
26f6d88b | 370 | engine->display.create = nvd0_display_create; |
26f6d88b | 371 | engine->display.destroy = nvd0_display_destroy; |
2a44e499 BS |
372 | engine->display.init = nvd0_display_init; |
373 | engine->display.fini = nvd0_display_fini; | |
d7f8172c | 374 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
375 | engine->gpio.fini = nv50_gpio_fini; |
376 | engine->gpio.drive = nvd0_gpio_drive; | |
377 | engine->gpio.sense = nvd0_gpio_sense; | |
d7f8172c | 378 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
d9f61c2d BS |
379 | engine->vram.init = nvc0_vram_init; |
380 | engine->vram.takedown = nv50_vram_fini; | |
381 | engine->vram.get = nvc0_vram_new; | |
382 | engine->vram.put = nv50_vram_del; | |
383 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
61091837 | 384 | engine->pm.temp_get = nv84_temp_get; |
4784e4aa | 385 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
386 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
387 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
4784e4aa BS |
388 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
389 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d9f61c2d | 390 | break; |
68455a43 BS |
391 | case 0xe0: |
392 | engine->instmem.init = nvc0_instmem_init; | |
393 | engine->instmem.takedown = nvc0_instmem_takedown; | |
394 | engine->instmem.suspend = nvc0_instmem_suspend; | |
395 | engine->instmem.resume = nvc0_instmem_resume; | |
396 | engine->instmem.get = nv50_instmem_get; | |
397 | engine->instmem.put = nv50_instmem_put; | |
398 | engine->instmem.map = nv50_instmem_map; | |
399 | engine->instmem.unmap = nv50_instmem_unmap; | |
400 | engine->instmem.flush = nv84_instmem_flush; | |
401 | engine->mc.init = nv50_mc_init; | |
402 | engine->mc.takedown = nv50_mc_takedown; | |
403 | engine->timer.init = nv04_timer_init; | |
404 | engine->timer.read = nv04_timer_read; | |
405 | engine->timer.takedown = nv04_timer_takedown; | |
406 | engine->fb.init = nvc0_fb_init; | |
407 | engine->fb.takedown = nvc0_fb_takedown; | |
68455a43 BS |
408 | engine->display.early_init = nouveau_stub_init; |
409 | engine->display.late_takedown = nouveau_stub_takedown; | |
410 | engine->display.create = nvd0_display_create; | |
411 | engine->display.destroy = nvd0_display_destroy; | |
412 | engine->display.init = nvd0_display_init; | |
413 | engine->display.fini = nvd0_display_fini; | |
414 | engine->gpio.init = nv50_gpio_init; | |
415 | engine->gpio.fini = nv50_gpio_fini; | |
416 | engine->gpio.drive = nvd0_gpio_drive; | |
417 | engine->gpio.sense = nvd0_gpio_sense; | |
418 | engine->gpio.irq_enable = nv50_gpio_irq_enable; | |
419 | engine->vram.init = nvc0_vram_init; | |
420 | engine->vram.takedown = nv50_vram_fini; | |
421 | engine->vram.get = nvc0_vram_new; | |
422 | engine->vram.put = nv50_vram_del; | |
423 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
424 | break; | |
6ee73861 BS |
425 | default: |
426 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
427 | return 1; | |
428 | } | |
429 | ||
03bc9675 BS |
430 | /* headless mode */ |
431 | if (nouveau_modeset == 2) { | |
432 | engine->display.early_init = nouveau_stub_init; | |
433 | engine->display.late_takedown = nouveau_stub_takedown; | |
434 | engine->display.create = nouveau_stub_init; | |
435 | engine->display.init = nouveau_stub_init; | |
436 | engine->display.destroy = nouveau_stub_takedown; | |
437 | } | |
438 | ||
6ee73861 BS |
439 | return 0; |
440 | } | |
441 | ||
442 | static unsigned int | |
443 | nouveau_vga_set_decode(void *priv, bool state) | |
444 | { | |
9967b948 MK |
445 | struct drm_device *dev = priv; |
446 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
447 | ||
448 | if (dev_priv->chipset >= 0x40) | |
449 | nv_wr32(dev, 0x88054, state); | |
450 | else | |
451 | nv_wr32(dev, 0x1854, state); | |
452 | ||
6ee73861 BS |
453 | if (state) |
454 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
455 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
456 | else | |
457 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
458 | } | |
459 | ||
6a9ee8af DA |
460 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
461 | enum vga_switcheroo_state state) | |
462 | { | |
fbf81762 | 463 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
464 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
465 | if (state == VGA_SWITCHEROO_ON) { | |
466 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
5bcf719b | 467 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 468 | nouveau_pci_resume(pdev); |
fbf81762 | 469 | drm_kms_helper_poll_enable(dev); |
5bcf719b | 470 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
471 | } else { |
472 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
5bcf719b | 473 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fbf81762 | 474 | drm_kms_helper_poll_disable(dev); |
d099230c | 475 | nouveau_switcheroo_optimus_dsm(); |
6a9ee8af | 476 | nouveau_pci_suspend(pdev, pmm); |
5bcf719b | 477 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
478 | } |
479 | } | |
480 | ||
8d608aa6 DA |
481 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
482 | { | |
483 | struct drm_device *dev = pci_get_drvdata(pdev); | |
484 | nouveau_fbcon_output_poll_changed(dev); | |
485 | } | |
486 | ||
6a9ee8af DA |
487 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
488 | { | |
489 | struct drm_device *dev = pci_get_drvdata(pdev); | |
490 | bool can_switch; | |
491 | ||
492 | spin_lock(&dev->count_lock); | |
493 | can_switch = (dev->open_count == 0); | |
494 | spin_unlock(&dev->count_lock); | |
495 | return can_switch; | |
496 | } | |
497 | ||
48aca13f BS |
498 | static void |
499 | nouveau_card_channel_fini(struct drm_device *dev) | |
500 | { | |
501 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
502 | ||
503 | if (dev_priv->channel) | |
504 | nouveau_channel_put_unlocked(&dev_priv->channel); | |
505 | } | |
506 | ||
507 | static int | |
508 | nouveau_card_channel_init(struct drm_device *dev) | |
509 | { | |
510 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
511 | struct nouveau_channel *chan; | |
d1b167e1 | 512 | int ret; |
48aca13f BS |
513 | |
514 | ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT); | |
515 | dev_priv->channel = chan; | |
516 | if (ret) | |
517 | return ret; | |
48aca13f BS |
518 | mutex_unlock(&dev_priv->channel->mutex); |
519 | ||
d1b167e1 BS |
520 | nouveau_bo_move_init(chan); |
521 | return 0; | |
48aca13f BS |
522 | } |
523 | ||
26ec685f TI |
524 | static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = { |
525 | .set_gpu_state = nouveau_switcheroo_set_state, | |
526 | .reprobe = nouveau_switcheroo_reprobe, | |
527 | .can_switch = nouveau_switcheroo_can_switch, | |
528 | }; | |
529 | ||
6ee73861 BS |
530 | int |
531 | nouveau_card_init(struct drm_device *dev) | |
532 | { | |
533 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
534 | struct nouveau_engine *engine; | |
eea55c89 | 535 | int ret, e = 0; |
6ee73861 | 536 | |
6ee73861 | 537 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
26ec685f | 538 | vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops); |
6ee73861 BS |
539 | |
540 | /* Initialise internal driver API hooks */ | |
541 | ret = nouveau_init_engine_ptrs(dev); | |
542 | if (ret) | |
c5804be0 | 543 | goto out; |
6ee73861 | 544 | engine = &dev_priv->engine; |
cff5c133 | 545 | spin_lock_init(&dev_priv->channels.lock); |
a5cf68b0 | 546 | spin_lock_init(&dev_priv->tile.lock); |
ff9e5279 | 547 | spin_lock_init(&dev_priv->context_switch_lock); |
04eb34a4 | 548 | spin_lock_init(&dev_priv->vm_lock); |
6ee73861 | 549 | |
c88c2e06 FJ |
550 | /* Make the CRTCs and I2C buses accessible */ |
551 | ret = engine->display.early_init(dev); | |
552 | if (ret) | |
553 | goto out; | |
554 | ||
6ee73861 | 555 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
556 | ret = nouveau_bios_init(dev); |
557 | if (ret) | |
c88c2e06 | 558 | goto out_display_early; |
6ee73861 | 559 | |
4c5df493 BS |
560 | /* workaround an odd issue on nvc1 by disabling the device's |
561 | * nosnoop capability. hopefully won't cause issues until a | |
562 | * better fix is found - assuming there is one... | |
563 | */ | |
564 | if (dev_priv->chipset == 0xc1) { | |
565 | nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); | |
566 | } | |
567 | ||
668b6c09 BS |
568 | /* PMC */ |
569 | ret = engine->mc.init(dev); | |
570 | if (ret) | |
571 | goto out_bios; | |
572 | ||
573 | /* PTIMER */ | |
574 | ret = engine->timer.init(dev); | |
575 | if (ret) | |
576 | goto out_mc; | |
577 | ||
578 | /* PFB */ | |
579 | ret = engine->fb.init(dev); | |
580 | if (ret) | |
581 | goto out_timer; | |
330c5988 | 582 | |
24f246ac | 583 | ret = engine->vram.init(dev); |
a76fb4e8 | 584 | if (ret) |
668b6c09 | 585 | goto out_fb; |
a76fb4e8 | 586 | |
668b6c09 BS |
587 | /* PGPIO */ |
588 | ret = nouveau_gpio_create(dev); | |
6ee73861 | 589 | if (ret) |
fbd2895e | 590 | goto out_vram; |
6ee73861 | 591 | |
668b6c09 BS |
592 | ret = nouveau_gpuobj_init(dev); |
593 | if (ret) | |
594 | goto out_gpio; | |
595 | ||
6ee73861 BS |
596 | ret = engine->instmem.init(dev); |
597 | if (ret) | |
fbd2895e | 598 | goto out_gpuobj; |
6ee73861 | 599 | |
24f246ac | 600 | ret = nouveau_mem_vram_init(dev); |
6ee73861 | 601 | if (ret) |
c5804be0 | 602 | goto out_instmem; |
6ee73861 | 603 | |
24f246ac BS |
604 | ret = nouveau_mem_gart_init(dev); |
605 | if (ret) | |
606 | goto out_ttmvram; | |
607 | ||
aba99a84 | 608 | if (!dev_priv->noaccel) { |
c420b2dc BS |
609 | switch (dev_priv->card_type) { |
610 | case NV_04: | |
611 | nv04_fifo_create(dev); | |
612 | break; | |
613 | case NV_10: | |
614 | case NV_20: | |
615 | case NV_30: | |
616 | if (dev_priv->chipset < 0x17) | |
617 | nv10_fifo_create(dev); | |
618 | else | |
619 | nv17_fifo_create(dev); | |
620 | break; | |
621 | case NV_40: | |
622 | nv40_fifo_create(dev); | |
623 | break; | |
624 | case NV_50: | |
625 | if (dev_priv->chipset == 0x50) | |
626 | nv50_fifo_create(dev); | |
627 | else | |
628 | nv84_fifo_create(dev); | |
629 | break; | |
630 | case NV_C0: | |
631 | case NV_D0: | |
632 | nvc0_fifo_create(dev); | |
633 | break; | |
634 | case NV_E0: | |
635 | nve0_fifo_create(dev); | |
636 | break; | |
637 | default: | |
638 | break; | |
639 | } | |
640 | ||
5e120f6e BS |
641 | switch (dev_priv->card_type) { |
642 | case NV_04: | |
643 | nv04_fence_create(dev); | |
644 | break; | |
645 | case NV_10: | |
646 | case NV_20: | |
647 | case NV_30: | |
648 | case NV_40: | |
649 | case NV_50: | |
650 | if (dev_priv->chipset < 0x84) | |
651 | nv10_fence_create(dev); | |
652 | else | |
653 | nv84_fence_create(dev); | |
654 | break; | |
655 | case NV_C0: | |
656 | case NV_D0: | |
657 | case NV_E0: | |
658 | nvc0_fence_create(dev); | |
659 | break; | |
660 | default: | |
661 | break; | |
662 | } | |
663 | ||
20abd163 BS |
664 | switch (dev_priv->card_type) { |
665 | case NV_04: | |
666 | case NV_10: | |
667 | case NV_20: | |
668 | case NV_30: | |
669 | case NV_40: | |
670 | nv04_software_create(dev); | |
671 | break; | |
672 | case NV_50: | |
673 | nv50_software_create(dev); | |
674 | break; | |
675 | case NV_C0: | |
676 | case NV_D0: | |
677 | case NV_E0: | |
678 | nvc0_software_create(dev); | |
679 | break; | |
680 | default: | |
681 | break; | |
682 | } | |
683 | ||
18b54c4d BS |
684 | switch (dev_priv->card_type) { |
685 | case NV_04: | |
686 | nv04_graph_create(dev); | |
687 | break; | |
688 | case NV_10: | |
689 | nv10_graph_create(dev); | |
690 | break; | |
691 | case NV_20: | |
692 | case NV_30: | |
693 | nv20_graph_create(dev); | |
694 | break; | |
695 | case NV_40: | |
696 | nv40_graph_create(dev); | |
697 | break; | |
698 | case NV_50: | |
699 | nv50_graph_create(dev); | |
700 | break; | |
701 | case NV_C0: | |
06784090 | 702 | case NV_D0: |
18b54c4d BS |
703 | nvc0_graph_create(dev); |
704 | break; | |
ab394543 BS |
705 | case NV_E0: |
706 | nve0_graph_create(dev); | |
707 | break; | |
18b54c4d BS |
708 | default: |
709 | break; | |
710 | } | |
6dfdd7a6 | 711 | |
7ff5441e | 712 | switch (dev_priv->chipset) { |
18b54c4d BS |
713 | case 0x84: |
714 | case 0x86: | |
715 | case 0x92: | |
716 | case 0x94: | |
717 | case 0x96: | |
718 | case 0xa0: | |
719 | nv84_crypt_create(dev); | |
7ff5441e | 720 | break; |
8f27c543 BS |
721 | case 0x98: |
722 | case 0xaa: | |
723 | case 0xac: | |
724 | nv98_crypt_create(dev); | |
725 | break; | |
7ff5441e | 726 | } |
7ff5441e | 727 | |
18b54c4d BS |
728 | switch (dev_priv->card_type) { |
729 | case NV_50: | |
730 | switch (dev_priv->chipset) { | |
731 | case 0xa3: | |
732 | case 0xa5: | |
733 | case 0xa8: | |
18b54c4d BS |
734 | nva3_copy_create(dev); |
735 | break; | |
736 | } | |
737 | break; | |
738 | case NV_C0: | |
14f0458a BS |
739 | if (!(nv_rd32(dev, 0x022500) & 0x00000200)) |
740 | nvc0_copy_create(dev, 1); | |
0c75f332 | 741 | case NV_D0: |
14f0458a BS |
742 | if (!(nv_rd32(dev, 0x022500) & 0x00000100)) |
743 | nvc0_copy_create(dev, 0); | |
18b54c4d BS |
744 | break; |
745 | default: | |
746 | break; | |
747 | } | |
748 | ||
8f27c543 BS |
749 | if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) { |
750 | nv84_bsp_create(dev); | |
751 | nv84_vp_create(dev); | |
752 | nv98_ppp_create(dev); | |
753 | } else | |
754 | if (dev_priv->chipset >= 0x84) { | |
755 | nv50_mpeg_create(dev); | |
756 | nv84_bsp_create(dev); | |
757 | nv84_vp_create(dev); | |
758 | } else | |
759 | if (dev_priv->chipset >= 0x50) { | |
760 | nv50_mpeg_create(dev); | |
761 | } else | |
52d07331 BS |
762 | if (dev_priv->card_type == NV_40 || |
763 | dev_priv->chipset == 0x31 || | |
764 | dev_priv->chipset == 0x34 || | |
8f27c543 | 765 | dev_priv->chipset == 0x36) { |
323dcac5 | 766 | nv31_mpeg_create(dev); |
8f27c543 | 767 | } |
a02ccc7f | 768 | |
6dfdd7a6 BS |
769 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
770 | if (dev_priv->eng[e]) { | |
771 | ret = dev_priv->eng[e]->init(dev, e); | |
772 | if (ret) | |
773 | goto out_engine; | |
774 | } | |
775 | } | |
a32ed69d | 776 | } |
6ee73861 | 777 | |
1575b364 BS |
778 | ret = nouveau_irq_init(dev); |
779 | if (ret) | |
c420b2dc | 780 | goto out_engine; |
1575b364 | 781 | |
27d5030a | 782 | ret = nouveau_display_create(dev); |
e88efe05 | 783 | if (ret) |
1575b364 | 784 | goto out_irq; |
6ee73861 | 785 | |
10b461e4 | 786 | nouveau_backlight_init(dev); |
7d3a766b | 787 | nouveau_pm_init(dev); |
10b461e4 | 788 | |
c61205b2 | 789 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
48aca13f | 790 | ret = nouveau_card_channel_init(dev); |
0c6c1c2f | 791 | if (ret) |
5e120f6e | 792 | goto out_pm; |
1575b364 BS |
793 | } |
794 | ||
795 | if (dev->mode_config.num_crtc) { | |
f62b27db | 796 | ret = nouveau_display_init(dev); |
1575b364 BS |
797 | if (ret) |
798 | goto out_chan; | |
799 | ||
800 | nouveau_fbcon_init(dev); | |
6ee73861 BS |
801 | } |
802 | ||
6ee73861 | 803 | return 0; |
c5804be0 | 804 | |
1575b364 | 805 | out_chan: |
48aca13f | 806 | nouveau_card_channel_fini(dev); |
7d3a766b BS |
807 | out_pm: |
808 | nouveau_pm_fini(dev); | |
10b461e4 | 809 | nouveau_backlight_exit(dev); |
27d5030a | 810 | nouveau_display_destroy(dev); |
c5804be0 | 811 | out_irq: |
35fa2f2a | 812 | nouveau_irq_fini(dev); |
6dfdd7a6 | 813 | out_engine: |
aba99a84 | 814 | if (!dev_priv->noaccel) { |
6dfdd7a6 | 815 | for (e = e - 1; e >= 0; e--) { |
2703c21a BS |
816 | if (!dev_priv->eng[e]) |
817 | continue; | |
6c320fef | 818 | dev_priv->eng[e]->fini(dev, e, false); |
2703c21a | 819 | dev_priv->eng[e]->destroy(dev,e ); |
6dfdd7a6 BS |
820 | } |
821 | } | |
fbd2895e | 822 | nouveau_mem_gart_fini(dev); |
24f246ac BS |
823 | out_ttmvram: |
824 | nouveau_mem_vram_fini(dev); | |
c5804be0 MK |
825 | out_instmem: |
826 | engine->instmem.takedown(dev); | |
fbd2895e BS |
827 | out_gpuobj: |
828 | nouveau_gpuobj_takedown(dev); | |
668b6c09 BS |
829 | out_gpio: |
830 | nouveau_gpio_destroy(dev); | |
fbd2895e | 831 | out_vram: |
24f246ac | 832 | engine->vram.takedown(dev); |
668b6c09 BS |
833 | out_fb: |
834 | engine->fb.takedown(dev); | |
835 | out_timer: | |
836 | engine->timer.takedown(dev); | |
837 | out_mc: | |
838 | engine->mc.takedown(dev); | |
c5804be0 MK |
839 | out_bios: |
840 | nouveau_bios_takedown(dev); | |
c88c2e06 FJ |
841 | out_display_early: |
842 | engine->display.late_takedown(dev); | |
c5804be0 | 843 | out: |
5c5ed6e2 | 844 | vga_switcheroo_unregister_client(dev->pdev); |
c5804be0 MK |
845 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
846 | return ret; | |
6ee73861 BS |
847 | } |
848 | ||
849 | static void nouveau_card_takedown(struct drm_device *dev) | |
850 | { | |
851 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
852 | struct nouveau_engine *engine = &dev_priv->engine; | |
6dfdd7a6 | 853 | int e; |
6ee73861 | 854 | |
1575b364 | 855 | if (dev->mode_config.num_crtc) { |
1575b364 | 856 | nouveau_fbcon_fini(dev); |
f62b27db | 857 | nouveau_display_fini(dev); |
1575b364 | 858 | } |
06b75e35 | 859 | |
48aca13f | 860 | nouveau_card_channel_fini(dev); |
7d3a766b | 861 | nouveau_pm_fini(dev); |
10b461e4 | 862 | nouveau_backlight_exit(dev); |
27d5030a | 863 | nouveau_display_destroy(dev); |
06b75e35 | 864 | |
aba99a84 | 865 | if (!dev_priv->noaccel) { |
6dfdd7a6 BS |
866 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
867 | if (dev_priv->eng[e]) { | |
6c320fef | 868 | dev_priv->eng[e]->fini(dev, e, false); |
6dfdd7a6 BS |
869 | dev_priv->eng[e]->destroy(dev,e ); |
870 | } | |
871 | } | |
b6d3d871 | 872 | } |
6ee73861 | 873 | |
97666109 JR |
874 | if (dev_priv->vga_ram) { |
875 | nouveau_bo_unpin(dev_priv->vga_ram); | |
876 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
877 | } | |
878 | ||
b6d3d871 BS |
879 | mutex_lock(&dev->struct_mutex); |
880 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
881 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); | |
882 | mutex_unlock(&dev->struct_mutex); | |
fbd2895e | 883 | nouveau_mem_gart_fini(dev); |
24f246ac | 884 | nouveau_mem_vram_fini(dev); |
6ee73861 | 885 | |
b6d3d871 | 886 | engine->instmem.takedown(dev); |
fbd2895e | 887 | nouveau_gpuobj_takedown(dev); |
6ee73861 | 888 | |
668b6c09 BS |
889 | nouveau_gpio_destroy(dev); |
890 | engine->vram.takedown(dev); | |
891 | engine->fb.takedown(dev); | |
892 | engine->timer.takedown(dev); | |
893 | engine->mc.takedown(dev); | |
894 | ||
b6d3d871 | 895 | nouveau_bios_takedown(dev); |
668b6c09 BS |
896 | engine->display.late_takedown(dev); |
897 | ||
898 | nouveau_irq_fini(dev); | |
6ee73861 | 899 | |
5c5ed6e2 | 900 | vga_switcheroo_unregister_client(dev->pdev); |
b6d3d871 | 901 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
902 | } |
903 | ||
3f0a68d8 BS |
904 | int |
905 | nouveau_open(struct drm_device *dev, struct drm_file *file_priv) | |
906 | { | |
fe32b16e | 907 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
3f0a68d8 | 908 | struct nouveau_fpriv *fpriv; |
e41f26e7 | 909 | int ret; |
3f0a68d8 BS |
910 | |
911 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
912 | if (unlikely(!fpriv)) | |
913 | return -ENOMEM; | |
914 | ||
915 | spin_lock_init(&fpriv->lock); | |
e8a863c1 BS |
916 | INIT_LIST_HEAD(&fpriv->channels); |
917 | ||
e41f26e7 BS |
918 | if (dev_priv->card_type == NV_50) { |
919 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, | |
920 | &fpriv->vm); | |
921 | if (ret) { | |
922 | kfree(fpriv); | |
923 | return ret; | |
924 | } | |
925 | } else | |
926 | if (dev_priv->card_type >= NV_C0) { | |
5de8037a BS |
927 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, |
928 | &fpriv->vm); | |
929 | if (ret) { | |
930 | kfree(fpriv); | |
931 | return ret; | |
932 | } | |
e41f26e7 | 933 | } |
fe32b16e | 934 | |
3f0a68d8 BS |
935 | file_priv->driver_priv = fpriv; |
936 | return 0; | |
937 | } | |
938 | ||
6ee73861 BS |
939 | /* here a client dies, release the stuff that was allocated for its |
940 | * file_priv */ | |
941 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) | |
942 | { | |
943 | nouveau_channel_cleanup(dev, file_priv); | |
944 | } | |
945 | ||
3f0a68d8 BS |
946 | void |
947 | nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv) | |
948 | { | |
949 | struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); | |
fe32b16e | 950 | nouveau_vm_ref(NULL, &fpriv->vm, NULL); |
3f0a68d8 BS |
951 | kfree(fpriv); |
952 | } | |
953 | ||
6ee73861 BS |
954 | /* first module load, setup the mmio/fb mapping */ |
955 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
956 | int nouveau_firstopen(struct drm_device *dev) | |
957 | { | |
958 | return 0; | |
959 | } | |
960 | ||
961 | /* if we have an OF card, copy vbios to RAMIN */ | |
962 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
963 | { | |
964 | #if defined(__powerpc__) | |
965 | int size, i; | |
966 | const uint32_t *bios; | |
967 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
968 | if (!dn) { | |
969 | NV_INFO(dev, "Unable to get the OF node\n"); | |
970 | return; | |
971 | } | |
972 | ||
973 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
974 | if (bios) { | |
975 | for (i = 0; i < size; i += 4) | |
976 | nv_wi32(dev, i, bios[i/4]); | |
977 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
978 | } else { | |
979 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
980 | } | |
981 | #endif | |
982 | } | |
983 | ||
06415c56 MS |
984 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
985 | { | |
986 | struct pci_dev *pdev = dev->pdev; | |
987 | struct apertures_struct *aper = alloc_apertures(3); | |
988 | if (!aper) | |
989 | return NULL; | |
990 | ||
991 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
992 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
993 | aper->count = 1; | |
994 | ||
995 | if (pci_resource_len(pdev, 2)) { | |
996 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
997 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
998 | aper->count++; | |
999 | } | |
1000 | ||
1001 | if (pci_resource_len(pdev, 3)) { | |
1002 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
1003 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
1004 | aper->count++; | |
1005 | } | |
1006 | ||
1007 | return aper; | |
1008 | } | |
1009 | ||
1010 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) | |
1011 | { | |
1012 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3b9676e7 | 1013 | bool primary = false; |
06415c56 MS |
1014 | dev_priv->apertures = nouveau_get_apertures(dev); |
1015 | if (!dev_priv->apertures) | |
1016 | return -ENOMEM; | |
1017 | ||
3b9676e7 MS |
1018 | #ifdef CONFIG_X86 |
1019 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
1020 | #endif | |
f212949c | 1021 | |
3b9676e7 | 1022 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); |
06415c56 MS |
1023 | return 0; |
1024 | } | |
1025 | ||
6ee73861 BS |
1026 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
1027 | { | |
1028 | struct drm_nouveau_private *dev_priv; | |
68455a43 | 1029 | unsigned long long offset, length; |
2f5394c3 | 1030 | uint32_t reg0 = ~0, strap; |
cd0b072f | 1031 | int ret; |
6ee73861 BS |
1032 | |
1033 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
1034 | if (!dev_priv) { |
1035 | ret = -ENOMEM; | |
1036 | goto err_out; | |
1037 | } | |
6ee73861 BS |
1038 | dev->dev_private = dev_priv; |
1039 | dev_priv->dev = dev; | |
1040 | ||
466e69b8 DA |
1041 | pci_set_master(dev->pdev); |
1042 | ||
6ee73861 | 1043 | dev_priv->flags = flags & NOUVEAU_FLAGS; |
6ee73861 BS |
1044 | |
1045 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
1046 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
1047 | ||
2f5394c3 BS |
1048 | /* first up, map the start of mmio and determine the chipset */ |
1049 | dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE); | |
1050 | if (dev_priv->mmio) { | |
1051 | #ifdef __BIG_ENDIAN | |
1052 | /* put the card into big-endian mode if it's not */ | |
1053 | if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) | |
1054 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); | |
1055 | DRM_MEMORYBARRIER(); | |
1056 | #endif | |
1057 | ||
1058 | /* determine chipset and derive architecture from it */ | |
1059 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
1060 | if ((reg0 & 0x0f000000) > 0) { | |
1061 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
1062 | switch (dev_priv->chipset & 0xf0) { | |
1063 | case 0x10: | |
1064 | case 0x20: | |
1065 | case 0x30: | |
1066 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
1067 | break; | |
1068 | case 0x40: | |
1069 | case 0x60: | |
1070 | dev_priv->card_type = NV_40; | |
1071 | break; | |
1072 | case 0x50: | |
1073 | case 0x80: | |
1074 | case 0x90: | |
1075 | case 0xa0: | |
1076 | dev_priv->card_type = NV_50; | |
1077 | break; | |
1078 | case 0xc0: | |
1079 | dev_priv->card_type = NV_C0; | |
1080 | break; | |
1081 | case 0xd0: | |
1082 | dev_priv->card_type = NV_D0; | |
1083 | break; | |
68455a43 BS |
1084 | case 0xe0: |
1085 | dev_priv->card_type = NV_E0; | |
1086 | break; | |
2f5394c3 BS |
1087 | default: |
1088 | break; | |
1089 | } | |
1090 | } else | |
1091 | if ((reg0 & 0xff00fff0) == 0x20004000) { | |
1092 | if (reg0 & 0x00f00000) | |
1093 | dev_priv->chipset = 0x05; | |
1094 | else | |
1095 | dev_priv->chipset = 0x04; | |
1096 | dev_priv->card_type = NV_04; | |
1097 | } | |
1098 | ||
1099 | iounmap(dev_priv->mmio); | |
1100 | } | |
1101 | ||
1102 | if (!dev_priv->card_type) { | |
1103 | NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); | |
1104 | ret = -EINVAL; | |
1105 | goto err_priv; | |
1106 | } | |
1107 | ||
42eddbd7 | 1108 | NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n", |
2f5394c3 | 1109 | dev_priv->card_type, reg0); |
6ee73861 | 1110 | |
68455a43 BS |
1111 | /* map the mmio regs, limiting the amount to preserve vmap space */ |
1112 | offset = pci_resource_start(dev->pdev, 0); | |
1113 | length = pci_resource_len(dev->pdev, 0); | |
1114 | if (dev_priv->card_type < NV_E0) | |
1115 | length = min(length, (unsigned long long)0x00800000); | |
1116 | ||
1117 | dev_priv->mmio = ioremap(offset, length); | |
6ee73861 BS |
1118 | if (!dev_priv->mmio) { |
1119 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " | |
1120 | "Please report your setup to " DRIVER_EMAIL "\n"); | |
a0d069ea | 1121 | ret = -EINVAL; |
d82f8e6c | 1122 | goto err_priv; |
6ee73861 | 1123 | } |
68455a43 | 1124 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset); |
6ee73861 | 1125 | |
f2cbe46f BS |
1126 | /* determine frequency of timing crystal */ |
1127 | strap = nv_rd32(dev, 0x101000); | |
1128 | if ( dev_priv->chipset < 0x17 || | |
1129 | (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25)) | |
1130 | strap &= 0x00000040; | |
1131 | else | |
1132 | strap &= 0x00400040; | |
1133 | ||
1134 | switch (strap) { | |
1135 | case 0x00000000: dev_priv->crystal = 13500; break; | |
1136 | case 0x00000040: dev_priv->crystal = 14318; break; | |
1137 | case 0x00400000: dev_priv->crystal = 27000; break; | |
1138 | case 0x00400040: dev_priv->crystal = 25000; break; | |
1139 | } | |
1140 | ||
1141 | NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal); | |
1142 | ||
aba99a84 BS |
1143 | /* Determine whether we'll attempt acceleration or not, some |
1144 | * cards are disabled by default here due to them being known | |
1145 | * non-functional, or never been tested due to lack of hw. | |
1146 | */ | |
1147 | dev_priv->noaccel = !!nouveau_noaccel; | |
1148 | if (nouveau_noaccel == -1) { | |
1149 | switch (dev_priv->chipset) { | |
06784090 | 1150 | case 0xd9: /* known broken */ |
ab394543 BS |
1151 | case 0xe4: /* needs binary driver firmware */ |
1152 | case 0xe7: /* needs binary driver firmware */ | |
ad830d23 BS |
1153 | NV_INFO(dev, "acceleration disabled by default, pass " |
1154 | "noaccel=0 to force enable\n"); | |
aba99a84 BS |
1155 | dev_priv->noaccel = true; |
1156 | break; | |
1157 | default: | |
1158 | dev_priv->noaccel = false; | |
1159 | break; | |
1160 | } | |
1161 | } | |
1162 | ||
cd0b072f BS |
1163 | ret = nouveau_remove_conflicting_drivers(dev); |
1164 | if (ret) | |
a0d069ea | 1165 | goto err_mmio; |
06415c56 | 1166 | |
25985edc | 1167 | /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */ |
6ee73861 BS |
1168 | if (dev_priv->card_type >= NV_40) { |
1169 | int ramin_bar = 2; | |
1170 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) | |
1171 | ramin_bar = 3; | |
1172 | ||
1173 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); | |
6d696305 BS |
1174 | dev_priv->ramin = |
1175 | ioremap(pci_resource_start(dev->pdev, ramin_bar), | |
6ee73861 BS |
1176 | dev_priv->ramin_size); |
1177 | if (!dev_priv->ramin) { | |
ff920bfb | 1178 | NV_ERROR(dev, "Failed to map PRAMIN BAR\n"); |
a0d069ea DC |
1179 | ret = -ENOMEM; |
1180 | goto err_mmio; | |
6ee73861 | 1181 | } |
6d696305 | 1182 | } else { |
6ee73861 | 1183 | dev_priv->ramin_size = 1 * 1024 * 1024; |
68455a43 | 1184 | dev_priv->ramin = ioremap(offset + NV_RAMIN, |
6d696305 | 1185 | dev_priv->ramin_size); |
6ee73861 BS |
1186 | if (!dev_priv->ramin) { |
1187 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); | |
a0d069ea DC |
1188 | ret = -ENOMEM; |
1189 | goto err_mmio; | |
6ee73861 BS |
1190 | } |
1191 | } | |
1192 | ||
1193 | nouveau_OF_copy_vbios_to_ramin(dev); | |
1194 | ||
1195 | /* Special flags */ | |
1196 | if (dev->pci_device == 0x01a0) | |
1197 | dev_priv->flags |= NV_NFORCE; | |
1198 | else if (dev->pci_device == 0x01f0) | |
1199 | dev_priv->flags |= NV_NFORCE2; | |
1200 | ||
1201 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
1202 | ret = nouveau_card_init(dev); |
1203 | if (ret) | |
a0d069ea | 1204 | goto err_ramin; |
6ee73861 BS |
1205 | |
1206 | return 0; | |
a0d069ea DC |
1207 | |
1208 | err_ramin: | |
1209 | iounmap(dev_priv->ramin); | |
1210 | err_mmio: | |
1211 | iounmap(dev_priv->mmio); | |
a0d069ea DC |
1212 | err_priv: |
1213 | kfree(dev_priv); | |
1214 | dev->dev_private = NULL; | |
1215 | err_out: | |
1216 | return ret; | |
6ee73861 BS |
1217 | } |
1218 | ||
6ee73861 BS |
1219 | void nouveau_lastclose(struct drm_device *dev) |
1220 | { | |
5ccb377f | 1221 | vga_switcheroo_process_delayed_switch(); |
6ee73861 BS |
1222 | } |
1223 | ||
1224 | int nouveau_unload(struct drm_device *dev) | |
1225 | { | |
1226 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1227 | ||
cd0b072f | 1228 | nouveau_card_takedown(dev); |
6ee73861 BS |
1229 | |
1230 | iounmap(dev_priv->mmio); | |
1231 | iounmap(dev_priv->ramin); | |
1232 | ||
1233 | kfree(dev_priv); | |
1234 | dev->dev_private = NULL; | |
1235 | return 0; | |
1236 | } | |
1237 | ||
6ee73861 | 1238 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ |
12fb9525 BS |
1239 | bool |
1240 | nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, | |
1241 | uint32_t reg, uint32_t mask, uint32_t val) | |
6ee73861 BS |
1242 | { |
1243 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1244 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1245 | uint64_t start = ptimer->read(dev); | |
1246 | ||
1247 | do { | |
1248 | if ((nv_rd32(dev, reg) & mask) == val) | |
1249 | return true; | |
1250 | } while (ptimer->read(dev) - start < timeout); | |
1251 | ||
1252 | return false; | |
1253 | } | |
1254 | ||
12fb9525 BS |
1255 | /* Wait until (value(reg) & mask) != val, up until timeout has hit */ |
1256 | bool | |
1257 | nouveau_wait_ne(struct drm_device *dev, uint64_t timeout, | |
1258 | uint32_t reg, uint32_t mask, uint32_t val) | |
1259 | { | |
1260 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1261 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1262 | uint64_t start = ptimer->read(dev); | |
1263 | ||
1264 | do { | |
1265 | if ((nv_rd32(dev, reg) & mask) != val) | |
1266 | return true; | |
1267 | } while (ptimer->read(dev) - start < timeout); | |
1268 | ||
1269 | return false; | |
1270 | } | |
1271 | ||
78e2933d BS |
1272 | /* Wait until cond(data) == true, up until timeout has hit */ |
1273 | bool | |
1274 | nouveau_wait_cb(struct drm_device *dev, u64 timeout, | |
1275 | bool (*cond)(void *), void *data) | |
1276 | { | |
1277 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1278 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1279 | u64 start = ptimer->read(dev); | |
1280 | ||
1281 | do { | |
1282 | if (cond(data) == true) | |
1283 | return true; | |
1284 | } while (ptimer->read(dev) - start < timeout); | |
1285 | ||
1286 | return false; | |
1287 | } | |
1288 | ||
6ee73861 BS |
1289 | /* Waits for PGRAPH to go completely idle */ |
1290 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
1291 | { | |
0541324a FJ |
1292 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
1293 | uint32_t mask = ~0; | |
1294 | ||
1295 | if (dev_priv->card_type == NV_40) | |
1296 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; | |
1297 | ||
1298 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { | |
6ee73861 BS |
1299 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
1300 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
1301 | return false; | |
1302 | } | |
1303 | ||
1304 | return true; | |
1305 | } | |
1306 |