[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / nouveau / nouveau_ttm.c

/*
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
 * All Rights Reserved.
 * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include "nouveau_drv.h"
#include "nouveau_ttm.h"
#include "nouveau_gem.h"

#include "drm_legacy.h"

#include <core/tegra.h>

static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_fb *fb = nvxx_fb(&drm->device);
	man->priv = fb;
	return 0;
}

static int
nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
{
	man->priv = NULL;
	return 0;
}

static inline void
nvkm_mem_node_cleanup(struct nvkm_mem *node)
{
	if (node->vma[0].node) {
		nvkm_vm_unmap(&node->vma[0]);
		nvkm_vm_put(&node->vma[0]);
	}

	if (node->vma[1].node) {
		nvkm_vm_unmap(&node->vma[1]);
		nvkm_vm_put(&node->vma[1]);
	}
}

static void
nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
	nvkm_mem_node_cleanup(mem->mm_node);
	ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node);
}

static int
nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;
	u32 size_nc = 0;
	int ret;

	if (drm->device.info.ram_size == 0)
		return -ENOMEM;

	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
		size_nc = 1 << nvbo->page_shift;

	ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT,
			     mem->page_alignment << PAGE_SHIFT, size_nc,
			     (nvbo->tile_flags >> 8) & 0x3ff, &node);
	if (ret) {
		mem->mm_node = NULL;
		return (ret == -ENOSPC) ? 0 : ret;
	}

	node->page_shift = nvbo->page_shift;

	mem->mm_node = node;
	mem->start   = node->offset >> PAGE_SHIFT;
	return 0;
}

const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	nouveau_vram_manager_init,
	nouveau_vram_manager_fini,
	nouveau_vram_manager_new,
	nouveau_vram_manager_del,
};

static int
nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	return 0;
}

static int
nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	return 0;
}

static void
nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	nvkm_mem_node_cleanup(mem->mm_node);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	switch (drm->device.info.family) {
	case NV_DEVICE_INFO_V0_TNT:
	case NV_DEVICE_INFO_V0_CELSIUS:
	case NV_DEVICE_INFO_V0_KELVIN:
	case NV_DEVICE_INFO_V0_RANKINE:
	case NV_DEVICE_INFO_V0_CURIE:
		break;
	case NV_DEVICE_INFO_V0_TESLA:
		if (drm->device.info.chipset != 0x50)
			node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
		break;
	case NV_DEVICE_INFO_V0_FERMI:
	case NV_DEVICE_INFO_V0_KEPLER:
	case NV_DEVICE_INFO_V0_MAXWELL:
		node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
		break;
	default:
		NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
			drm->device.info.family);
		break;
	}

	mem->mm_node = node;
	mem->start   = 0;
	return 0;
}

static void
nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	nouveau_gart_manager_init,
	nouveau_gart_manager_fini,
	nouveau_gart_manager_new,
	nouveau_gart_manager_del,
	nouveau_gart_manager_debug
};

/*XXX*/
#include <subdev/mmu/nv04.h>
static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
	struct nv04_mmu *priv = (void *)mmu;
	struct nvkm_vm *vm = NULL;
	nvkm_vm_ref(priv->vm, &vm, NULL);
	man->priv = vm;
	return 0;
}

static int
nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	struct nvkm_vm *vm = man->priv;
	nvkm_vm_ref(NULL, &vm, NULL);
	man->priv = NULL;
	return 0;
}

static void
nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node = mem->mm_node;
	if (node->vma[0].node)
		nvkm_vm_put(&node->vma[0]);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nv04_gart_manager_new(struct ttm_mem_type_manager *man,
		      struct ttm_buffer_object *bo,
		      const struct ttm_place *place,
		      struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node;
	int ret;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
			  NV_MEM_ACCESS_RW, &node->vma[0]);
	if (ret) {
		kfree(node);
		return ret;
	}

	mem->mm_node = node;
	mem->start   = node->vma[0].offset >> PAGE_SHIFT;
	return 0;
}

static void
nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nv04_gart_manager = {
	nv04_gart_manager_init,
	nv04_gart_manager_fini,
	nv04_gart_manager_new,
	nv04_gart_manager_del,
	nv04_gart_manager_debug
};

int
nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
{
	struct drm_file *file_priv = filp->private_data;
	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);

	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
		return drm_legacy_mmap(filp, vma);

	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
}

static int
nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
{
	return ttm_mem_global_init(ref->object);
}

static void
nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
{
	ttm_mem_global_release(ref->object);
}

int
nouveau_ttm_global_init(struct nouveau_drm *drm)
{
	struct drm_global_reference *global_ref;
	int ret;

	global_ref = &drm->ttm.mem_global_ref;
	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
	global_ref->size = sizeof(struct ttm_mem_global);
	global_ref->init = &nouveau_ttm_mem_global_init;
	global_ref->release = &nouveau_ttm_mem_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM memory accounting\n");
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
	global_ref = &drm->ttm.bo_global_ref.ref;
	global_ref->global_type = DRM_GLOBAL_TTM_BO;
	global_ref->size = sizeof(struct ttm_bo_global);
	global_ref->init = &ttm_bo_global_init;
	global_ref->release = &ttm_bo_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM BO subsystem\n");
		drm_global_item_unref(&drm->ttm.mem_global_ref);
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	return 0;
}

void
nouveau_ttm_global_release(struct nouveau_drm *drm)
{
	if (drm->ttm.mem_global_ref.release == NULL)
		return;

	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	drm_global_item_unref(&drm->ttm.mem_global_ref);
	drm->ttm.mem_global_ref.release = NULL;
}

int
nouveau_ttm_init(struct nouveau_drm *drm)
{
	struct nvkm_device *device = nvxx_device(&drm->device);
	struct nvkm_pci *pci = device->pci;
	struct drm_device *dev = drm->dev;
	u8 bits;
	int ret;

	if (pci && pci->agp.bridge) {
		drm->agp.bridge = pci->agp.bridge;
		drm->agp.base = pci->agp.base;
		drm->agp.size = pci->agp.size;
		drm->agp.cma = pci->agp.cma;
	}

	bits = nvxx_mmu(&drm->device)->dma_bits;
	if (nvxx_device(&drm->device)->func->pci) {
		if (drm->agp.bridge)
			bits = 32;
	} else if (device->func->tegra) {
		struct nvkm_device_tegra *tegra = device->func->tegra(device);

		/*
		 * If the platform can use a IOMMU, then the addressable DMA
		 * space is constrained by the IOMMU bit
		 */
		if (tegra->func->iommu_bit)
			bits = min(bits, tegra->func->iommu_bit);

	}

	ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
	if (ret && bits != 32) {
		bits = 32;
		ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
	}
	if (ret)
		return ret;

	ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits));
	if (ret)
		dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32));

	ret = nouveau_ttm_global_init(drm);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&drm->ttm.bdev,
				  drm->ttm.bo_global_ref.ref.object,
				  &nouveau_bo_driver,
				  dev->anon_inode->i_mapping,
				  DRM_FILE_PAGE_OFFSET,
				  bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
		return ret;
	}

	/* VRAM init */
	drm->gem.vram_available = drm->device.info.ram_user;

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
			      drm->gem.vram_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
		return ret;
	}

	drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
					 device->func->resource_size(device, 1));

	/* GART init */
	if (!drm->agp.bridge) {
		drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
	} else {
		drm->gem.gart_available = drm->agp.size;
	}

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
			      drm->gem.gart_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "GART mm init failed, %d\n", ret);
		return ret;
	}

	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	return 0;
}

void
nouveau_ttm_fini(struct nouveau_drm *drm)
{
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);

	ttm_bo_device_release(&drm->ttm.bdev);

	nouveau_ttm_global_release(drm);

	arch_phys_wc_del(drm->ttm.mtrr);
	drm->ttm.mtrr = 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
	3	* All Rights Reserved.
	4	* Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
	5	* All Rights Reserved.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a
	8	* copy of this software and associated documentation files (the "Software"),
	9	* to deal in the Software without restriction, including without limitation
	10	* the rights to use, copy, modify, merge, publish, distribute, sub license,
	11	* and/or sell copies of the Software, and to permit persons to whom the
	12	* Software is furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
4dc28134	27	#include "nouveau_drv.h"
ebb945a9 BS	28	#include "nouveau_ttm.h"
ebb945a9 BS	29	#include "nouveau_gem.h"
6ee73861	30
2036eaa7	31	#include "drm_legacy.h"
b31cf78b AC	32
	33	#include <core/tegra.h>
	34
bc9e7b9a BS	35	static int
	36	nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	37	{
897a6e27	38	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
b1e4553c BS	39	struct nvkm_fb *fb = nvxx_fb(&drm->device);
b1e4553c BS	40	man->priv = fb;
bc9e7b9a BS	41	return 0;
	42	}
	43
	44	static int
	45	nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
	46	{
897a6e27	47	man->priv = NULL;
bc9e7b9a BS	48	return 0;
	49	}
	50
	51	static inline void
be83cd4e	52	nvkm_mem_node_cleanup(struct nvkm_mem *node)
bc9e7b9a BS	53	{
bc9e7b9a BS	54	if (node->vma[0].node) {
be83cd4e BS	55	nvkm_vm_unmap(&node->vma[0]);
be83cd4e BS	56	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	57	}
	58
	59	if (node->vma[1].node) {
be83cd4e BS	60	nvkm_vm_unmap(&node->vma[1]);
be83cd4e BS	61	nvkm_vm_put(&node->vma[1]);
bc9e7b9a BS	62	}
	63	}
	64
	65	static void
	66	nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
	67	struct ttm_mem_reg *mem)
	68	{
ebb945a9	69	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
d36a99d2	70	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
be83cd4e	71	nvkm_mem_node_cleanup(mem->mm_node);
d36a99d2	72	ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node);
bc9e7b9a BS	73	}
	74
	75	static int
	76	nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
	77	struct ttm_buffer_object *bo,
f1217ed0	78	const struct ttm_place *place,
bc9e7b9a BS	79	struct ttm_mem_reg *mem)
bc9e7b9a BS	80	{
ebb945a9	81	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
d36a99d2	82	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
bc9e7b9a	83	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	84	struct nvkm_mem *node;
bc9e7b9a BS	85	u32 size_nc = 0;
	86	int ret;
	87
eaecf032 AC	88	if (drm->device.info.ram_size == 0)
	89	return -ENOMEM;
	90
bc9e7b9a BS	91	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
	92	size_nc = 1 << nvbo->page_shift;
	93
d36a99d2 BS	94	ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT,
	95	mem->page_alignment << PAGE_SHIFT, size_nc,
	96	(nvbo->tile_flags >> 8) & 0x3ff, &node);
bc9e7b9a BS	97	if (ret) {
	98	mem->mm_node = NULL;
	99	return (ret == -ENOSPC) ? 0 : ret;
	100	}
	101
	102	node->page_shift = nvbo->page_shift;
	103
	104	mem->mm_node = node;
	105	mem->start = node->offset >> PAGE_SHIFT;
	106	return 0;
	107	}
	108
bc9e7b9a BS	109	const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	110	nouveau_vram_manager_init,
	111	nouveau_vram_manager_fini,
	112	nouveau_vram_manager_new,
	113	nouveau_vram_manager_del,
bc9e7b9a BS	114	};
	115
	116	static int
	117	nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	118	{
	119	return 0;
	120	}
	121
	122	static int
	123	nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
	124	{
	125	return 0;
	126	}
	127
	128	static void
	129	nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
	130	struct ttm_mem_reg *mem)
	131	{
be83cd4e	132	nvkm_mem_node_cleanup(mem->mm_node);
bc9e7b9a BS	133	kfree(mem->mm_node);
	134	mem->mm_node = NULL;
	135	}
	136
	137	static int
	138	nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
	139	struct ttm_buffer_object *bo,
f1217ed0	140	const struct ttm_place *place,
bc9e7b9a BS	141	struct ttm_mem_reg *mem)
bc9e7b9a BS	142	{
de7b7d59 BS	143	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
de7b7d59 BS	144	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	145	struct nvkm_mem *node;
bc9e7b9a	146
bc9e7b9a BS	147	node = kzalloc(sizeof(*node), GFP_KERNEL);
	148	if (!node)
	149	return -ENOMEM;
2e2cfbe6	150
bc9e7b9a BS	151	node->page_shift = 12;
bc9e7b9a BS	152
967e7bde	153	switch (drm->device.info.family) {
eb48b12e AC	154	case NV_DEVICE_INFO_V0_TNT:
	155	case NV_DEVICE_INFO_V0_CELSIUS:
	156	case NV_DEVICE_INFO_V0_KELVIN:
	157	case NV_DEVICE_INFO_V0_RANKINE:
	158	case NV_DEVICE_INFO_V0_CURIE:
	159	break;
967e7bde BS	160	case NV_DEVICE_INFO_V0_TESLA:
967e7bde BS	161	if (drm->device.info.chipset != 0x50)
de7b7d59 BS	162	node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
de7b7d59 BS	163	break;
967e7bde BS	164	case NV_DEVICE_INFO_V0_FERMI:
967e7bde BS	165	case NV_DEVICE_INFO_V0_KEPLER:
eb48b12e	166	case NV_DEVICE_INFO_V0_MAXWELL:
de7b7d59 BS	167	node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
	168	break;
	169	default:
eb48b12e AC	170	NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
eb48b12e AC	171	drm->device.info.family);
de7b7d59 BS	172	break;
	173	}
	174
bc9e7b9a BS	175	mem->mm_node = node;
	176	mem->start = 0;
	177	return 0;
	178	}
	179
5b8a43ae	180	static void
bc9e7b9a BS	181	nouveau_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	182	{
	183	}
	184
	185	const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	186	nouveau_gart_manager_init,
	187	nouveau_gart_manager_fini,
	188	nouveau_gart_manager_new,
	189	nouveau_gart_manager_del,
	190	nouveau_gart_manager_debug
	191	};
	192
fdb751ef	193	/XXX/
5ce3bf3c	194	#include <subdev/mmu/nv04.h>
bc9e7b9a BS	195	static int
	196	nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	197	{
ebb945a9	198	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e	199	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
1f5bffca	200	struct nv04_mmu priv = (void )mmu;
be83cd4e BS	201	struct nvkm_vm *vm = NULL;
be83cd4e BS	202	nvkm_vm_ref(priv->vm, &vm, NULL);
ebb945a9 BS	203	man->priv = vm;
ebb945a9 BS	204	return 0;
bc9e7b9a BS	205	}
	206
	207	static int
	208	nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
	209	{
be83cd4e BS	210	struct nvkm_vm *vm = man->priv;
be83cd4e BS	211	nvkm_vm_ref(NULL, &vm, NULL);
bc9e7b9a BS	212	man->priv = NULL;
	213	return 0;
	214	}
	215
	216	static void
	217	nv04_gart_manager_del(struct ttm_mem_type_manager man, struct ttm_mem_reg mem)
	218	{
be83cd4e	219	struct nvkm_mem *node = mem->mm_node;
bc9e7b9a	220	if (node->vma[0].node)
be83cd4e	221	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	222	kfree(mem->mm_node);
	223	mem->mm_node = NULL;
	224	}
	225
	226	static int
	227	nv04_gart_manager_new(struct ttm_mem_type_manager *man,
	228	struct ttm_buffer_object *bo,
f1217ed0	229	const struct ttm_place *place,
bc9e7b9a BS	230	struct ttm_mem_reg *mem)
bc9e7b9a BS	231	{
be83cd4e	232	struct nvkm_mem *node;
bc9e7b9a BS	233	int ret;
	234
	235	node = kzalloc(sizeof(*node), GFP_KERNEL);
	236	if (!node)
	237	return -ENOMEM;
	238
	239	node->page_shift = 12;
	240
be83cd4e BS	241	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
be83cd4e BS	242	NV_MEM_ACCESS_RW, &node->vma[0]);
bc9e7b9a BS	243	if (ret) {
	244	kfree(node);
	245	return ret;
	246	}
	247
	248	mem->mm_node = node;
	249	mem->start = node->vma[0].offset >> PAGE_SHIFT;
	250	return 0;
	251	}
	252
5b8a43ae	253	static void
bc9e7b9a BS	254	nv04_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	255	{
	256	}
	257
	258	const struct ttm_mem_type_manager_func nv04_gart_manager = {
	259	nv04_gart_manager_init,
	260	nv04_gart_manager_fini,
	261	nv04_gart_manager_new,
	262	nv04_gart_manager_del,
	263	nv04_gart_manager_debug
	264	};
	265
6ee73861 BS	266	int
	267	nouveau_ttm_mmap(struct file filp, struct vm_area_struct vma)
	268	{
	269	struct drm_file *file_priv = filp->private_data;
77145f1c	270	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
6ee73861 BS	271
6ee73861 BS	272	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
2036eaa7	273	return drm_legacy_mmap(filp, vma);
6ee73861	274
ebb945a9	275	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
6ee73861 BS	276	}
	277
	278	static int
ba4420c2	279	nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
6ee73861 BS	280	{
	281	return ttm_mem_global_init(ref->object);
	282	}
	283
	284	static void
ba4420c2	285	nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
6ee73861 BS	286	{
	287	ttm_mem_global_release(ref->object);
	288	}
	289
	290	int
ebb945a9	291	nouveau_ttm_global_init(struct nouveau_drm *drm)
6ee73861	292	{
ba4420c2	293	struct drm_global_reference *global_ref;
6ee73861 BS	294	int ret;
6ee73861 BS	295
ebb945a9	296	global_ref = &drm->ttm.mem_global_ref;
ba4420c2	297	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
6ee73861 BS	298	global_ref->size = sizeof(struct ttm_mem_global);
	299	global_ref->init = &nouveau_ttm_mem_global_init;
	300	global_ref->release = &nouveau_ttm_mem_global_release;
	301
ba4420c2	302	ret = drm_global_item_ref(global_ref);
6ee73861 BS	303	if (unlikely(ret != 0)) {
6ee73861 BS	304	DRM_ERROR("Failed setting up TTM memory accounting\n");
ebb945a9	305	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	306	return ret;
	307	}
	308
ebb945a9 BS	309	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
ebb945a9 BS	310	global_ref = &drm->ttm.bo_global_ref.ref;
ba4420c2	311	global_ref->global_type = DRM_GLOBAL_TTM_BO;
6ee73861 BS	312	global_ref->size = sizeof(struct ttm_bo_global);
	313	global_ref->init = &ttm_bo_global_init;
	314	global_ref->release = &ttm_bo_global_release;
	315
ba4420c2	316	ret = drm_global_item_ref(global_ref);
6ee73861 BS	317	if (unlikely(ret != 0)) {
6ee73861 BS	318	DRM_ERROR("Failed setting up TTM BO subsystem\n");
ebb945a9 BS	319	drm_global_item_unref(&drm->ttm.mem_global_ref);
ebb945a9 BS	320	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	321	return ret;
	322	}
	323
	324	return 0;
	325	}
	326
	327	void
ebb945a9	328	nouveau_ttm_global_release(struct nouveau_drm *drm)
6ee73861	329	{
ebb945a9	330	if (drm->ttm.mem_global_ref.release == NULL)
6ee73861 BS	331	return;
6ee73861 BS	332
ebb945a9 BS	333	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	334	drm_global_item_unref(&drm->ttm.mem_global_ref);
	335	drm->ttm.mem_global_ref.release = NULL;
	336	}
	337
	338	int
	339	nouveau_ttm_init(struct nouveau_drm *drm)
	340	{
7e8820fe	341	struct nvkm_device *device = nvxx_device(&drm->device);
340b0e7c	342	struct nvkm_pci *pci = device->pci;
ebb945a9	343	struct drm_device *dev = drm->dev;
524883bb	344	u8 bits;
ebb945a9 BS	345	int ret;
ebb945a9 BS	346
340b0e7c BS	347	if (pci && pci->agp.bridge) {
	348	drm->agp.bridge = pci->agp.bridge;
	349	drm->agp.base = pci->agp.base;
	350	drm->agp.size = pci->agp.size;
	351	drm->agp.cma = pci->agp.cma;
	352	}
	353
989aa5b7	354	bits = nvxx_mmu(&drm->device)->dma_bits;
26c9e8ef	355	if (nvxx_device(&drm->device)->func->pci) {
0dcc4a59	356	if (drm->agp.bridge)
420b9469	357	bits = 32;
b31cf78b AC	358	} else if (device->func->tegra) {
b31cf78b AC	359	struct nvkm_device_tegra *tegra = device->func->tegra(device);
420b9469	360
b31cf78b AC	361	/*
	362	* If the platform can use a IOMMU, then the addressable DMA
	363	* space is constrained by the IOMMU bit
	364	*/
	365	if (tegra->func->iommu_bit)
	366	bits = min(bits, tegra->func->iommu_bit);
420b9469	367
420b9469	368	}
ebb945a9	369
b31cf78b	370	ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
0dcc4a59 CH	371	if (ret && bits != 32) {
	372	bits = 32;
	373	ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits));
	374	}
b31cf78b AC	375	if (ret)
	376	return ret;
	377
	378	ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits));
	379	if (ret)
	380	dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32));
	381
ebb945a9 BS	382	ret = nouveau_ttm_global_init(drm);
	383	if (ret)
	384	return ret;
	385
	386	ret = ttm_bo_device_init(&drm->ttm.bdev,
	387	drm->ttm.bo_global_ref.ref.object,
44d847b7 DH	388	&nouveau_bo_driver,
	389	dev->anon_inode->i_mapping,
	390	DRM_FILE_PAGE_OFFSET,
ebb945a9 BS	391	bits <= 32 ? true : false);
	392	if (ret) {
	393	NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
	394	return ret;
	395	}
	396
	397	/* VRAM init */
f392ec4b	398	drm->gem.vram_available = drm->device.info.ram_user;
ebb945a9 BS	399
	400	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
	401	drm->gem.vram_available >> PAGE_SHIFT);
	402	if (ret) {
	403	NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
	404	return ret;
	405	}
	406
7e8820fe BS	407	drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
7e8820fe BS	408	device->func->resource_size(device, 1));
ebb945a9 BS	409
ebb945a9 BS	410	/* GART init */
340b0e7c	411	if (!drm->agp.bridge) {
989aa5b7	412	drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
ebb945a9 BS	413	} else {
	414	drm->gem.gart_available = drm->agp.size;
	415	}
	416
	417	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
	418	drm->gem.gart_available >> PAGE_SHIFT);
	419	if (ret) {
	420	NV_ERROR(drm, "GART mm init failed, %d\n", ret);
	421	return ret;
	422	}
	423
	424	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	425	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	426	return 0;
	427	}
	428
	429	void
	430	nouveau_ttm_fini(struct nouveau_drm *drm)
	431	{
ebb945a9 BS	432	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
ebb945a9 BS	433	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
ebb945a9 BS	434
	435	ttm_bo_device_release(&drm->ttm.bdev);
	436
	437	nouveau_ttm_global_release(drm);
	438
247d36d7 AL	439	arch_phys_wc_del(drm->ttm.mtrr);
247d36d7 AL	440	drm->ttm.mtrr = 0;
6ee73861	441	}