[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / nouveau / nouveau_ttm.c

/*
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
 * All Rights Reserved.
 * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include "nouveau_drm.h"
#include "nouveau_ttm.h"
#include "nouveau_gem.h"

#include "drm_legacy.h"
static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
	man->priv = pfb;
	return 0;
}

static int
nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
{
	man->priv = NULL;
	return 0;
}

static inline void
nvkm_mem_node_cleanup(struct nvkm_mem *node)
{
	if (node->vma[0].node) {
		nvkm_vm_unmap(&node->vma[0]);
		nvkm_vm_put(&node->vma[0]);
	}

	if (node->vma[1].node) {
		nvkm_vm_unmap(&node->vma[1]);
		nvkm_vm_put(&node->vma[1]);
	}
}

static void
nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
	nvkm_mem_node_cleanup(mem->mm_node);
	pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node);
}

static int
nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;
	u32 size_nc = 0;
	int ret;

	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
		size_nc = 1 << nvbo->page_shift;

	ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT,
			   mem->page_alignment << PAGE_SHIFT, size_nc,
			   (nvbo->tile_flags >> 8) & 0x3ff, &node);
	if (ret) {
		mem->mm_node = NULL;
		return (ret == -ENOSPC) ? 0 : ret;
	}

	node->page_shift = nvbo->page_shift;

	mem->mm_node = node;
	mem->start   = node->offset >> PAGE_SHIFT;
	return 0;
}

static void
nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
	struct nvkm_fb *pfb = man->priv;
	struct nvkm_mm *mm = &pfb->vram;
	struct nvkm_mm_node *r;
	u32 total = 0, free = 0;

	mutex_lock(&nv_subdev(pfb)->mutex);
	list_for_each_entry(r, &mm->nodes, nl_entry) {
		printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
		       prefix, r->type, ((u64)r->offset << 12),
		       (((u64)r->offset + r->length) << 12));

		total += r->length;
		if (!r->type)
			free += r->length;
	}
	mutex_unlock(&nv_subdev(pfb)->mutex);

	printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
	       prefix, (u64)total << 12, (u64)free << 12);
	printk(KERN_DEBUG "%s  block: 0x%08x\n",
	       prefix, mm->block_size << 12);
}

const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	nouveau_vram_manager_init,
	nouveau_vram_manager_fini,
	nouveau_vram_manager_new,
	nouveau_vram_manager_del,
	nouveau_vram_manager_debug
};

static int
nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	return 0;
}

static int
nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	return 0;
}

static void
nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	nvkm_mem_node_cleanup(mem->mm_node);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	switch (drm->device.info.family) {
	case NV_DEVICE_INFO_V0_TESLA:
		if (drm->device.info.chipset != 0x50)
			node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
		break;
	case NV_DEVICE_INFO_V0_FERMI:
	case NV_DEVICE_INFO_V0_KEPLER:
		node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
		break;
	default:
		break;
	}

	mem->mm_node = node;
	mem->start   = 0;
	return 0;
}

static void
nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	nouveau_gart_manager_init,
	nouveau_gart_manager_fini,
	nouveau_gart_manager_new,
	nouveau_gart_manager_del,
	nouveau_gart_manager_debug
};

/*XXX*/
#include <subdev/mmu/nv04.h>
static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
	struct nv04_mmu_priv *priv = (void *)mmu;
	struct nvkm_vm *vm = NULL;
	nvkm_vm_ref(priv->vm, &vm, NULL);
	man->priv = vm;
	return 0;
}

static int
nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	struct nvkm_vm *vm = man->priv;
	nvkm_vm_ref(NULL, &vm, NULL);
	man->priv = NULL;
	return 0;
}

static void
nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node = mem->mm_node;
	if (node->vma[0].node)
		nvkm_vm_put(&node->vma[0]);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nv04_gart_manager_new(struct ttm_mem_type_manager *man,
		      struct ttm_buffer_object *bo,
		      const struct ttm_place *place,
		      struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node;
	int ret;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
			  NV_MEM_ACCESS_RW, &node->vma[0]);
	if (ret) {
		kfree(node);
		return ret;
	}

	mem->mm_node = node;
	mem->start   = node->vma[0].offset >> PAGE_SHIFT;
	return 0;
}

static void
nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nv04_gart_manager = {
	nv04_gart_manager_init,
	nv04_gart_manager_fini,
	nv04_gart_manager_new,
	nv04_gart_manager_del,
	nv04_gart_manager_debug
};

int
nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
{
	struct drm_file *file_priv = filp->private_data;
	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);

	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
		return drm_legacy_mmap(filp, vma);

	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
}

static int
nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
{
	return ttm_mem_global_init(ref->object);
}

static void
nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
{
	ttm_mem_global_release(ref->object);
}

int
nouveau_ttm_global_init(struct nouveau_drm *drm)
{
	struct drm_global_reference *global_ref;
	int ret;

	global_ref = &drm->ttm.mem_global_ref;
	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
	global_ref->size = sizeof(struct ttm_mem_global);
	global_ref->init = &nouveau_ttm_mem_global_init;
	global_ref->release = &nouveau_ttm_mem_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM memory accounting\n");
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
	global_ref = &drm->ttm.bo_global_ref.ref;
	global_ref->global_type = DRM_GLOBAL_TTM_BO;
	global_ref->size = sizeof(struct ttm_bo_global);
	global_ref->init = &ttm_bo_global_init;
	global_ref->release = &ttm_bo_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM BO subsystem\n");
		drm_global_item_unref(&drm->ttm.mem_global_ref);
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	return 0;
}

void
nouveau_ttm_global_release(struct nouveau_drm *drm)
{
	if (drm->ttm.mem_global_ref.release == NULL)
		return;

	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	drm_global_item_unref(&drm->ttm.mem_global_ref);
	drm->ttm.mem_global_ref.release = NULL;
}

int
nouveau_ttm_init(struct nouveau_drm *drm)
{
	struct drm_device *dev = drm->dev;
	u32 bits;
	int ret;

	bits = nvxx_mmu(&drm->device)->dma_bits;
	if (nv_device_is_pci(nvxx_device(&drm->device))) {
		if (drm->agp.stat == ENABLED ||
		     !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
			bits = 32;

		ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
		if (ret)
			return ret;

		ret = pci_set_consistent_dma_mask(dev->pdev,
						  DMA_BIT_MASK(bits));
		if (ret)
			pci_set_consistent_dma_mask(dev->pdev,
						    DMA_BIT_MASK(32));
	}

	ret = nouveau_ttm_global_init(drm);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&drm->ttm.bdev,
				  drm->ttm.bo_global_ref.ref.object,
				  &nouveau_bo_driver,
				  dev->anon_inode->i_mapping,
				  DRM_FILE_PAGE_OFFSET,
				  bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
		return ret;
	}

	/* VRAM init */
	drm->gem.vram_available = drm->device.info.ram_user;

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
			      drm->gem.vram_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
		return ret;
	}

	drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1),
					 nv_device_resource_len(nvxx_device(&drm->device), 1));

	/* GART init */
	if (drm->agp.stat != ENABLED) {
		drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
	} else {
		drm->gem.gart_available = drm->agp.size;
	}

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
			      drm->gem.gart_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "GART mm init failed, %d\n", ret);
		return ret;
	}

	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	return 0;
}

void
nouveau_ttm_fini(struct nouveau_drm *drm)
{
	mutex_lock(&drm->dev->struct_mutex);
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
	mutex_unlock(&drm->dev->struct_mutex);

	ttm_bo_device_release(&drm->ttm.bdev);

	nouveau_ttm_global_release(drm);

	arch_phys_wc_del(drm->ttm.mtrr);
	drm->ttm.mtrr = 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
	3	* All Rights Reserved.
	4	* Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
	5	* All Rights Reserved.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a
	8	* copy of this software and associated documentation files (the "Software"),
	9	* to deal in the Software without restriction, including without limitation
	10	* the rights to use, copy, modify, merge, publish, distribute, sub license,
	11	* and/or sell copies of the Software, and to permit persons to whom the
	12	* Software is furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
ebb945a9 BS	27	#include "nouveau_drm.h"
	28	#include "nouveau_ttm.h"
	29	#include "nouveau_gem.h"
6ee73861	30
2036eaa7	31	#include "drm_legacy.h"
bc9e7b9a BS	32	static int
	33	nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	34	{
897a6e27	35	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e	36	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
897a6e27	37	man->priv = pfb;
bc9e7b9a BS	38	return 0;
	39	}
	40
	41	static int
	42	nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
	43	{
897a6e27	44	man->priv = NULL;
bc9e7b9a BS	45	return 0;
	46	}
	47
	48	static inline void
be83cd4e	49	nvkm_mem_node_cleanup(struct nvkm_mem *node)
bc9e7b9a BS	50	{
bc9e7b9a BS	51	if (node->vma[0].node) {
be83cd4e BS	52	nvkm_vm_unmap(&node->vma[0]);
be83cd4e BS	53	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	54	}
	55
	56	if (node->vma[1].node) {
be83cd4e BS	57	nvkm_vm_unmap(&node->vma[1]);
be83cd4e BS	58	nvkm_vm_put(&node->vma[1]);
bc9e7b9a BS	59	}
	60	}
	61
	62	static void
	63	nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
	64	struct ttm_mem_reg *mem)
	65	{
ebb945a9	66	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e BS	67	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
	68	nvkm_mem_node_cleanup(mem->mm_node);
	69	pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node);
bc9e7b9a BS	70	}
	71
	72	static int
	73	nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
	74	struct ttm_buffer_object *bo,
f1217ed0	75	const struct ttm_place *place,
bc9e7b9a BS	76	struct ttm_mem_reg *mem)
bc9e7b9a BS	77	{
ebb945a9	78	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e	79	struct nvkm_fb *pfb = nvxx_fb(&drm->device);
bc9e7b9a	80	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	81	struct nvkm_mem *node;
bc9e7b9a BS	82	u32 size_nc = 0;
	83	int ret;
	84
	85	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
	86	size_nc = 1 << nvbo->page_shift;
	87
dceef5d8	88	ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT,
ebb945a9 BS	89	mem->page_alignment << PAGE_SHIFT, size_nc,
ebb945a9 BS	90	(nvbo->tile_flags >> 8) & 0x3ff, &node);
bc9e7b9a BS	91	if (ret) {
	92	mem->mm_node = NULL;
	93	return (ret == -ENOSPC) ? 0 : ret;
	94	}
	95
	96	node->page_shift = nvbo->page_shift;
	97
	98	mem->mm_node = node;
	99	mem->start = node->offset >> PAGE_SHIFT;
	100	return 0;
	101	}
	102
5b8a43ae	103	static void
bc9e7b9a BS	104	nouveau_vram_manager_debug(struct ttm_mem_type_manager man, const char prefix)
bc9e7b9a BS	105	{
be83cd4e BS	106	struct nvkm_fb *pfb = man->priv;
	107	struct nvkm_mm *mm = &pfb->vram;
	108	struct nvkm_mm_node *r;
bc9e7b9a BS	109	u32 total = 0, free = 0;
bc9e7b9a BS	110
51a506c0	111	mutex_lock(&nv_subdev(pfb)->mutex);
bc9e7b9a BS	112	list_for_each_entry(r, &mm->nodes, nl_entry) {
	113	printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
	114	prefix, r->type, ((u64)r->offset << 12),
	115	(((u64)r->offset + r->length) << 12));
	116
	117	total += r->length;
	118	if (!r->type)
	119	free += r->length;
	120	}
51a506c0	121	mutex_unlock(&nv_subdev(pfb)->mutex);
bc9e7b9a BS	122
	123	printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
	124	prefix, (u64)total << 12, (u64)free << 12);
	125	printk(KERN_DEBUG "%s block: 0x%08x\n",
	126	prefix, mm->block_size << 12);
	127	}
	128
	129	const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	130	nouveau_vram_manager_init,
	131	nouveau_vram_manager_fini,
	132	nouveau_vram_manager_new,
	133	nouveau_vram_manager_del,
	134	nouveau_vram_manager_debug
	135	};
	136
	137	static int
	138	nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	139	{
	140	return 0;
	141	}
	142
	143	static int
	144	nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
	145	{
	146	return 0;
	147	}
	148
	149	static void
	150	nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
	151	struct ttm_mem_reg *mem)
	152	{
be83cd4e	153	nvkm_mem_node_cleanup(mem->mm_node);
bc9e7b9a BS	154	kfree(mem->mm_node);
	155	mem->mm_node = NULL;
	156	}
	157
	158	static int
	159	nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
	160	struct ttm_buffer_object *bo,
f1217ed0	161	const struct ttm_place *place,
bc9e7b9a BS	162	struct ttm_mem_reg *mem)
bc9e7b9a BS	163	{
de7b7d59 BS	164	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
de7b7d59 BS	165	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	166	struct nvkm_mem *node;
bc9e7b9a	167
bc9e7b9a BS	168	node = kzalloc(sizeof(*node), GFP_KERNEL);
	169	if (!node)
	170	return -ENOMEM;
2e2cfbe6	171
bc9e7b9a BS	172	node->page_shift = 12;
bc9e7b9a BS	173
967e7bde BS	174	switch (drm->device.info.family) {
	175	case NV_DEVICE_INFO_V0_TESLA:
	176	if (drm->device.info.chipset != 0x50)
de7b7d59 BS	177	node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
de7b7d59 BS	178	break;
967e7bde BS	179	case NV_DEVICE_INFO_V0_FERMI:
967e7bde BS	180	case NV_DEVICE_INFO_V0_KEPLER:
de7b7d59 BS	181	node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
	182	break;
	183	default:
	184	break;
	185	}
	186
bc9e7b9a BS	187	mem->mm_node = node;
	188	mem->start = 0;
	189	return 0;
	190	}
	191
5b8a43ae	192	static void
bc9e7b9a BS	193	nouveau_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	194	{
	195	}
	196
	197	const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	198	nouveau_gart_manager_init,
	199	nouveau_gart_manager_fini,
	200	nouveau_gart_manager_new,
	201	nouveau_gart_manager_del,
	202	nouveau_gart_manager_debug
	203	};
	204
fdb751ef	205	/XXX/
5ce3bf3c	206	#include <subdev/mmu/nv04.h>
bc9e7b9a BS	207	static int
	208	nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	209	{
ebb945a9	210	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e	211	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
5ce3bf3c	212	struct nv04_mmu_priv priv = (void )mmu;
be83cd4e BS	213	struct nvkm_vm *vm = NULL;
be83cd4e BS	214	nvkm_vm_ref(priv->vm, &vm, NULL);
ebb945a9 BS	215	man->priv = vm;
ebb945a9 BS	216	return 0;
bc9e7b9a BS	217	}
	218
	219	static int
	220	nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
	221	{
be83cd4e BS	222	struct nvkm_vm *vm = man->priv;
be83cd4e BS	223	nvkm_vm_ref(NULL, &vm, NULL);
bc9e7b9a BS	224	man->priv = NULL;
	225	return 0;
	226	}
	227
	228	static void
	229	nv04_gart_manager_del(struct ttm_mem_type_manager man, struct ttm_mem_reg mem)
	230	{
be83cd4e	231	struct nvkm_mem *node = mem->mm_node;
bc9e7b9a	232	if (node->vma[0].node)
be83cd4e	233	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	234	kfree(mem->mm_node);
	235	mem->mm_node = NULL;
	236	}
	237
	238	static int
	239	nv04_gart_manager_new(struct ttm_mem_type_manager *man,
	240	struct ttm_buffer_object *bo,
f1217ed0	241	const struct ttm_place *place,
bc9e7b9a BS	242	struct ttm_mem_reg *mem)
bc9e7b9a BS	243	{
be83cd4e	244	struct nvkm_mem *node;
bc9e7b9a BS	245	int ret;
	246
	247	node = kzalloc(sizeof(*node), GFP_KERNEL);
	248	if (!node)
	249	return -ENOMEM;
	250
	251	node->page_shift = 12;
	252
be83cd4e BS	253	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
be83cd4e BS	254	NV_MEM_ACCESS_RW, &node->vma[0]);
bc9e7b9a BS	255	if (ret) {
	256	kfree(node);
	257	return ret;
	258	}
	259
	260	mem->mm_node = node;
	261	mem->start = node->vma[0].offset >> PAGE_SHIFT;
	262	return 0;
	263	}
	264
5b8a43ae	265	static void
bc9e7b9a BS	266	nv04_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	267	{
	268	}
	269
	270	const struct ttm_mem_type_manager_func nv04_gart_manager = {
	271	nv04_gart_manager_init,
	272	nv04_gart_manager_fini,
	273	nv04_gart_manager_new,
	274	nv04_gart_manager_del,
	275	nv04_gart_manager_debug
	276	};
	277
6ee73861 BS	278	int
	279	nouveau_ttm_mmap(struct file filp, struct vm_area_struct vma)
	280	{
	281	struct drm_file *file_priv = filp->private_data;
77145f1c	282	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
6ee73861 BS	283
6ee73861 BS	284	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
2036eaa7	285	return drm_legacy_mmap(filp, vma);
6ee73861	286
ebb945a9	287	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
6ee73861 BS	288	}
	289
	290	static int
ba4420c2	291	nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
6ee73861 BS	292	{
	293	return ttm_mem_global_init(ref->object);
	294	}
	295
	296	static void
ba4420c2	297	nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
6ee73861 BS	298	{
	299	ttm_mem_global_release(ref->object);
	300	}
	301
	302	int
ebb945a9	303	nouveau_ttm_global_init(struct nouveau_drm *drm)
6ee73861	304	{
ba4420c2	305	struct drm_global_reference *global_ref;
6ee73861 BS	306	int ret;
6ee73861 BS	307
ebb945a9	308	global_ref = &drm->ttm.mem_global_ref;
ba4420c2	309	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
6ee73861 BS	310	global_ref->size = sizeof(struct ttm_mem_global);
	311	global_ref->init = &nouveau_ttm_mem_global_init;
	312	global_ref->release = &nouveau_ttm_mem_global_release;
	313
ba4420c2	314	ret = drm_global_item_ref(global_ref);
6ee73861 BS	315	if (unlikely(ret != 0)) {
6ee73861 BS	316	DRM_ERROR("Failed setting up TTM memory accounting\n");
ebb945a9	317	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	318	return ret;
	319	}
	320
ebb945a9 BS	321	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
ebb945a9 BS	322	global_ref = &drm->ttm.bo_global_ref.ref;
ba4420c2	323	global_ref->global_type = DRM_GLOBAL_TTM_BO;
6ee73861 BS	324	global_ref->size = sizeof(struct ttm_bo_global);
	325	global_ref->init = &ttm_bo_global_init;
	326	global_ref->release = &ttm_bo_global_release;
	327
ba4420c2	328	ret = drm_global_item_ref(global_ref);
6ee73861 BS	329	if (unlikely(ret != 0)) {
6ee73861 BS	330	DRM_ERROR("Failed setting up TTM BO subsystem\n");
ebb945a9 BS	331	drm_global_item_unref(&drm->ttm.mem_global_ref);
ebb945a9 BS	332	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	333	return ret;
	334	}
	335
	336	return 0;
	337	}
	338
	339	void
ebb945a9	340	nouveau_ttm_global_release(struct nouveau_drm *drm)
6ee73861	341	{
ebb945a9	342	if (drm->ttm.mem_global_ref.release == NULL)
6ee73861 BS	343	return;
6ee73861 BS	344
ebb945a9 BS	345	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	346	drm_global_item_unref(&drm->ttm.mem_global_ref);
	347	drm->ttm.mem_global_ref.release = NULL;
	348	}
	349
	350	int
	351	nouveau_ttm_init(struct nouveau_drm *drm)
	352	{
	353	struct drm_device *dev = drm->dev;
	354	u32 bits;
	355	int ret;
	356
989aa5b7 BS	357	bits = nvxx_mmu(&drm->device)->dma_bits;
989aa5b7 BS	358	if (nv_device_is_pci(nvxx_device(&drm->device))) {
420b9469 AC	359	if (drm->agp.stat == ENABLED \|\|
	360	!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
	361	bits = 32;
	362
	363	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
	364	if (ret)
	365	return ret;
	366
	367	ret = pci_set_consistent_dma_mask(dev->pdev,
	368	DMA_BIT_MASK(bits));
	369	if (ret)
	370	pci_set_consistent_dma_mask(dev->pdev,
	371	DMA_BIT_MASK(32));
	372	}
ebb945a9 BS	373
	374	ret = nouveau_ttm_global_init(drm);
	375	if (ret)
	376	return ret;
	377
	378	ret = ttm_bo_device_init(&drm->ttm.bdev,
	379	drm->ttm.bo_global_ref.ref.object,
44d847b7 DH	380	&nouveau_bo_driver,
	381	dev->anon_inode->i_mapping,
	382	DRM_FILE_PAGE_OFFSET,
ebb945a9 BS	383	bits <= 32 ? true : false);
	384	if (ret) {
	385	NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
	386	return ret;
	387	}
	388
	389	/* VRAM init */
f392ec4b	390	drm->gem.vram_available = drm->device.info.ram_user;
ebb945a9 BS	391
	392	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
	393	drm->gem.vram_available >> PAGE_SHIFT);
	394	if (ret) {
	395	NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
	396	return ret;
	397	}
	398
989aa5b7 BS	399	drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1),
989aa5b7 BS	400	nv_device_resource_len(nvxx_device(&drm->device), 1));
ebb945a9 BS	401
	402	/* GART init */
	403	if (drm->agp.stat != ENABLED) {
989aa5b7	404	drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
ebb945a9 BS	405	} else {
	406	drm->gem.gart_available = drm->agp.size;
	407	}
	408
	409	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
	410	drm->gem.gart_available >> PAGE_SHIFT);
	411	if (ret) {
	412	NV_ERROR(drm, "GART mm init failed, %d\n", ret);
	413	return ret;
	414	}
	415
	416	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	417	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	418	return 0;
	419	}
	420
	421	void
	422	nouveau_ttm_fini(struct nouveau_drm *drm)
	423	{
	424	mutex_lock(&drm->dev->struct_mutex);
	425	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
	426	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
	427	mutex_unlock(&drm->dev->struct_mutex);
	428
	429	ttm_bo_device_release(&drm->ttm.bdev);
	430
	431	nouveau_ttm_global_release(drm);
	432
247d36d7 AL	433	arch_phys_wc_del(drm->ttm.mtrr);
247d36d7 AL	434	drm->ttm.mtrr = 0;
6ee73861	435	}