[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_vm.h

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#ifndef __NOUVEAU_VM_H__
#define __NOUVEAU_VM_H__

#include "drmP.h"

#include "nouveau_drv.h"
#include "nouveau_mm.h"

struct nouveau_vm_pgt {
	struct nouveau_gpuobj *obj[2];
	u32 refcount[2];
};

struct nouveau_vm_pgd {
	struct list_head head;
	struct nouveau_gpuobj *obj;
};

struct nouveau_vma {
	struct list_head head;
	int refcount;
	struct nouveau_vm *vm;
	struct nouveau_mm_node *node;
	u64 offset;
	u32 access;
};

struct nouveau_vm {
	struct drm_device *dev;
	struct nouveau_mm mm;
	int refcount;

	struct list_head pgd_list;
	atomic_t engref[16];

	struct nouveau_vm_pgt *pgt;
	u32 fpde;
	u32 lpde;

	u32 pgt_bits;
	u8  spg_shift;
	u8  lpg_shift;

	void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
			struct nouveau_gpuobj *pgt[2]);
	void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
		    struct nouveau_mem *, u32 pte, u32 cnt,
		    u64 phys, u64 delta);
	void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
		       struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);

	void (*map_sg_table)(struct nouveau_vma *, struct nouveau_gpuobj *,
			     struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
	void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt);
	void (*flush)(struct nouveau_vm *);
};

/* nouveau_vm.c */
int  nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset,
		    struct nouveau_vm **);
int  nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
		    struct nouveau_gpuobj *pgd);
int  nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
		    u32 access, struct nouveau_vma *);
void nouveau_vm_put(struct nouveau_vma *);
void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *);
void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *);
void nouveau_vm_unmap(struct nouveau_vma *);
void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length,
		       struct nouveau_mem *);
void nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
			     struct nouveau_mem *mem);
/* nv50_vm.c */
void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
		     struct nouveau_gpuobj *pgt[2]);
void nv50_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
		 struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
void nv50_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
		    struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
void nv50_vm_flush(struct nouveau_vm *);
void nv50_vm_flush_engine(struct drm_device *, int engine);

/* nvc0_vm.c */
void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
		     struct nouveau_gpuobj *pgt[2]);
void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
		 struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
		    struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
void nvc0_vm_flush(struct nouveau_vm *);

#endif
Commit	Line	Data
a11c3198 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#ifndef __NOUVEAU_VM_H__
	26	#define __NOUVEAU_VM_H__
	27
	28	#include "drmP.h"
	29
	30	#include "nouveau_drv.h"
	31	#include "nouveau_mm.h"
	32
	33	struct nouveau_vm_pgt {
3ee01281 BS	34	struct nouveau_gpuobj *obj[2];
3ee01281 BS	35	u32 refcount[2];
a11c3198 BS	36	};
	37
	38	struct nouveau_vm_pgd {
	39	struct list_head head;
	40	struct nouveau_gpuobj *obj;
	41	};
	42
	43	struct nouveau_vma {
fd2871af	44	struct list_head head;
2fd3db6f	45	int refcount;
a11c3198 BS	46	struct nouveau_vm *vm;
	47	struct nouveau_mm_node *node;
	48	u64 offset;
	49	u32 access;
	50	};
	51
	52	struct nouveau_vm {
	53	struct drm_device *dev;
987eec10	54	struct nouveau_mm mm;
a11c3198 BS	55	int refcount;
	56
	57	struct list_head pgd_list;
6dfdd7a6	58	atomic_t engref[16];
a11c3198 BS	59
	60	struct nouveau_vm_pgt *pgt;
	61	u32 fpde;
	62	u32 lpde;
	63
	64	u32 pgt_bits;
	65	u8 spg_shift;
	66	u8 lpg_shift;
	67
3ee01281 BS	68	void (map_pgt)(struct nouveau_gpuobj pgd, u32 pde,
3ee01281 BS	69	struct nouveau_gpuobj *pgt[2]);
a11c3198	70	void (map)(struct nouveau_vma , struct nouveau_gpuobj *,
8f7286f8 BS	71	struct nouveau_mem *, u32 pte, u32 cnt,
8f7286f8 BS	72	u64 phys, u64 delta);
a11c3198	73	void (map_sg)(struct nouveau_vma , struct nouveau_gpuobj *,
26c0c9e3	74	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
22b33e8e DA	75
	76	void (map_sg_table)(struct nouveau_vma , struct nouveau_gpuobj *,
	77	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
a11c3198 BS	78	void (unmap)(struct nouveau_gpuobj pgt, u32 pte, u32 cnt);
	79	void (flush)(struct nouveau_vm );
	80	};
	81
	82	/* nouveau_vm.c */
	83	int nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset,
a11c3198 BS	84	struct nouveau_vm **);
	85	int nouveau_vm_ref(struct nouveau_vm , struct nouveau_vm *,
	86	struct nouveau_gpuobj *pgd);
	87	int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
	88	u32 access, struct nouveau_vma *);
	89	void nouveau_vm_put(struct nouveau_vma *);
d5f42394 BS	90	void nouveau_vm_map(struct nouveau_vma , struct nouveau_mem );
d5f42394 BS	91	void nouveau_vm_map_at(struct nouveau_vma , u64 offset, struct nouveau_mem );
a11c3198 BS	92	void nouveau_vm_unmap(struct nouveau_vma *);
	93	void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
	94	void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length,
f7b24c42	95	struct nouveau_mem *);
22b33e8e DA	96	void nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
22b33e8e DA	97	struct nouveau_mem *mem);
a11c3198	98	/* nv50_vm.c */
3ee01281 BS	99	void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
3ee01281 BS	100	struct nouveau_gpuobj *pgt[2]);
a11c3198	101	void nv50_vm_map(struct nouveau_vma , struct nouveau_gpuobj ,
8f7286f8	102	struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
a11c3198	103	void nv50_vm_map_sg(struct nouveau_vma , struct nouveau_gpuobj ,
26c0c9e3	104	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
a11c3198 BS	105	void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
	106	void nv50_vm_flush(struct nouveau_vm *);
	107	void nv50_vm_flush_engine(struct drm_device *, int engine);
	108
4c74eb7f BS	109	/* nvc0_vm.c */
	110	void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
	111	struct nouveau_gpuobj *pgt[2]);
	112	void nvc0_vm_map(struct nouveau_vma , struct nouveau_gpuobj ,
8f7286f8	113	struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
4c74eb7f	114	void nvc0_vm_map_sg(struct nouveau_vma , struct nouveau_gpuobj ,
26c0c9e3	115	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
4c74eb7f BS	116	void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
	117	void nvc0_vm_flush(struct nouveau_vm *);
	118
a11c3198	119	#endif