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Merge branch 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspe...
[mirror_ubuntu-kernels.git] / drivers / gpu / drm / nouveau / nv04_crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28
29#include "nouveau_drv.h"
30#include "nouveau_encoder.h"
31#include "nouveau_connector.h"
32#include "nouveau_crtc.h"
33#include "nouveau_fb.h"
34#include "nouveau_hw.h"
35#include "nvreg.h"
a424d761 36#include "nouveau_fbcon.h"
6ee73861
BS		 37
38static int
39nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
40 struct drm_framebuffer *old_fb);
41
42static void
43crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
44{
45 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
46 crtcstate->CRTC[index]);
47}
48
49static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
50{
51 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
52 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
53 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
54
55 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
56 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
57 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
58 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
59 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
60 }
61 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
62}
63
64static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
65{
66 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
67 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
68 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
69
70 nv_crtc->sharpness = level;
71 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
72 level += 0x40;
73 regp->ramdac_634 = level;
74 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
75}
76
77#define PLLSEL_VPLL1_MASK \
78 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
79 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
80#define PLLSEL_VPLL2_MASK \
81 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
82 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
83#define PLLSEL_TV_MASK \
84 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
85 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
86 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
87 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
88
89/* NV4x 0x40.. pll notes:
90 * gpu pll: 0x4000 + 0x4004
91 * ?gpu? pll: 0x4008 + 0x400c
92 * vpll1: 0x4010 + 0x4014
93 * vpll2: 0x4018 + 0x401c
94 * mpll: 0x4020 + 0x4024
95 * mpll: 0x4038 + 0x403c
96 *
97 * the first register of each pair has some unknown details:
98 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
99 * bits 20-23: (mpll) something to do with post divider?
100 * bits 28-31: related to single stage mode? (bit 8/12)
101 */
102
103static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
104{
105 struct drm_device *dev = crtc->dev;
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
108 struct nv04_mode_state *state = &dev_priv->mode_reg;
109 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
110 struct nouveau_pll_vals *pv = &regp->pllvals;
111 struct pll_lims pll_lim;
112
855a95e4 113 if (get_pll_limits(dev, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, &pll_lim))
6ee73861
BS		 114 return;
115
116 /* NM2 == 0 is used to determine single stage mode on two stage plls */
117 pv->NM2 = 0;
118
119 /* for newer nv4x the blob uses only the first stage of the vpll below a
120 * certain clock. for a certain nv4b this is 150MHz. since the max
121 * output frequency of the first stage for this card is 300MHz, it is
122 * assumed the threshold is given by vco1 maxfreq/2
123 */
124 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
125 * not 8, others unknown), the blob always uses both plls. no problem
126 * has yet been observed in allowing the use a single stage pll on all
127 * nv43 however. the behaviour of single stage use is untested on nv40
128 */
129 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2))
130 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
131
132 if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv))
133 return;
134
135 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
136
137 /* The blob uses this always, so let's do the same */
138 if (dev_priv->card_type == NV_40)
139 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
140 /* again nv40 and some nv43 act more like nv3x as described above */
141 if (dev_priv->chipset < 0x41)
142 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
143 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
144 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
145
146 if (pv->NM2)
ef2bb506 147 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
6ee73861
BS		 148 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
149 else
ef2bb506 150 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
6ee73861
BS		 151 pv->N1, pv->M1, pv->log2P);
152
153 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
154}
155
156static void
157nv_crtc_dpms(struct drm_crtc *crtc, int mode)
158{
159 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
160 struct drm_device *dev = crtc->dev;
161 unsigned char seq1 = 0, crtc17 = 0;
162 unsigned char crtc1A;
163
ef2bb506 164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
6ee73861
BS		 165 nv_crtc->index);
166
25985edc 167 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
6ee73861
BS		 168 return;
169
170 nv_crtc->last_dpms = mode;
171
172 if (nv_two_heads(dev))
173 NVSetOwner(dev, nv_crtc->index);
174
175 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
176 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
177 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
178 switch (mode) {
179 case DRM_MODE_DPMS_STANDBY:
180 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
181 seq1 = 0x20;
182 crtc17 = 0x80;
183 crtc1A |= 0x80;
184 break;
185 case DRM_MODE_DPMS_SUSPEND:
186 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
187 seq1 = 0x20;
188 crtc17 = 0x80;
189 crtc1A |= 0x40;
190 break;
191 case DRM_MODE_DPMS_OFF:
192 /* Screen: Off; HSync: Off, VSync: Off */
193 seq1 = 0x20;
194 crtc17 = 0x00;
195 crtc1A |= 0xC0;
196 break;
197 case DRM_MODE_DPMS_ON:
198 default:
199 /* Screen: On; HSync: On, VSync: On */
200 seq1 = 0x00;
201 crtc17 = 0x80;
202 break;
203 }
204
205 NVVgaSeqReset(dev, nv_crtc->index, true);
206 /* Each head has it's own sequencer, so we can turn it off when we want */
207 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
208 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
209 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
210 mdelay(10);
211 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
212 NVVgaSeqReset(dev, nv_crtc->index, false);
213
214 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
215}
216
217static bool
218nv_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
219 struct drm_display_mode *adjusted_mode)
220{
221 return true;
222}
223
224static void
225nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
226{
227 struct drm_device *dev = crtc->dev;
228 struct drm_nouveau_private *dev_priv = dev->dev_private;
229 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
230 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
231 struct drm_framebuffer *fb = crtc->fb;
232
233 /* Calculate our timings */
e5ec882c
FJ		 234 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
235 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
236 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
6ee73861
BS		 237 int horizTotal = (mode->crtc_htotal >> 3) - 5;
238 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
239 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
240 int vertDisplay = mode->crtc_vdisplay - 1;
241 int vertStart = mode->crtc_vsync_start - 1;
242 int vertEnd = mode->crtc_vsync_end - 1;
243 int vertTotal = mode->crtc_vtotal - 2;
244 int vertBlankStart = mode->crtc_vdisplay - 1;
245 int vertBlankEnd = mode->crtc_vtotal - 1;
246
247 struct drm_encoder *encoder;
248 bool fp_output = false;
249
250 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
251 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
252
253 if (encoder->crtc == crtc &&
254 (nv_encoder->dcb->type == OUTPUT_LVDS ||
255 nv_encoder->dcb->type == OUTPUT_TMDS))
256 fp_output = true;
257 }
258
259 if (fp_output) {
260 vertStart = vertTotal - 3;
261 vertEnd = vertTotal - 2;
262 vertBlankStart = vertStart;
263 horizStart = horizTotal - 5;
264 horizEnd = horizTotal - 2;
265 horizBlankEnd = horizTotal + 4;
266#if 0
267 if (dev->overlayAdaptor && dev_priv->card_type >= NV_10)
268 /* This reportedly works around some video overlay bandwidth problems */
269 horizTotal += 2;
270#endif
271 }
272
273 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
274 vertTotal |= 1;
275
276#if 0
277 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
278 ErrorF("horizStart: 0x%X \n", horizStart);
279 ErrorF("horizEnd: 0x%X \n", horizEnd);
280 ErrorF("horizTotal: 0x%X \n", horizTotal);
281 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
282 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
283 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
284 ErrorF("vertStart: 0x%X \n", vertStart);
285 ErrorF("vertEnd: 0x%X \n", vertEnd);
286 ErrorF("vertTotal: 0x%X \n", vertTotal);
287 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
288 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
289#endif
290
291 /*
292 * compute correct Hsync & Vsync polarity
293 */
294 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
295 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
296
297 regp->MiscOutReg = 0x23;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 regp->MiscOutReg |= 0x40;
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 regp->MiscOutReg |= 0x80;
302 } else {
303 int vdisplay = mode->vdisplay;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 vdisplay *= 2;
306 if (mode->vscan > 1)
307 vdisplay *= mode->vscan;
308 if (vdisplay < 400)
309 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
310 else if (vdisplay < 480)
311 regp->MiscOutReg = 0x63; /* -hsync +vsync */
312 else if (vdisplay < 768)
313 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
314 else
315 regp->MiscOutReg = 0x23; /* +hsync +vsync */
316 }
317
318 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2;
319
320 /*
321 * Time Sequencer
322 */
323 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
324 /* 0x20 disables the sequencer */
325 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
326 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
327 else
328 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
329 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
330 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
331 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
332
333 /*
334 * CRTC
335 */
336 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
337 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
338 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
339 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
340 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
341 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
342 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
343 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
344 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
345 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
346 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
347 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
348 (1 << 4) |
349 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
350 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
351 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
352 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
353 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
354 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
355 1 << 6 |
356 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
357 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
359 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
360 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
361 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
364 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
365 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
366 /* framebuffer can be larger than crtc scanout area. */
367 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8;
368 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
370 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
371 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
372 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
373
374 /*
375 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
376 */
377
378 /* framebuffer can be larger than crtc scanout area. */
c1003d9c
FJ		 379 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
380 XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
381 regp->CRTC[NV_CIO_CRE_42] =
382 XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 383 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
384 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
385 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
386 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
387 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
388 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
389 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
390 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
391 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
392 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
393 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
394 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
395 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
396 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
397 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
398
399 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
400 horizTotal = (horizTotal >> 1) & ~1;
401 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
402 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
403 } else
404 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
405
406 /*
407 * Graphics Display Controller
408 */
409 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
410 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
411 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
412 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
413 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
414 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
415 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
416 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
417 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
418
419 regp->Attribute[0] = 0x00; /* standard colormap translation */
420 regp->Attribute[1] = 0x01;
421 regp->Attribute[2] = 0x02;
422 regp->Attribute[3] = 0x03;
423 regp->Attribute[4] = 0x04;
424 regp->Attribute[5] = 0x05;
425 regp->Attribute[6] = 0x06;
426 regp->Attribute[7] = 0x07;
427 regp->Attribute[8] = 0x08;
428 regp->Attribute[9] = 0x09;
429 regp->Attribute[10] = 0x0A;
430 regp->Attribute[11] = 0x0B;
431 regp->Attribute[12] = 0x0C;
432 regp->Attribute[13] = 0x0D;
433 regp->Attribute[14] = 0x0E;
434 regp->Attribute[15] = 0x0F;
435 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
436 /* Non-vga */
437 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
438 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
439 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
440 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
441}
442
443/**
444 * Sets up registers for the given mode/adjusted_mode pair.
445 *
446 * The clocks, CRTCs and outputs attached to this CRTC must be off.
447 *
448 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
449 * be easily turned on/off after this.
450 */
451static void
452nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
453{
454 struct drm_device *dev = crtc->dev;
455 struct drm_nouveau_private *dev_priv = dev->dev_private;
456 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
457 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
458 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
459 struct drm_encoder *encoder;
460 bool lvds_output = false, tmds_output = false, tv_output = false,
461 off_chip_digital = false;
462
463 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
464 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
465 bool digital = false;
466
467 if (encoder->crtc != crtc)
468 continue;
469
470 if (nv_encoder->dcb->type == OUTPUT_LVDS)
471 digital = lvds_output = true;
472 if (nv_encoder->dcb->type == OUTPUT_TV)
473 tv_output = true;
474 if (nv_encoder->dcb->type == OUTPUT_TMDS)
475 digital = tmds_output = true;
476 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
477 off_chip_digital = true;
478 }
479
480 /* Registers not directly related to the (s)vga mode */
481
482 /* What is the meaning of this register? */
483 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
484 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
485
486 regp->crtc_eng_ctrl = 0;
487 /* Except for rare conditions I2C is enabled on the primary crtc */
488 if (nv_crtc->index == 0)
489 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
490#if 0
491 /* Set overlay to desired crtc. */
492 if (dev->overlayAdaptor) {
493 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
494 if (pPriv->overlayCRTC == nv_crtc->index)
495 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
496 }
497#endif
498
499 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
500 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
501 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
502 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
503 if (dev_priv->chipset >= 0x11)
504 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
505 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
506 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
507
508 /* Unblock some timings */
509 regp->CRTC[NV_CIO_CRE_53] = 0;
510 regp->CRTC[NV_CIO_CRE_54] = 0;
511
512 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
513 if (lvds_output)
514 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
515 else if (tmds_output)
516 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
517 else
518 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
519
520 /* These values seem to vary */
521 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
522 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
523
524 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
525
526 /* probably a scratch reg, but kept for cargo-cult purposes:
527 * bit0: crtc0?, head A
528 * bit6: lvds, head A
529 * bit7: (only in X), head A
530 */
531 if (nv_crtc->index == 0)
532 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
533
534 /* The blob seems to take the current value from crtc 0, add 4 to that
535 * and reuse the old value for crtc 1 */
536 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
537 if (!nv_crtc->index)
538 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
539
540 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
541 * 1 << 30 on 0x60.830), for no apparent reason */
542 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
543
4a9f822f
FJ		 544 if (dev_priv->card_type >= NV_30)
545 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
546
6ee73861
BS		 547 regp->crtc_830 = mode->crtc_vdisplay - 3;
548 regp->crtc_834 = mode->crtc_vdisplay - 1;
549
550 if (dev_priv->card_type == NV_40)
551 /* This is what the blob does */
552 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
553
554 if (dev_priv->card_type >= NV_30)
555 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
556
63f7fcfe
FJ		 557 if (dev_priv->card_type >= NV_10)
558 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
559 else
560 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
6ee73861
BS		 561
562 /* Some misc regs */
563 if (dev_priv->card_type == NV_40) {
564 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
565 regp->CRTC[NV_CIO_CRE_86] = 0x1;
566 }
567
568 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8;
569 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
570 if (lvds_output || tmds_output || tv_output)
571 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
572
573 /* Generic PRAMDAC regs */
574
575 if (dev_priv->card_type >= NV_10)
576 /* Only bit that bios and blob set. */
577 regp->nv10_cursync = (1 << 25);
578
579 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
580 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
581 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
582 if (crtc->fb->depth == 16)
583 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
584 if (dev_priv->chipset >= 0x11)
585 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
586
587 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
588 regp->tv_setup = 0;
589
590 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
591
592 /* Some values the blob sets */
593 regp->ramdac_8c0 = 0x100;
594 regp->ramdac_a20 = 0x0;
595 regp->ramdac_a24 = 0xfffff;
596 regp->ramdac_a34 = 0x1;
597}
598
599/**
600 * Sets up registers for the given mode/adjusted_mode pair.
601 *
602 * The clocks, CRTCs and outputs attached to this CRTC must be off.
603 *
604 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
605 * be easily turned on/off after this.
606 */
607static int
608nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
609 struct drm_display_mode *adjusted_mode,
610 int x, int y, struct drm_framebuffer *old_fb)
611{
612 struct drm_device *dev = crtc->dev;
613 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
614 struct drm_nouveau_private *dev_priv = dev->dev_private;
615
ef2bb506 616 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 617 drm_mode_debug_printmodeline(adjusted_mode);
618
619 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
620 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
621
622 nv_crtc_mode_set_vga(crtc, adjusted_mode);
623 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
624 if (dev_priv->card_type == NV_40)
625 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
626 nv_crtc_mode_set_regs(crtc, adjusted_mode);
627 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
628 return 0;
629}
630
631static void nv_crtc_save(struct drm_crtc *crtc)
632{
633 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
634 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
635 struct nv04_mode_state *state = &dev_priv->mode_reg;
636 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
637 struct nv04_mode_state *saved = &dev_priv->saved_reg;
638 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
639
640 if (nv_two_heads(crtc->dev))
641 NVSetOwner(crtc->dev, nv_crtc->index);
642
643 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
644
645 /* init some state to saved value */
646 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
647 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
648 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
649 crtc_state->gpio_ext = crtc_saved->gpio_ext;
650}
651
652static void nv_crtc_restore(struct drm_crtc *crtc)
653{
654 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
655 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
656 int head = nv_crtc->index;
657 uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
658
659 if (nv_two_heads(crtc->dev))
660 NVSetOwner(crtc->dev, head);
661
662 nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg);
663 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
664
665 nv_crtc->last_dpms = NV_DPMS_CLEARED;
666}
667
668static void nv_crtc_prepare(struct drm_crtc *crtc)
669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_nouveau_private *dev_priv = dev->dev_private;
672 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
673 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
674
675 if (nv_two_heads(dev))
676 NVSetOwner(dev, nv_crtc->index);
677
1c180fa5 678 drm_vblank_pre_modeset(dev, nv_crtc->index);
6ee73861
BS		 679 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
680
681 NVBlankScreen(dev, nv_crtc->index, true);
682
25985edc 683 /* Some more preparation. */
6ee73861
BS		 684 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
685 if (dev_priv->card_type == NV_40) {
686 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
687 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
688 }
689}
690
691static void nv_crtc_commit(struct drm_crtc *crtc)
692{
693 struct drm_device *dev = crtc->dev;
694 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
695 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
696 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
697
698 nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg);
699 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
700
701#ifdef __BIG_ENDIAN
702 /* turn on LFB swapping */
703 {
704 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
705 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
706 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
707 }
708#endif
709
710 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1c180fa5 711 drm_vblank_post_modeset(dev, nv_crtc->index);
6ee73861
BS		 712}
713
714static void nv_crtc_destroy(struct drm_crtc *crtc)
715{
716 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
717
ef2bb506 718 NV_DEBUG_KMS(crtc->dev, "\n");
6ee73861
BS		 719
720 if (!nv_crtc)
721 return;
722
723 drm_crtc_cleanup(crtc);
724
9d59e8a1 725 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
6ee73861
BS		 726 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
727 kfree(nv_crtc);
728}
729
730static void
731nv_crtc_gamma_load(struct drm_crtc *crtc)
732{
733 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
734 struct drm_device *dev = nv_crtc->base.dev;
735 struct drm_nouveau_private *dev_priv = dev->dev_private;
736 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
737 int i;
738
739 rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC;
740 for (i = 0; i < 256; i++) {
741 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
742 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
743 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
744 }
745
746 nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg);
747}
748
749static void
7203425a
JS		 750nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
751 uint32_t size)
6ee73861 752{
7203425a 753 int end = (start + size > 256) ? 256 : start + size, i;
6ee73861 754 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861 755
7203425a 756 for (i = start; i < end; i++) {
6ee73861
BS		 757 nv_crtc->lut.r[i] = r[i];
758 nv_crtc->lut.g[i] = g[i];
759 nv_crtc->lut.b[i] = b[i];
760 }
761
762 /* We need to know the depth before we upload, but it's possible to
763 * get called before a framebuffer is bound. If this is the case,
764 * mark the lut values as dirty by setting depth==0, and it'll be
765 * uploaded on the first mode_set_base()
766 */
767 if (!nv_crtc->base.fb) {
768 nv_crtc->lut.depth = 0;
769 return;
770 }
771
772 nv_crtc_gamma_load(crtc);
773}
774
775static int
be64c2bb
CB		 776nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
777 struct drm_framebuffer *passed_fb,
778 int x, int y, bool atomic)
6ee73861
BS		 779{
780 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
781 struct drm_device *dev = crtc->dev;
782 struct drm_nouveau_private *dev_priv = dev->dev_private;
783 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
784 struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
785 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
786 int arb_burst, arb_lwm;
787 int ret;
788
be64c2bb
CB		 789 /* If atomic, we want to switch to the fb we were passed, so
790 * now we update pointers to do that. (We don't pin; just
791 * assume we're already pinned and update the base address.)
792 */
793 if (atomic) {
794 drm_fb = passed_fb;
795 fb = nouveau_framebuffer(passed_fb);
f9ec8f6c 796 } else {
be64c2bb
CB		 797 /* If not atomic, we can go ahead and pin, and unpin the
798 * old fb we were passed.
799 */
800 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
801 if (ret)
802 return ret;
6ee73861 803
be64c2bb
CB		 804 if (passed_fb) {
805 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
806 nouveau_bo_unpin(ofb->nvbo);
807 }
6ee73861
BS		 808 }
809
810 nv_crtc->fb.offset = fb->nvbo->bo.offset;
811
812 if (nv_crtc->lut.depth != drm_fb->depth) {
813 nv_crtc->lut.depth = drm_fb->depth;
814 nv_crtc_gamma_load(crtc);
815 }
816
817 /* Update the framebuffer format. */
818 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
819 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8;
820 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
821 if (crtc->fb->depth == 16)
822 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
823 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
824 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
825 regp->ramdac_gen_ctrl);
826
827 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
828 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
829 XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c
FJ		 830 regp->CRTC[NV_CIO_CRE_42] =
831 XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 832 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
833 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
c1003d9c 834 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
6ee73861
BS		 835
836 /* Update the framebuffer location. */
837 regp->fb_start = nv_crtc->fb.offset & ~3;
838 regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8);
5794b5fd 839 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
6ee73861
BS		 840
841 /* Update the arbitration parameters. */
842 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
843 &arb_burst, &arb_lwm);
844
845 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
846 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
847 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
848 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
849
4295f188 850 if (dev_priv->card_type >= NV_20) {
6ee73861
BS		 851 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
852 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
853 }
854
855 return 0;
856}
857
be64c2bb
CB		 858static int
859nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
860 struct drm_framebuffer *old_fb)
861{
862 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
863}
864
865static int
866nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
867 struct drm_framebuffer *fb,
21c74a8e 868 int x, int y, enum mode_set_atomic state)
be64c2bb 869{
a424d761
CB		 870 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
871 struct drm_device *dev = dev_priv->dev;
872
21c74a8e 873 if (state == ENTER_ATOMIC_MODE_SET)
a424d761
CB		 874 nouveau_fbcon_save_disable_accel(dev);
875 else
876 nouveau_fbcon_restore_accel(dev);
877
be64c2bb
CB		 878 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
879}
880
6ee73861
BS		 881static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
882 struct nouveau_bo *dst)
883{
884 int width = nv_cursor_width(dev);
885 uint32_t pixel;
886 int i, j;
887
888 for (i = 0; i < width; i++) {
889 for (j = 0; j < width; j++) {
890 pixel = nouveau_bo_rd32(src, i*64 + j);
891
892 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
893 | (pixel & 0xf80000) >> 9
894 | (pixel & 0xf800) >> 6
895 | (pixel & 0xf8) >> 3);
896 }
897 }
898}
899
900static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
901 struct nouveau_bo *dst)
902{
903 uint32_t pixel;
904 int alpha, i;
905
906 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
907 * cursors (though NPM in combination with fp dithering may not work on
908 * nv11, from "nv" driver history)
909 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
910 * blob uses, however we get given PM cursors so we use PM mode
911 */
912 for (i = 0; i < 64 * 64; i++) {
913 pixel = nouveau_bo_rd32(src, i);
914
915 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
916 * than" shouldn't happen; fix "equal to" case by adding one to
917 * alpha channel (slightly inaccurate, but so is attempting to
918 * get back to NPM images, due to limits of integer precision)
919 */
920 alpha = pixel >> 24;
921 if (alpha > 0 && alpha < 255)
922 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
923
924#ifdef __BIG_ENDIAN
925 {
926 struct drm_nouveau_private *dev_priv = dev->dev_private;
927
928 if (dev_priv->chipset == 0x11) {
929 pixel = ((pixel & 0x000000ff) << 24) |
930 ((pixel & 0x0000ff00) << 8) |
931 ((pixel & 0x00ff0000) >> 8) |
932 ((pixel & 0xff000000) >> 24);
933 }
934 }
935#endif
936
937 nouveau_bo_wr32(dst, i, pixel);
938 }
939}
940
941static int
942nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
943 uint32_t buffer_handle, uint32_t width, uint32_t height)
944{
945 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
946 struct drm_device *dev = dev_priv->dev;
947 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
948 struct nouveau_bo *cursor = NULL;
949 struct drm_gem_object *gem;
950 int ret = 0;
951
6ee73861
BS		 952 if (!buffer_handle) {
953 nv_crtc->cursor.hide(nv_crtc, true);
954 return 0;
955 }
956
b4fa9d0f
MS		 957 if (width != 64 || height != 64)
958 return -EINVAL;
959
6ee73861
BS		 960 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
961 if (!gem)
bf79cb91 962 return -ENOENT;
6ee73861
BS		 963 cursor = nouveau_gem_object(gem);
964
965 ret = nouveau_bo_map(cursor);
966 if (ret)
967 goto out;
968
969 if (dev_priv->chipset >= 0x11)
970 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
971 else
972 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
973
974 nouveau_bo_unmap(cursor);
975 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
976 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
977 nv_crtc->cursor.show(nv_crtc, true);
978out:
bc9025bd 979 drm_gem_object_unreference_unlocked(gem);
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BS		 980 return ret;
981}
982
983static int
984nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
985{
986 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
987
988 nv_crtc->cursor.set_pos(nv_crtc, x, y);
989 return 0;
990}
991
992static const struct drm_crtc_funcs nv04_crtc_funcs = {
993 .save = nv_crtc_save,
994 .restore = nv_crtc_restore,
995 .cursor_set = nv04_crtc_cursor_set,
996 .cursor_move = nv04_crtc_cursor_move,
997 .gamma_set = nv_crtc_gamma_set,
998 .set_config = drm_crtc_helper_set_config,
332b242f 999 .page_flip = nouveau_crtc_page_flip,
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BS		 1000 .destroy = nv_crtc_destroy,
1001};
1002
1003static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1004 .dpms = nv_crtc_dpms,
1005 .prepare = nv_crtc_prepare,
1006 .commit = nv_crtc_commit,
1007 .mode_fixup = nv_crtc_mode_fixup,
1008 .mode_set = nv_crtc_mode_set,
1009 .mode_set_base = nv04_crtc_mode_set_base,
be64c2bb 1010 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
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BS		 1011 .load_lut = nv_crtc_gamma_load,
1012};
1013
1014int
1015nv04_crtc_create(struct drm_device *dev, int crtc_num)
1016{
1017 struct nouveau_crtc *nv_crtc;
1018 int ret, i;
1019
1020 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1021 if (!nv_crtc)
1022 return -ENOMEM;
1023
1024 for (i = 0; i < 256; i++) {
1025 nv_crtc->lut.r[i] = i << 8;
1026 nv_crtc->lut.g[i] = i << 8;
1027 nv_crtc->lut.b[i] = i << 8;
1028 }
1029 nv_crtc->lut.depth = 0;
1030
1031 nv_crtc->index = crtc_num;
1032 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1033
1034 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
1035 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1036 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1037
1038 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
d550c41e 1039 0, 0x0000, &nv_crtc->cursor.nvbo);
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BS		 1040 if (!ret) {
1041 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
1042 if (!ret)
1043 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1044 if (ret)
1045 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1046 }
1047
1048 nv04_cursor_init(nv_crtc);
1049
1050 return 0;
1051}
1052
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