[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / nv04_fbcon.c

/*
 * Copyright 2009 Ben Skeggs
 * Copyright 2008 Stuart Bennett
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <core/object.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fbcon.h"

int
nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
	struct nouveau_channel *chan = drm->channel;
	int ret;

	ret = RING_SPACE(chan, 4);
	if (ret)
		return ret;

	BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
	OUT_RING(chan, (region->sy << 16) | region->sx);
	OUT_RING(chan, (region->dy << 16) | region->dx);
	OUT_RING(chan, (region->height << 16) | region->width);
	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
	struct nouveau_channel *chan = drm->channel;
	int ret;

	ret = RING_SPACE(chan, 7);
	if (ret)
		return ret;

	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
	OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
	BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
		OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
	else
		OUT_RING(chan, rect->color);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
	OUT_RING(chan, (rect->dx << 16) | rect->dy);
	OUT_RING(chan, (rect->width << 16) | rect->height);
	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
	struct nouveau_channel *chan = drm->channel;
	uint32_t fg;
	uint32_t bg;
	uint32_t dsize;
	uint32_t width;
	uint32_t *data = (uint32_t *)image->data;
	int ret;

	if (image->depth != 1)
		return -ENODEV;

	ret = RING_SPACE(chan, 8);
	if (ret)
		return ret;

	width = ALIGN(image->width, 8);
	dsize = ALIGN(width * image->height, 32) >> 5;

	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
		fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
		bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
	} else {
		fg = image->fg_color;
		bg = image->bg_color;
	}

	BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
	OUT_RING(chan, ((image->dy + image->height) << 16) |
			 ((image->dx + image->width) & 0xffff));
	OUT_RING(chan, bg);
	OUT_RING(chan, fg);
	OUT_RING(chan, (image->height << 16) | width);
	OUT_RING(chan, (image->height << 16) | image->width);
	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));

	while (dsize) {
		int iter_len = dsize > 128 ? 128 : dsize;

		ret = RING_SPACE(chan, iter_len + 1);
		if (ret)
			return ret;

		BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
		OUT_RINGp(chan, data, iter_len);
		data += iter_len;
		dsize -= iter_len;
	}

	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_accel_init(struct fb_info *info)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct drm_device *dev = nfbdev->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_channel *chan = drm->channel;
	struct nvif_device *device = &drm->device;
	int surface_fmt, pattern_fmt, rect_fmt;
	int ret;

	switch (info->var.bits_per_pixel) {
	case 8:
		surface_fmt = 1;
		pattern_fmt = 3;
		rect_fmt = 3;
		break;
	case 16:
		surface_fmt = 4;
		pattern_fmt = 1;
		rect_fmt = 1;
		break;
	case 32:
		switch (info->var.transp.length) {
		case 0: /* depth 24 */
		case 8: /* depth 32 */
			break;
		default:
			return -EINVAL;
		}

		surface_fmt = 6;
		pattern_fmt = 3;
		rect_fmt = 3;
		break;
	default:
		return -EINVAL;
	}

	ret = nvif_object_init(chan->object, NULL, NvCtxSurf2D,
			       device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
			       0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
	if (ret)
		return ret;

	ret = nvif_object_init(chan->object, NULL, NvClipRect, 0x0019, NULL, 0,
			       &nfbdev->clip);
	if (ret)
		return ret;

	ret = nvif_object_init(chan->object, NULL, NvRop, 0x0043, NULL, 0,
			       &nfbdev->rop);
	if (ret)
		return ret;

	ret = nvif_object_init(chan->object, NULL, NvImagePatt, 0x0044, NULL, 0,
			       &nfbdev->patt);
	if (ret)
		return ret;

	ret = nvif_object_init(chan->object, NULL, NvGdiRect, 0x004a, NULL, 0,
			       &nfbdev->gdi);
	if (ret)
		return ret;

	ret = nvif_object_init(chan->object, NULL, NvImageBlit,
			       device->info.chipset >= 0x11 ? 0x009f : 0x005f,
			       NULL, 0, &nfbdev->blit);
	if (ret)
		return ret;

	if (RING_SPACE(chan, 49)) {
		nouveau_fbcon_gpu_lockup(info);
		return 0;
	}

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
	OUT_RING(chan, NvDmaFB);
	OUT_RING(chan, NvDmaFB);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
	OUT_RING(chan, surface_fmt);
	OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvRop);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
	OUT_RING(chan, 0x55);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvImagePatt);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
	OUT_RING(chan, pattern_fmt);
#ifdef __BIG_ENDIAN
	OUT_RING(chan, 2);
#else
	OUT_RING(chan, 1);
#endif
	OUT_RING(chan, 0);
	OUT_RING(chan, 1);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvClipRect);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
	OUT_RING(chan, 0);
	OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);

	BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
	OUT_RING(chan, NvImageBlit);
	BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
	OUT_RING(chan, 3);
	if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
		BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
		OUT_RING(chan, 0);
		OUT_RING(chan, 1);
		OUT_RING(chan, 2);
	}

	BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
	OUT_RING(chan, NvGdiRect);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
	OUT_RING(chan, NvImagePatt);
	OUT_RING(chan, NvRop);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
	OUT_RING(chan, 1);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
	OUT_RING(chan, rect_fmt);
	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
	OUT_RING(chan, 3);

	FIRE_RING(chan);

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Ben Skeggs
	3	* Copyright 2008 Stuart Bennett
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
ebb945a9 BS	25	#include <core/object.h>
	26
	27	#include "nouveau_drm.h"
6ee73861 BS	28	#include "nouveau_dma.h"
	29	#include "nouveau_fbcon.h"
	30
ceed5f30	31	int
6ee73861 BS	32	nv04_fbcon_copyarea(struct fb_info info, const struct fb_copyarea region)
6ee73861 BS	33	{
8be48d92	34	struct nouveau_fbdev *nfbdev = info->par;
77145f1c	35	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
ebb945a9	36	struct nouveau_channel *chan = drm->channel;
ceed5f30	37	int ret;
6ee73861	38
ceed5f30 BS	39	ret = RING_SPACE(chan, 4);
	40	if (ret)
	41	return ret;
6ee73861	42
6d597027	43	BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
6ee73861 BS	44	OUT_RING(chan, (region->sy << 16) \| region->sx);
	45	OUT_RING(chan, (region->dy << 16) \| region->dx);
	46	OUT_RING(chan, (region->height << 16) \| region->width);
	47	FIRE_RING(chan);
ceed5f30	48	return 0;
6ee73861 BS	49	}
6ee73861 BS	50
ceed5f30	51	int
6ee73861 BS	52	nv04_fbcon_fillrect(struct fb_info info, const struct fb_fillrect rect)
6ee73861 BS	53	{
8be48d92	54	struct nouveau_fbdev *nfbdev = info->par;
77145f1c	55	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
ebb945a9	56	struct nouveau_channel *chan = drm->channel;
ceed5f30	57	int ret;
6ee73861	58
ceed5f30 BS	59	ret = RING_SPACE(chan, 7);
	60	if (ret)
	61	return ret;
6ee73861	62
6d597027	63	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
6ee73861	64	OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
6d597027	65	BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
bf5302b9 BS	66	if (info->fix.visual == FB_VISUAL_TRUECOLOR \|\|
	67	info->fix.visual == FB_VISUAL_DIRECTCOLOR)
	68	OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
	69	else
	70	OUT_RING(chan, rect->color);
6d597027	71	BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
6ee73861 BS	72	OUT_RING(chan, (rect->dx << 16) \| rect->dy);
	73	OUT_RING(chan, (rect->width << 16) \| rect->height);
	74	FIRE_RING(chan);
ceed5f30	75	return 0;
6ee73861 BS	76	}
6ee73861 BS	77
ceed5f30	78	int
6ee73861 BS	79	nv04_fbcon_imageblit(struct fb_info info, const struct fb_image image)
6ee73861 BS	80	{
8be48d92	81	struct nouveau_fbdev *nfbdev = info->par;
77145f1c	82	struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
ebb945a9	83	struct nouveau_channel *chan = drm->channel;
6ee73861 BS	84	uint32_t fg;
	85	uint32_t bg;
	86	uint32_t dsize;
	87	uint32_t width;
	88	uint32_t data = (uint32_t )image->data;
ceed5f30	89	int ret;
6ee73861	90
ceed5f30 BS	91	if (image->depth != 1)
ceed5f30 BS	92	return -ENODEV;
6ee73861	93
ceed5f30 BS	94	ret = RING_SPACE(chan, 8);
	95	if (ret)
	96	return ret;
6ee73861	97
c82b88d5 MK	98	width = ALIGN(image->width, 8);
c82b88d5 MK	99	dsize = ALIGN(width * image->height, 32) >> 5;
6ee73861 BS	100
	101	if (info->fix.visual == FB_VISUAL_TRUECOLOR \|\|
	102	info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
	103	fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
	104	bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
	105	} else {
	106	fg = image->fg_color;
	107	bg = image->bg_color;
	108	}
	109
6d597027	110	BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
6ee73861 BS	111	OUT_RING(chan, (image->dy << 16) \| (image->dx & 0xffff));
	112	OUT_RING(chan, ((image->dy + image->height) << 16) \|
	113	((image->dx + image->width) & 0xffff));
	114	OUT_RING(chan, bg);
	115	OUT_RING(chan, fg);
6ee73861	116	OUT_RING(chan, (image->height << 16) \| width);
c82b88d5	117	OUT_RING(chan, (image->height << 16) \| image->width);
6ee73861 BS	118	OUT_RING(chan, (image->dy << 16) \| (image->dx & 0xffff));
	119
	120	while (dsize) {
	121	int iter_len = dsize > 128 ? 128 : dsize;
	122
ceed5f30 BS	123	ret = RING_SPACE(chan, iter_len + 1);
	124	if (ret)
	125	return ret;
6ee73861	126
6d597027	127	BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
6ee73861 BS	128	OUT_RINGp(chan, data, iter_len);
	129	data += iter_len;
	130	dsize -= iter_len;
	131	}
	132
	133	FIRE_RING(chan);
ceed5f30	134	return 0;
6ee73861 BS	135	}
6ee73861 BS	136
6ee73861 BS	137	int
	138	nv04_fbcon_accel_init(struct fb_info *info)
	139	{
8be48d92 DA	140	struct nouveau_fbdev *nfbdev = info->par;
8be48d92 DA	141	struct drm_device *dev = nfbdev->dev;
77145f1c	142	struct nouveau_drm *drm = nouveau_drm(dev);
ebb945a9	143	struct nouveau_channel *chan = drm->channel;
967e7bde	144	struct nvif_device *device = &drm->device;
6ee73861 BS	145	int surface_fmt, pattern_fmt, rect_fmt;
	146	int ret;
	147
	148	switch (info->var.bits_per_pixel) {
	149	case 8:
	150	surface_fmt = 1;
	151	pattern_fmt = 3;
	152	rect_fmt = 3;
	153	break;
	154	case 16:
	155	surface_fmt = 4;
	156	pattern_fmt = 1;
	157	rect_fmt = 1;
	158	break;
	159	case 32:
	160	switch (info->var.transp.length) {
	161	case 0: /* depth 24 */
	162	case 8: /* depth 32 */
	163	break;
	164	default:
	165	return -EINVAL;
	166	}
	167
	168	surface_fmt = 6;
	169	pattern_fmt = 3;
	170	rect_fmt = 3;
	171	break;
	172	default:
	173	return -EINVAL;
	174	}
	175
0ad72863 BS	176	ret = nvif_object_init(chan->object, NULL, NvCtxSurf2D,
	177	device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
	178	0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
6ee73861 BS	179	if (ret)
	180	return ret;
	181
0ad72863 BS	182	ret = nvif_object_init(chan->object, NULL, NvClipRect, 0x0019, NULL, 0,
0ad72863 BS	183	&nfbdev->clip);
6ee73861 BS	184	if (ret)
	185	return ret;
	186
0ad72863 BS	187	ret = nvif_object_init(chan->object, NULL, NvRop, 0x0043, NULL, 0,
0ad72863 BS	188	&nfbdev->rop);
6ee73861 BS	189	if (ret)
	190	return ret;
	191
0ad72863 BS	192	ret = nvif_object_init(chan->object, NULL, NvImagePatt, 0x0044, NULL, 0,
0ad72863 BS	193	&nfbdev->patt);
6ee73861 BS	194	if (ret)
	195	return ret;
	196
0ad72863 BS	197	ret = nvif_object_init(chan->object, NULL, NvGdiRect, 0x004a, NULL, 0,
0ad72863 BS	198	&nfbdev->gdi);
6ee73861 BS	199	if (ret)
	200	return ret;
	201
0ad72863 BS	202	ret = nvif_object_init(chan->object, NULL, NvImageBlit,
	203	device->info.chipset >= 0x11 ? 0x009f : 0x005f,
	204	NULL, 0, &nfbdev->blit);
6ee73861 BS	205	if (ret)
	206	return ret;
	207
	208	if (RING_SPACE(chan, 49)) {
846975a9	209	nouveau_fbcon_gpu_lockup(info);
6ee73861 BS	210	return 0;
	211	}
	212
ebb945a9	213	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
6ee73861	214	OUT_RING(chan, NvCtxSurf2D);
ebb945a9	215	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
6ee73861 BS	216	OUT_RING(chan, NvDmaFB);
6ee73861 BS	217	OUT_RING(chan, NvDmaFB);
ebb945a9	218	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
6ee73861 BS	219	OUT_RING(chan, surface_fmt);
	220	OUT_RING(chan, info->fix.line_length \| (info->fix.line_length << 16));
	221	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	222	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	223
ebb945a9	224	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
6ee73861	225	OUT_RING(chan, NvRop);
ebb945a9	226	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
6ee73861 BS	227	OUT_RING(chan, 0x55);
6ee73861 BS	228
ebb945a9	229	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
6ee73861	230	OUT_RING(chan, NvImagePatt);
ebb945a9	231	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
6ee73861 BS	232	OUT_RING(chan, pattern_fmt);
	233	#ifdef __BIG_ENDIAN
	234	OUT_RING(chan, 2);
	235	#else
	236	OUT_RING(chan, 1);
	237	#endif
	238	OUT_RING(chan, 0);
	239	OUT_RING(chan, 1);
	240	OUT_RING(chan, ~0);
	241	OUT_RING(chan, ~0);
	242	OUT_RING(chan, ~0);
	243	OUT_RING(chan, ~0);
	244
ebb945a9	245	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
6ee73861	246	OUT_RING(chan, NvClipRect);
ebb945a9	247	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
6ee73861 BS	248	OUT_RING(chan, 0);
	249	OUT_RING(chan, (info->var.yres_virtual << 16) \| info->var.xres_virtual);
	250
6d597027	251	BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
6ee73861	252	OUT_RING(chan, NvImageBlit);
6d597027	253	BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
6ee73861	254	OUT_RING(chan, NvCtxSurf2D);
6d597027	255	BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
6ee73861	256	OUT_RING(chan, 3);
967e7bde	257	if (device->info.chipset >= 0x11 /XXX: oclass == 0x009f/) {
b9d9dcda BS	258	BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
	259	OUT_RING(chan, 0);
	260	OUT_RING(chan, 1);
	261	OUT_RING(chan, 2);
	262	}
6ee73861	263
6d597027	264	BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
6ee73861	265	OUT_RING(chan, NvGdiRect);
6d597027	266	BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
6ee73861	267	OUT_RING(chan, NvCtxSurf2D);
6d597027	268	BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
6ee73861 BS	269	OUT_RING(chan, NvImagePatt);
6ee73861 BS	270	OUT_RING(chan, NvRop);
6d597027	271	BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
6ee73861	272	OUT_RING(chan, 1);
6d597027	273	BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
6ee73861	274	OUT_RING(chan, rect_fmt);
6d597027	275	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
6ee73861 BS	276	OUT_RING(chan, 3);
	277
	278	FIRE_RING(chan);
	279
6ee73861 BS	280	return 0;
	281	}
	282