]>
Commit | Line | Data |
---|---|---|
6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2007 Ben Skeggs. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "nouveau_drv.h" | |
29 | #include "nouveau_drm.h" | |
e05c5a31 | 30 | #include "nouveau_ramht.h" |
6ee73861 | 31 | |
e05c5a31 | 32 | #define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE)) |
6ee73861 BS |
33 | #define NV40_RAMFC__SIZE 128 |
34 | ||
35 | int | |
36 | nv40_fifo_create_context(struct nouveau_channel *chan) | |
37 | { | |
38 | struct drm_device *dev = chan->dev; | |
39 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
40 | uint32_t fc = NV40_RAMFC(chan->id); | |
ff9e5279 | 41 | unsigned long flags; |
6ee73861 BS |
42 | int ret; |
43 | ||
44 | ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0, | |
45 | NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC | | |
a8eaebc6 | 46 | NVOBJ_FLAG_ZERO_FREE, &chan->ramfc); |
6ee73861 BS |
47 | if (ret) |
48 | return ret; | |
49 | ||
ff9e5279 MM |
50 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
51 | ||
6ee73861 BS |
52 | nv_wi32(dev, fc + 0, chan->pushbuf_base); |
53 | nv_wi32(dev, fc + 4, chan->pushbuf_base); | |
a8eaebc6 | 54 | nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4); |
6ee73861 BS |
55 | nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
56 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | | |
57 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | | |
58 | #ifdef __BIG_ENDIAN | |
59 | NV_PFIFO_CACHE1_BIG_ENDIAN | | |
60 | #endif | |
61 | 0x30000000 /* no idea.. */); | |
a8eaebc6 | 62 | nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4); |
6ee73861 | 63 | nv_wi32(dev, fc + 60, 0x0001FFFF); |
6ee73861 BS |
64 | |
65 | /* enable the fifo dma operation */ | |
66 | nv_wr32(dev, NV04_PFIFO_MODE, | |
67 | nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id)); | |
ff9e5279 MM |
68 | |
69 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
6ee73861 BS |
70 | return 0; |
71 | } | |
72 | ||
73 | void | |
74 | nv40_fifo_destroy_context(struct nouveau_channel *chan) | |
75 | { | |
76 | struct drm_device *dev = chan->dev; | |
77 | ||
78 | nv_wr32(dev, NV04_PFIFO_MODE, | |
79 | nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id)); | |
80 | ||
a8eaebc6 | 81 | nouveau_gpuobj_ref(NULL, &chan->ramfc); |
6ee73861 BS |
82 | } |
83 | ||
84 | static void | |
85 | nv40_fifo_do_load_context(struct drm_device *dev, int chid) | |
86 | { | |
87 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
88 | uint32_t fc = NV40_RAMFC(chid), tmp, tmp2; | |
89 | ||
6ee73861 BS |
90 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0)); |
91 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4)); | |
92 | nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8)); | |
93 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, nv_ri32(dev, fc + 12)); | |
94 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, nv_ri32(dev, fc + 16)); | |
95 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 20)); | |
96 | ||
97 | /* No idea what 0x2058 is.. */ | |
98 | tmp = nv_ri32(dev, fc + 24); | |
99 | tmp2 = nv_rd32(dev, 0x2058) & 0xFFF; | |
100 | tmp2 |= (tmp & 0x30000000); | |
101 | nv_wr32(dev, 0x2058, tmp2); | |
102 | tmp &= ~0x30000000; | |
103 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, tmp); | |
104 | ||
105 | nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 28)); | |
106 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 32)); | |
107 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 36)); | |
108 | tmp = nv_ri32(dev, fc + 40); | |
109 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp); | |
110 | nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 44)); | |
111 | nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 48)); | |
112 | nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 52)); | |
113 | nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, nv_ri32(dev, fc + 56)); | |
114 | ||
115 | /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */ | |
116 | tmp = nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF; | |
117 | tmp |= nv_ri32(dev, fc + 60) & 0x1FFFF; | |
118 | nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, tmp); | |
119 | ||
120 | nv_wr32(dev, 0x32e4, nv_ri32(dev, fc + 64)); | |
121 | /* NVIDIA does this next line twice... */ | |
122 | nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68)); | |
123 | nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76)); | |
124 | nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80)); | |
125 | ||
6ee73861 BS |
126 | nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0); |
127 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0); | |
128 | } | |
129 | ||
130 | int | |
131 | nv40_fifo_load_context(struct nouveau_channel *chan) | |
132 | { | |
133 | struct drm_device *dev = chan->dev; | |
134 | uint32_t tmp; | |
135 | ||
136 | nv40_fifo_do_load_context(dev, chan->id); | |
137 | ||
138 | /* Set channel active, and in DMA mode */ | |
139 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, | |
140 | NV40_PFIFO_CACHE1_PUSH1_DMA | chan->id); | |
141 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1); | |
142 | ||
143 | /* Reset DMA_CTL_AT_INFO to INVALID */ | |
144 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31); | |
145 | nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | int | |
151 | nv40_fifo_unload_context(struct drm_device *dev) | |
152 | { | |
153 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
154 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | |
155 | uint32_t fc, tmp; | |
156 | int chid; | |
157 | ||
158 | chid = pfifo->channel_id(dev); | |
159 | if (chid < 0 || chid >= dev_priv->engine.fifo.channels) | |
160 | return 0; | |
161 | fc = NV40_RAMFC(chid); | |
162 | ||
6ee73861 BS |
163 | nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT)); |
164 | nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET)); | |
165 | nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT)); | |
166 | nv_wi32(dev, fc + 12, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE)); | |
167 | nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT)); | |
168 | nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE)); | |
169 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH); | |
170 | tmp |= nv_rd32(dev, 0x2058) & 0x30000000; | |
171 | nv_wi32(dev, fc + 24, tmp); | |
172 | nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE)); | |
173 | nv_wi32(dev, fc + 32, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1)); | |
174 | nv_wi32(dev, fc + 36, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE)); | |
175 | tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP); | |
176 | nv_wi32(dev, fc + 40, tmp); | |
177 | nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT)); | |
178 | nv_wi32(dev, fc + 48, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE)); | |
179 | /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something | |
180 | * more involved depending on the value of 0x3228? | |
181 | */ | |
182 | nv_wi32(dev, fc + 52, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET)); | |
183 | nv_wi32(dev, fc + 56, nv_rd32(dev, NV40_PFIFO_GRCTX_INSTANCE)); | |
184 | nv_wi32(dev, fc + 60, nv_rd32(dev, NV04_PFIFO_DMA_TIMESLICE) & 0x1ffff); | |
185 | /* No idea what the below is for exactly, ripped from a mmio-trace */ | |
186 | nv_wi32(dev, fc + 64, nv_rd32(dev, NV40_PFIFO_UNK32E4)); | |
187 | /* NVIDIA do this next line twice.. bug? */ | |
188 | nv_wi32(dev, fc + 68, nv_rd32(dev, 0x32e8)); | |
189 | nv_wi32(dev, fc + 76, nv_rd32(dev, 0x2088)); | |
190 | nv_wi32(dev, fc + 80, nv_rd32(dev, 0x3300)); | |
191 | #if 0 /* no real idea which is PUT/GET in UNK_48.. */ | |
192 | tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_GET); | |
193 | tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16); | |
194 | nv_wi32(dev, fc + 72, tmp); | |
195 | #endif | |
6ee73861 BS |
196 | |
197 | nv40_fifo_do_load_context(dev, pfifo->channels - 1); | |
198 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, | |
199 | NV40_PFIFO_CACHE1_PUSH1_DMA | (pfifo->channels - 1)); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static void | |
204 | nv40_fifo_init_reset(struct drm_device *dev) | |
205 | { | |
206 | int i; | |
207 | ||
208 | nv_wr32(dev, NV03_PMC_ENABLE, | |
209 | nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO); | |
210 | nv_wr32(dev, NV03_PMC_ENABLE, | |
211 | nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); | |
212 | ||
213 | nv_wr32(dev, 0x003224, 0x000f0078); | |
214 | nv_wr32(dev, 0x003210, 0x00000000); | |
215 | nv_wr32(dev, 0x003270, 0x00000000); | |
216 | nv_wr32(dev, 0x003240, 0x00000000); | |
217 | nv_wr32(dev, 0x003244, 0x00000000); | |
218 | nv_wr32(dev, 0x003258, 0x00000000); | |
219 | nv_wr32(dev, 0x002504, 0x00000000); | |
220 | for (i = 0; i < 16; i++) | |
221 | nv_wr32(dev, 0x002510 + (i * 4), 0x00000000); | |
222 | nv_wr32(dev, 0x00250c, 0x0000ffff); | |
223 | nv_wr32(dev, 0x002048, 0x00000000); | |
224 | nv_wr32(dev, 0x003228, 0x00000000); | |
225 | nv_wr32(dev, 0x0032e8, 0x00000000); | |
226 | nv_wr32(dev, 0x002410, 0x00000000); | |
227 | nv_wr32(dev, 0x002420, 0x00000000); | |
228 | nv_wr32(dev, 0x002058, 0x00000001); | |
229 | nv_wr32(dev, 0x00221c, 0x00000000); | |
230 | /* something with 0x2084, read/modify/write, no change */ | |
231 | nv_wr32(dev, 0x002040, 0x000000ff); | |
232 | nv_wr32(dev, 0x002500, 0x00000000); | |
233 | nv_wr32(dev, 0x003200, 0x00000000); | |
234 | ||
235 | nv_wr32(dev, NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff); | |
236 | } | |
237 | ||
238 | static void | |
239 | nv40_fifo_init_ramxx(struct drm_device *dev) | |
240 | { | |
241 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
242 | ||
243 | nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | | |
e05c5a31 BS |
244 | ((dev_priv->ramht->bits - 9) << 16) | |
245 | (dev_priv->ramht->gpuobj->pinst >> 8)); | |
246 | nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8); | |
6ee73861 BS |
247 | |
248 | switch (dev_priv->chipset) { | |
249 | case 0x47: | |
250 | case 0x49: | |
251 | case 0x4b: | |
252 | nv_wr32(dev, 0x2230, 1); | |
253 | break; | |
254 | default: | |
255 | break; | |
256 | } | |
257 | ||
258 | switch (dev_priv->chipset) { | |
259 | case 0x40: | |
260 | case 0x41: | |
261 | case 0x42: | |
262 | case 0x43: | |
263 | case 0x45: | |
264 | case 0x47: | |
265 | case 0x48: | |
266 | case 0x49: | |
267 | case 0x4b: | |
268 | nv_wr32(dev, NV40_PFIFO_RAMFC, 0x30002); | |
269 | break; | |
270 | default: | |
271 | nv_wr32(dev, 0x2230, 0); | |
272 | nv_wr32(dev, NV40_PFIFO_RAMFC, | |
a76fb4e8 | 273 | ((dev_priv->vram_size - 512 * 1024 + |
e05c5a31 | 274 | dev_priv->ramfc->pinst) >> 16) | (3 << 16)); |
6ee73861 BS |
275 | break; |
276 | } | |
277 | } | |
278 | ||
279 | static void | |
280 | nv40_fifo_init_intr(struct drm_device *dev) | |
281 | { | |
282 | nv_wr32(dev, 0x002100, 0xffffffff); | |
283 | nv_wr32(dev, 0x002140, 0xffffffff); | |
284 | } | |
285 | ||
286 | int | |
287 | nv40_fifo_init(struct drm_device *dev) | |
288 | { | |
289 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
290 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | |
291 | int i; | |
292 | ||
293 | nv40_fifo_init_reset(dev); | |
294 | nv40_fifo_init_ramxx(dev); | |
295 | ||
296 | nv40_fifo_do_load_context(dev, pfifo->channels - 1); | |
297 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); | |
298 | ||
299 | nv40_fifo_init_intr(dev); | |
300 | pfifo->enable(dev); | |
301 | pfifo->reassign(dev, true); | |
302 | ||
303 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
304 | if (dev_priv->fifos[i]) { | |
305 | uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE); | |
306 | nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i)); | |
307 | } | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } |