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drm/nouveau: move master modesetting init to nouveau_display
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nv50_crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm_mode.h"
29#include "drm_crtc_helper.h"
30
31#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32#include "nouveau_reg.h"
33#include "nouveau_drv.h"
34#include "nouveau_hw.h"
35#include "nouveau_encoder.h"
36#include "nouveau_crtc.h"
37#include "nouveau_fb.h"
38#include "nouveau_connector.h"
39#include "nv50_display.h"
40
549cd872
BS		 41static int
42nv50_crtc_wait_complete(struct drm_crtc *crtc)
43{
44 struct drm_device *dev = crtc->dev;
45 struct drm_nouveau_private *dev_priv = dev->dev_private;
46 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
47 struct nv50_display *disp = nv50_display(dev);
48 struct nouveau_channel *evo = disp->master;
49 u64 start;
50 int ret;
51
52 ret = RING_SPACE(evo, 6);
53 if (ret)
54 return ret;
55 BEGIN_RING(evo, 0, 0x0084, 1);
56 OUT_RING (evo, 0x80000000);
57 BEGIN_RING(evo, 0, 0x0080, 1);
58 OUT_RING (evo, 0);
59 BEGIN_RING(evo, 0, 0x0084, 1);
60 OUT_RING (evo, 0x00000000);
61
62 nv_wo32(disp->ntfy, 0x000, 0x00000000);
63 FIRE_RING (evo);
64
65 start = ptimer->read(dev);
66 do {
67 if (nv_ro32(disp->ntfy, 0x000))
68 return 0;
69 } while (ptimer->read(dev) - start < 2000000000ULL);
70
71 return -EBUSY;
72}
73
6ee73861
BS		 74static void
75nv50_crtc_lut_load(struct drm_crtc *crtc)
76{
77 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
78 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
79 int i;
80
ef2bb506 81 NV_DEBUG_KMS(crtc->dev, "\n");
6ee73861
BS		 82
83 for (i = 0; i < 256; i++) {
84 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
85 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
86 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
87 }
88
89 if (nv_crtc->lut.depth == 30) {
90 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
91 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
92 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
93 }
94}
95
96int
97nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
98{
99 struct drm_device *dev = nv_crtc->base.dev;
100 struct drm_nouveau_private *dev_priv = dev->dev_private;
59c0f578 101 struct nouveau_channel *evo = nv50_display(dev)->master;
6ee73861
BS		 102 int index = nv_crtc->index, ret;
103
ef2bb506
MM		 104 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
105 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
6ee73861
BS		 106
107 if (blanked) {
108 nv_crtc->cursor.hide(nv_crtc, false);
109
110 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
111 if (ret) {
112 NV_ERROR(dev, "no space while blanking crtc\n");
113 return ret;
114 }
115 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
116 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
117 OUT_RING(evo, 0);
118 if (dev_priv->chipset != 0x50) {
119 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
120 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
121 }
122
123 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
124 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
125 } else {
126 if (nv_crtc->cursor.visible)
127 nv_crtc->cursor.show(nv_crtc, false);
128 else
129 nv_crtc->cursor.hide(nv_crtc, false);
130
131 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
132 if (ret) {
133 NV_ERROR(dev, "no space while unblanking crtc\n");
134 return ret;
135 }
136 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
137 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
138 NV50_EVO_CRTC_CLUT_MODE_OFF :
139 NV50_EVO_CRTC_CLUT_MODE_ON);
180cc306 140 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8);
6ee73861
BS		 141 if (dev_priv->chipset != 0x50) {
142 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
143 OUT_RING(evo, NvEvoVRAM);
144 }
145
146 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
147 OUT_RING(evo, nv_crtc->fb.offset >> 8);
148 OUT_RING(evo, 0);
149 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
150 if (dev_priv->chipset != 0x50)
6d86951a
BS		 151 if (nv_crtc->fb.tile_flags == 0x7a00 ||
152 nv_crtc->fb.tile_flags == 0xfe00)
6ee73861
BS		 153 OUT_RING(evo, NvEvoFB32);
154 else
155 if (nv_crtc->fb.tile_flags == 0x7000)
156 OUT_RING(evo, NvEvoFB16);
157 else
6d86951a 158 OUT_RING(evo, NvEvoVRAM_LP);
6ee73861 159 else
6d86951a 160 OUT_RING(evo, NvEvoVRAM_LP);
6ee73861
BS		 161 }
162
163 nv_crtc->fb.blanked = blanked;
164 return 0;
165}
166
167static int
168nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
169{
170 struct drm_device *dev = nv_crtc->base.dev;
59c0f578 171 struct nouveau_channel *evo = nv50_display(dev)->master;
6ee73861
BS		 172 int ret;
173
ef2bb506 174 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 175
176 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
177 if (ret) {
178 NV_ERROR(dev, "no space while setting dither\n");
179 return ret;
180 }
181
182 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
183 if (on)
184 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
185 else
186 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
187
188 if (update) {
189 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
190 OUT_RING(evo, 0);
191 FIRE_RING(evo);
192 }
193
194 return 0;
195}
196
197struct nouveau_connector *
198nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
199{
200 struct drm_device *dev = nv_crtc->base.dev;
201 struct drm_connector *connector;
202 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
203
204 /* The safest approach is to find an encoder with the right crtc, that
205 * is also linked to a connector. */
206 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
207 if (connector->encoder)
208 if (connector->encoder->crtc == crtc)
209 return nouveau_connector(connector);
210 }
211
212 return NULL;
213}
214
215static int
216nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
217{
218 struct nouveau_connector *nv_connector =
219 nouveau_crtc_connector_get(nv_crtc);
549cd872
BS		 220 struct drm_crtc *crtc = &nv_crtc->base;
221 struct drm_device *dev = crtc->dev;
59c0f578 222 struct nouveau_channel *evo = nv50_display(dev)->master;
6ee73861 223 struct drm_display_mode *native_mode = NULL;
549cd872 224 struct drm_display_mode *mode = &crtc->mode;
6ee73861
BS		 225 uint32_t outX, outY, horiz, vert;
226 int ret;
227
ef2bb506 228 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 229
230 switch (scaling_mode) {
231 case DRM_MODE_SCALE_NONE:
232 break;
233 default:
234 if (!nv_connector || !nv_connector->native_mode) {
235 NV_ERROR(dev, "No native mode, forcing panel scaling\n");
236 scaling_mode = DRM_MODE_SCALE_NONE;
237 } else {
238 native_mode = nv_connector->native_mode;
239 }
240 break;
241 }
242
243 switch (scaling_mode) {
244 case DRM_MODE_SCALE_ASPECT:
245 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
246 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
247
248 if (vert > horiz) {
249 outX = (mode->hdisplay * horiz) >> 19;
250 outY = (mode->vdisplay * horiz) >> 19;
251 } else {
252 outX = (mode->hdisplay * vert) >> 19;
253 outY = (mode->vdisplay * vert) >> 19;
254 }
255 break;
256 case DRM_MODE_SCALE_FULLSCREEN:
257 outX = native_mode->hdisplay;
258 outY = native_mode->vdisplay;
259 break;
260 case DRM_MODE_SCALE_CENTER:
261 case DRM_MODE_SCALE_NONE:
262 default:
263 outX = mode->hdisplay;
264 outY = mode->vdisplay;
265 break;
266 }
267
549cd872 268 ret = RING_SPACE(evo, 5);
6ee73861
BS		 269 if (ret)
270 return ret;
271
272 /* Got a better name for SCALER_ACTIVE? */
273 /* One day i've got to really figure out why this is needed. */
274 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
275 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
276 (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
277 mode->hdisplay != outX || mode->vdisplay != outY) {
278 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
279 } else {
280 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
281 }
282
283 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
284 OUT_RING(evo, outY << 16 | outX);
285 OUT_RING(evo, outY << 16 | outX);
286
287 if (update) {
549cd872
BS		 288 nv50_display_flip_stop(crtc);
289 nv50_crtc_wait_complete(crtc);
290 nv50_display_flip_next(crtc, crtc->fb, NULL);
6ee73861
BS		 291 }
292
293 return 0;
294}
295
296int
297nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
298{
1ac7b528 299 struct drm_nouveau_private *dev_priv = dev->dev_private;
e9ebb68b 300 struct pll_lims pll;
5b32165b 301 uint32_t reg1, reg2;
e9ebb68b 302 int ret, N1, M1, N2, M2, P;
6ee73861 303
5b32165b 304 ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
6ee73861
BS		 305 if (ret)
306 return ret;
307
e9ebb68b
BS		 308 if (pll.vco2.maxfreq) {
309 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
310 if (ret <= 0)
311 return 0;
6ee73861 312
17b96cc3 313 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
e9ebb68b
BS		 314 pclk, ret, N1, M1, N2, M2, P);
315
5b32165b
BS		 316 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
317 reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
318 nv_wr32(dev, pll.reg + 0, 0x10000611);
319 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
320 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
1ac7b528
BS		 321 } else
322 if (dev_priv->chipset < NV_C0) {
52eba8dd 323 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
e9ebb68b
BS		 324 if (ret <= 0)
325 return 0;
326
327 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
328 pclk, ret, N1, N2, M1, P);
17b96cc3 329
5b32165b
BS		 330 reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
331 nv_wr32(dev, pll.reg + 0, 0x50000610);
332 nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
333 nv_wr32(dev, pll.reg + 8, N2);
1ac7b528 334 } else {
52eba8dd 335 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
1ac7b528
BS		 336 if (ret <= 0)
337 return 0;
338
339 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
340 pclk, ret, N1, N2, M1, P);
341
5b32165b
BS		 342 nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
343 nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
344 nv_wr32(dev, pll.reg + 0x10, N2 << 16);
6ee73861
BS		 345 }
346
347 return 0;
348}
349
350static void
351nv50_crtc_destroy(struct drm_crtc *crtc)
352{
dd19e44b
MS		 353 struct drm_device *dev;
354 struct nouveau_crtc *nv_crtc;
6ee73861
BS		 355
356 if (!crtc)
357 return;
358
dd19e44b
MS		 359 dev = crtc->dev;
360 nv_crtc = nouveau_crtc(crtc);
361
362 NV_DEBUG_KMS(dev, "\n");
363
6ee73861
BS		 364 drm_crtc_cleanup(&nv_crtc->base);
365
9d59e8a1 366 nouveau_bo_unmap(nv_crtc->lut.nvbo);
6ee73861 367 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
9d59e8a1 368 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
6ee73861
BS		 369 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
370 kfree(nv_crtc->mode);
371 kfree(nv_crtc);
372}
373
374int
375nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
376 uint32_t buffer_handle, uint32_t width, uint32_t height)
377{
378 struct drm_device *dev = crtc->dev;
6ee73861
BS		 379 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
380 struct nouveau_bo *cursor = NULL;
381 struct drm_gem_object *gem;
382 int ret = 0, i;
383
6ee73861
BS		 384 if (!buffer_handle) {
385 nv_crtc->cursor.hide(nv_crtc, true);
386 return 0;
387 }
388
b4fa9d0f
MS		 389 if (width != 64 || height != 64)
390 return -EINVAL;
391
6ee73861
BS		 392 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
393 if (!gem)
bf79cb91 394 return -ENOENT;
6ee73861
BS		 395 cursor = nouveau_gem_object(gem);
396
397 ret = nouveau_bo_map(cursor);
398 if (ret)
399 goto out;
400
401 /* The simple will do for now. */
402 for (i = 0; i < 64 * 64; i++)
403 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
404
405 nouveau_bo_unmap(cursor);
406
180cc306 407 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset);
6ee73861
BS		 408 nv_crtc->cursor.show(nv_crtc, true);
409
410out:
bc9025bd 411 drm_gem_object_unreference_unlocked(gem);
6ee73861
BS		 412 return ret;
413}
414
415int
416nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
417{
418 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
419
420 nv_crtc->cursor.set_pos(nv_crtc, x, y);
421 return 0;
422}
423
424static void
425nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
7203425a 426 uint32_t start, uint32_t size)
6ee73861 427{
7203425a 428 int end = (start + size > 256) ? 256 : start + size, i;
6ee73861 429 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861 430
7203425a 431 for (i = start; i < end; i++) {
6ee73861
BS		 432 nv_crtc->lut.r[i] = r[i];
433 nv_crtc->lut.g[i] = g[i];
434 nv_crtc->lut.b[i] = b[i];
435 }
436
437 /* We need to know the depth before we upload, but it's possible to
438 * get called before a framebuffer is bound. If this is the case,
439 * mark the lut values as dirty by setting depth==0, and it'll be
440 * uploaded on the first mode_set_base()
441 */
442 if (!nv_crtc->base.fb) {
443 nv_crtc->lut.depth = 0;
444 return;
445 }
446
447 nv50_crtc_lut_load(crtc);
448}
449
450static void
451nv50_crtc_save(struct drm_crtc *crtc)
452{
453 NV_ERROR(crtc->dev, "!!\n");
454}
455
456static void
457nv50_crtc_restore(struct drm_crtc *crtc)
458{
459 NV_ERROR(crtc->dev, "!!\n");
460}
461
462static const struct drm_crtc_funcs nv50_crtc_funcs = {
463 .save = nv50_crtc_save,
464 .restore = nv50_crtc_restore,
465 .cursor_set = nv50_crtc_cursor_set,
466 .cursor_move = nv50_crtc_cursor_move,
467 .gamma_set = nv50_crtc_gamma_set,
468 .set_config = drm_crtc_helper_set_config,
332b242f 469 .page_flip = nouveau_crtc_page_flip,
6ee73861
BS		 470 .destroy = nv50_crtc_destroy,
471};
472
473static void
474nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
475{
476}
477
478static void
479nv50_crtc_prepare(struct drm_crtc *crtc)
480{
481 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
482 struct drm_device *dev = crtc->dev;
6ee73861 483
ef2bb506 484 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861 485
1d3fac0c 486 nv50_display_flip_stop(crtc);
1c180fa5 487 drm_vblank_pre_modeset(dev, nv_crtc->index);
6ee73861
BS		 488 nv50_crtc_blank(nv_crtc, true);
489}
490
491static void
492nv50_crtc_commit(struct drm_crtc *crtc)
493{
6ee73861 494 struct drm_device *dev = crtc->dev;
6ee73861 495 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861 496
ef2bb506 497 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861
BS		 498
499 nv50_crtc_blank(nv_crtc, false);
1c180fa5 500 drm_vblank_post_modeset(dev, nv_crtc->index);
60f60bf1 501 nv50_crtc_wait_complete(crtc);
1d3fac0c 502 nv50_display_flip_next(crtc, crtc->fb, NULL);
6ee73861
BS		 503}
504
505static bool
506nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
507 struct drm_display_mode *adjusted_mode)
508{
509 return true;
510}
511
512static int
be64c2bb
CB		 513nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
514 struct drm_framebuffer *passed_fb,
60f60bf1 515 int x, int y, bool atomic)
6ee73861
BS		 516{
517 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
518 struct drm_device *dev = nv_crtc->base.dev;
519 struct drm_nouveau_private *dev_priv = dev->dev_private;
59c0f578 520 struct nouveau_channel *evo = nv50_display(dev)->master;
ffbc559b
EV		 521 struct drm_framebuffer *drm_fb;
522 struct nouveau_framebuffer *fb;
45c4e0aa 523 int ret;
6ee73861 524
ef2bb506 525 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861 526
ffbc559b
EV		 527 /* no fb bound */
528 if (!atomic && !crtc->fb) {
529 NV_DEBUG_KMS(dev, "No FB bound\n");
530 return 0;
531 }
532
be64c2bb
CB		 533 /* If atomic, we want to switch to the fb we were passed, so
534 * now we update pointers to do that. (We don't pin; just
535 * assume we're already pinned and update the base address.)
536 */
537 if (atomic) {
538 drm_fb = passed_fb;
539 fb = nouveau_framebuffer(passed_fb);
f9ec8f6c 540 } else {
ffbc559b
EV		 541 drm_fb = crtc->fb;
542 fb = nouveau_framebuffer(crtc->fb);
be64c2bb
CB		 543 /* If not atomic, we can go ahead and pin, and unpin the
544 * old fb we were passed.
545 */
546 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
547 if (ret)
548 return ret;
549
550 if (passed_fb) {
551 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
552 nouveau_bo_unpin(ofb->nvbo);
553 }
554 }
555
180cc306 556 nv_crtc->fb.offset = fb->nvbo->bo.offset;
f13b3263 557 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo);
6ee73861
BS		 558 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
559 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
560 ret = RING_SPACE(evo, 2);
561 if (ret)
562 return ret;
563
564 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
45c4e0aa 565 OUT_RING (evo, fb->r_dma);
6ee73861
BS		 566 }
567
568 ret = RING_SPACE(evo, 12);
569 if (ret)
570 return ret;
571
572 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
45c4e0aa
BS		 573 OUT_RING (evo, nv_crtc->fb.offset >> 8);
574 OUT_RING (evo, 0);
575 OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width);
576 OUT_RING (evo, fb->r_pitch);
577 OUT_RING (evo, fb->r_format);
6ee73861
BS		 578
579 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
45c4e0aa
BS		 580 OUT_RING (evo, fb->base.depth == 8 ?
581 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
6ee73861
BS		 582
583 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
45c4e0aa 584 OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
6ee73861 585 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
45c4e0aa 586 OUT_RING (evo, (y << 16) | x);
6ee73861
BS		 587
588 if (nv_crtc->lut.depth != fb->base.depth) {
589 nv_crtc->lut.depth = fb->base.depth;
590 nv50_crtc_lut_load(crtc);
591 }
592
6ee73861
BS		 593 return 0;
594}
595
596static int
597nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
598 struct drm_display_mode *adjusted_mode, int x, int y,
599 struct drm_framebuffer *old_fb)
600{
601 struct drm_device *dev = crtc->dev;
59c0f578 602 struct nouveau_channel *evo = nv50_display(dev)->master;
6ee73861
BS		 603 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
604 struct nouveau_connector *nv_connector = NULL;
605 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
606 uint32_t hunk1, vunk1, vunk2a, vunk2b;
607 int ret;
608
609 /* Find the connector attached to this CRTC */
610 nv_connector = nouveau_crtc_connector_get(nv_crtc);
611
612 *nv_crtc->mode = *adjusted_mode;
613
ef2bb506 614 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861
BS		 615
616 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
617 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
618 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
619 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
620 /* I can't give this a proper name, anyone else can? */
621 hunk1 = adjusted_mode->htotal -
622 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
623 vunk1 = adjusted_mode->vtotal -
624 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
625 /* Another strange value, this time only for interlaced adjusted_modes. */
626 vunk2a = 2 * adjusted_mode->vtotal -
627 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
628 vunk2b = adjusted_mode->vtotal -
629 adjusted_mode->vsync_start + adjusted_mode->vtotal;
630
631 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
632 vsync_dur /= 2;
633 vsync_start_to_end /= 2;
634 vunk1 /= 2;
635 vunk2a /= 2;
636 vunk2b /= 2;
637 /* magic */
638 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
639 vsync_start_to_end -= 1;
640 vunk1 -= 1;
641 vunk2a -= 1;
642 vunk2b -= 1;
643 }
644 }
645
646 ret = RING_SPACE(evo, 17);
647 if (ret)
648 return ret;
649
650 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
651 OUT_RING(evo, adjusted_mode->clock | 0x800000);
652 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
653
654 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
655 OUT_RING(evo, 0);
656 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
657 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
658 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
659 (hsync_start_to_end - 1));
660 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
661
662 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
663 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
664 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
665 } else {
666 OUT_RING(evo, 0);
667 OUT_RING(evo, 0);
668 }
669
670 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
671 OUT_RING(evo, 0);
672
673 /* This is the actual resolution of the mode. */
674 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
675 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
676 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
677 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
678
679 nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
680 nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
681
60f60bf1 682 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
6ee73861
BS		 683}
684
685static int
686nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
687 struct drm_framebuffer *old_fb)
688{
60f60bf1
BS		 689 int ret;
690
1d3fac0c 691 nv50_display_flip_stop(crtc);
60f60bf1
BS		 692 ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
693 if (ret)
694 return ret;
695
1d3fac0c
BS		 696 ret = nv50_crtc_wait_complete(crtc);
697 if (ret)
698 return ret;
699
700 return nv50_display_flip_next(crtc, crtc->fb, NULL);
be64c2bb
CB		 701}
702
703static int
704nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
705 struct drm_framebuffer *fb,
21c74a8e 706 int x, int y, enum mode_set_atomic state)
be64c2bb 707{
60f60bf1
BS		 708 int ret;
709
1d3fac0c 710 nv50_display_flip_stop(crtc);
60f60bf1
BS		 711 ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true);
712 if (ret)
713 return ret;
714
715 return nv50_crtc_wait_complete(crtc);
6ee73861
BS		 716}
717
718static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
719 .dpms = nv50_crtc_dpms,
720 .prepare = nv50_crtc_prepare,
721 .commit = nv50_crtc_commit,
722 .mode_fixup = nv50_crtc_mode_fixup,
723 .mode_set = nv50_crtc_mode_set,
724 .mode_set_base = nv50_crtc_mode_set_base,
be64c2bb 725 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
6ee73861
BS		 726 .load_lut = nv50_crtc_lut_load,
727};
728
729int
730nv50_crtc_create(struct drm_device *dev, int index)
731{
732 struct nouveau_crtc *nv_crtc = NULL;
733 int ret, i;
734
ef2bb506 735 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 736
737 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
738 if (!nv_crtc)
739 return -ENOMEM;
740
741 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
742 if (!nv_crtc->mode) {
743 kfree(nv_crtc);
744 return -ENOMEM;
745 }
746
747 /* Default CLUT parameters, will be activated on the hw upon
748 * first mode set.
749 */
750 for (i = 0; i < 256; i++) {
751 nv_crtc->lut.r[i] = i << 8;
752 nv_crtc->lut.g[i] = i << 8;
753 nv_crtc->lut.b[i] = i << 8;
754 }
755 nv_crtc->lut.depth = 0;
756
7375c95b 757 ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM,
d550c41e 758 0, 0x0000, &nv_crtc->lut.nvbo);
6ee73861
BS		 759 if (!ret) {
760 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
761 if (!ret)
762 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
763 if (ret)
764 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
765 }
766
767 if (ret) {
768 kfree(nv_crtc->mode);
769 kfree(nv_crtc);
770 return ret;
771 }
772
773 nv_crtc->index = index;
774
775 /* set function pointers */
776 nv_crtc->set_dither = nv50_crtc_set_dither;
777 nv_crtc->set_scale = nv50_crtc_set_scale;
778
779 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
780 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
781 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
782
7375c95b 783 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
d550c41e 784 0, 0x0000, &nv_crtc->cursor.nvbo);
6ee73861
BS		 785 if (!ret) {
786 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
787 if (!ret)
788 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
789 if (ret)
790 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
791 }
792
793 nv50_cursor_init(nv_crtc);
794 return 0;
795}
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