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Commit | Line | Data |
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56d237d2 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 | 27 | #include <drm/drmP.h> |
ad633619 | 28 | #include <drm/drm_atomic.h> |
973f10c2 | 29 | #include <drm/drm_atomic_helper.h> |
760285e7 | 30 | #include <drm/drm_crtc_helper.h> |
4874322e | 31 | #include <drm/drm_dp_helper.h> |
b516a9ef | 32 | #include <drm/drm_fb_helper.h> |
ad633619 | 33 | #include <drm/drm_plane_helper.h> |
26f6d88b | 34 | |
fdb751ef | 35 | #include <nvif/class.h> |
845f2725 | 36 | #include <nvif/cl0002.h> |
7568b106 BS |
37 | #include <nvif/cl5070.h> |
38 | #include <nvif/cl507a.h> | |
39 | #include <nvif/cl507b.h> | |
40 | #include <nvif/cl507c.h> | |
41 | #include <nvif/cl507d.h> | |
42 | #include <nvif/cl507e.h> | |
973f10c2 | 43 | #include <nvif/event.h> |
fdb751ef | 44 | |
4dc28134 | 45 | #include "nouveau_drv.h" |
77145f1c BS |
46 | #include "nouveau_dma.h" |
47 | #include "nouveau_gem.h" | |
26f6d88b BS |
48 | #include "nouveau_connector.h" |
49 | #include "nouveau_encoder.h" | |
50 | #include "nouveau_crtc.h" | |
f589be88 | 51 | #include "nouveau_fence.h" |
839ca903 | 52 | #include "nouveau_fbcon.h" |
3a89cd02 | 53 | #include "nv50_display.h" |
26f6d88b | 54 | |
8a46438a BS |
55 | #define EVO_DMA_NR 9 |
56 | ||
bdb8c212 | 57 | #define EVO_MASTER (0x00) |
a63a97eb | 58 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
59 | #define EVO_OVLY(c) (0x05 + (c)) |
60 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
61 | #define EVO_CURS(c) (0x0d + (c)) |
62 | ||
816af2f2 BS |
63 | /* offsets in shared sync bo of various structures */ |
64 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
65 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
66 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
67 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
973f10c2 BS |
68 | #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20) |
69 | #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30) | |
816af2f2 | 70 | |
3dbd036b BS |
71 | /****************************************************************************** |
72 | * Atomic state | |
73 | *****************************************************************************/ | |
839ca903 BS |
74 | #define nv50_atom(p) container_of((p), struct nv50_atom, state) |
75 | ||
76 | struct nv50_atom { | |
77 | struct drm_atomic_state state; | |
78 | ||
79 | struct list_head outp; | |
80 | bool lock_core; | |
81 | bool flush_disable; | |
82 | }; | |
83 | ||
84 | struct nv50_outp_atom { | |
85 | struct list_head head; | |
86 | ||
87 | struct drm_encoder *encoder; | |
88 | bool flush_disable; | |
89 | ||
90 | union { | |
91 | struct { | |
92 | bool ctrl:1; | |
93 | }; | |
94 | u8 mask; | |
95 | } clr; | |
96 | ||
97 | union { | |
98 | struct { | |
99 | bool ctrl:1; | |
100 | }; | |
101 | u8 mask; | |
102 | } set; | |
103 | }; | |
104 | ||
3dbd036b BS |
105 | #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state) |
106 | ||
107 | struct nv50_head_atom { | |
108 | struct drm_crtc_state state; | |
109 | ||
c4e6812c BS |
110 | struct { |
111 | u16 iW; | |
112 | u16 iH; | |
113 | u16 oW; | |
114 | u16 oH; | |
115 | } view; | |
116 | ||
3dbd036b BS |
117 | struct nv50_head_mode { |
118 | bool interlace; | |
119 | u32 clock; | |
120 | struct { | |
121 | u16 active; | |
122 | u16 synce; | |
123 | u16 blanke; | |
124 | u16 blanks; | |
125 | } h; | |
126 | struct { | |
127 | u32 active; | |
128 | u16 synce; | |
129 | u16 blanke; | |
130 | u16 blanks; | |
131 | u16 blank2s; | |
132 | u16 blank2e; | |
133 | u16 blankus; | |
134 | } v; | |
135 | } mode; | |
136 | ||
a7ae1561 BS |
137 | struct { |
138 | u32 handle; | |
139 | u64 offset:40; | |
140 | } lut; | |
141 | ||
ad633619 BS |
142 | struct { |
143 | bool visible; | |
144 | u32 handle; | |
145 | u64 offset:40; | |
146 | u8 format; | |
147 | u8 kind:7; | |
148 | u8 layout:1; | |
149 | u8 block:4; | |
150 | u32 pitch:20; | |
151 | u16 x; | |
152 | u16 y; | |
153 | u16 w; | |
154 | u16 h; | |
155 | } core; | |
156 | ||
ea8ee390 BS |
157 | struct { |
158 | bool visible; | |
159 | u32 handle; | |
160 | u64 offset:40; | |
161 | u8 layout:1; | |
162 | u8 format:1; | |
163 | } curs; | |
164 | ||
ad633619 BS |
165 | struct { |
166 | u8 depth; | |
167 | u8 cpp; | |
168 | u16 x; | |
169 | u16 y; | |
170 | u16 w; | |
171 | u16 h; | |
172 | } base; | |
173 | ||
6bbab3b6 BS |
174 | struct { |
175 | u8 cpp; | |
176 | } ovly; | |
177 | ||
7e91833d BS |
178 | struct { |
179 | bool enable:1; | |
180 | u8 bits:2; | |
181 | u8 mode:4; | |
182 | } dither; | |
183 | ||
7e08d67c BS |
184 | struct { |
185 | struct { | |
186 | u16 cos:12; | |
187 | u16 sin:12; | |
188 | } sat; | |
189 | } procamp; | |
190 | ||
ad633619 BS |
191 | union { |
192 | struct { | |
193 | bool core:1; | |
ea8ee390 | 194 | bool curs:1; |
ad633619 BS |
195 | }; |
196 | u8 mask; | |
197 | } clr; | |
198 | ||
3dbd036b BS |
199 | union { |
200 | struct { | |
ad633619 | 201 | bool core:1; |
ea8ee390 | 202 | bool curs:1; |
ad633619 | 203 | bool view:1; |
3dbd036b | 204 | bool mode:1; |
6bbab3b6 BS |
205 | bool base:1; |
206 | bool ovly:1; | |
7e91833d | 207 | bool dither:1; |
7e08d67c | 208 | bool procamp:1; |
3dbd036b BS |
209 | }; |
210 | u16 mask; | |
211 | } set; | |
212 | }; | |
213 | ||
839ca903 BS |
214 | static inline struct nv50_head_atom * |
215 | nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) | |
216 | { | |
217 | struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); | |
218 | if (IS_ERR(statec)) | |
219 | return (void *)statec; | |
220 | return nv50_head_atom(statec); | |
221 | } | |
222 | ||
973f10c2 BS |
223 | #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state) |
224 | ||
225 | struct nv50_wndw_atom { | |
226 | struct drm_plane_state state; | |
227 | u8 interval; | |
228 | ||
229 | struct drm_rect clip; | |
230 | ||
231 | struct { | |
232 | u32 handle; | |
233 | u16 offset:12; | |
234 | bool awaken:1; | |
235 | } ntfy; | |
236 | ||
237 | struct { | |
238 | u32 handle; | |
239 | u16 offset:12; | |
240 | u32 acquire; | |
241 | u32 release; | |
242 | } sema; | |
243 | ||
244 | struct { | |
245 | u8 enable:2; | |
246 | } lut; | |
247 | ||
248 | struct { | |
249 | u8 mode:2; | |
250 | u8 interval:4; | |
251 | ||
252 | u8 format; | |
253 | u8 kind:7; | |
254 | u8 layout:1; | |
255 | u8 block:4; | |
256 | u32 pitch:20; | |
257 | u16 w; | |
258 | u16 h; | |
259 | ||
260 | u32 handle; | |
261 | u64 offset; | |
262 | } image; | |
263 | ||
264 | struct { | |
265 | u16 x; | |
266 | u16 y; | |
267 | } point; | |
268 | ||
269 | union { | |
270 | struct { | |
271 | bool ntfy:1; | |
272 | bool sema:1; | |
273 | bool image:1; | |
274 | }; | |
275 | u8 mask; | |
276 | } clr; | |
277 | ||
278 | union { | |
279 | struct { | |
280 | bool ntfy:1; | |
281 | bool sema:1; | |
282 | bool image:1; | |
283 | bool lut:1; | |
284 | bool point:1; | |
285 | }; | |
286 | u8 mask; | |
287 | } set; | |
288 | }; | |
289 | ||
b5a794b0 BS |
290 | /****************************************************************************** |
291 | * EVO channel | |
292 | *****************************************************************************/ | |
293 | ||
e225f446 | 294 | struct nv50_chan { |
0ad72863 | 295 | struct nvif_object user; |
a01ca78c | 296 | struct nvif_device *device; |
b5a794b0 BS |
297 | }; |
298 | ||
299 | static int | |
a01ca78c | 300 | nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 301 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 302 | struct nv50_chan *chan) |
b5a794b0 | 303 | { |
41a63406 BS |
304 | struct nvif_sclass *sclass; |
305 | int ret, i, n; | |
6af5289e | 306 | |
a01ca78c BS |
307 | chan->device = device; |
308 | ||
41a63406 | 309 | ret = n = nvif_object_sclass_get(disp, &sclass); |
6af5289e BS |
310 | if (ret < 0) |
311 | return ret; | |
312 | ||
410f3ec6 | 313 | while (oclass[0]) { |
41a63406 BS |
314 | for (i = 0; i < n; i++) { |
315 | if (sclass[i].oclass == oclass[0]) { | |
fcf3f91c | 316 | ret = nvif_object_init(disp, 0, oclass[0], |
a01ca78c | 317 | data, size, &chan->user); |
6af5289e BS |
318 | if (ret == 0) |
319 | nvif_object_map(&chan->user); | |
41a63406 | 320 | nvif_object_sclass_put(&sclass); |
6af5289e BS |
321 | return ret; |
322 | } | |
b76f1529 | 323 | } |
6af5289e | 324 | oclass++; |
410f3ec6 | 325 | } |
6af5289e | 326 | |
41a63406 | 327 | nvif_object_sclass_put(&sclass); |
410f3ec6 | 328 | return -ENOSYS; |
b5a794b0 BS |
329 | } |
330 | ||
331 | static void | |
0ad72863 | 332 | nv50_chan_destroy(struct nv50_chan *chan) |
b5a794b0 | 333 | { |
0ad72863 | 334 | nvif_object_fini(&chan->user); |
b5a794b0 BS |
335 | } |
336 | ||
337 | /****************************************************************************** | |
338 | * PIO EVO channel | |
339 | *****************************************************************************/ | |
340 | ||
e225f446 BS |
341 | struct nv50_pioc { |
342 | struct nv50_chan base; | |
b5a794b0 BS |
343 | }; |
344 | ||
345 | static void | |
0ad72863 | 346 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
b5a794b0 | 347 | { |
0ad72863 | 348 | nv50_chan_destroy(&pioc->base); |
b5a794b0 BS |
349 | } |
350 | ||
351 | static int | |
a01ca78c | 352 | nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 353 | const s32 *oclass, u8 head, void *data, u32 size, |
a01ca78c | 354 | struct nv50_pioc *pioc) |
b5a794b0 | 355 | { |
a01ca78c BS |
356 | return nv50_chan_create(device, disp, oclass, head, data, size, |
357 | &pioc->base); | |
410f3ec6 BS |
358 | } |
359 | ||
410f3ec6 BS |
360 | /****************************************************************************** |
361 | * Overlay Immediate | |
362 | *****************************************************************************/ | |
363 | ||
364 | struct nv50_oimm { | |
365 | struct nv50_pioc base; | |
366 | }; | |
367 | ||
368 | static int | |
a01ca78c BS |
369 | nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp, |
370 | int head, struct nv50_oimm *oimm) | |
410f3ec6 | 371 | { |
648d4dfd | 372 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
373 | .head = head, |
374 | }; | |
315a8b2e | 375 | static const s32 oclass[] = { |
648d4dfd BS |
376 | GK104_DISP_OVERLAY, |
377 | GF110_DISP_OVERLAY, | |
378 | GT214_DISP_OVERLAY, | |
379 | G82_DISP_OVERLAY, | |
380 | NV50_DISP_OVERLAY, | |
410f3ec6 BS |
381 | 0 |
382 | }; | |
383 | ||
a01ca78c BS |
384 | return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), |
385 | &oimm->base); | |
b5a794b0 BS |
386 | } |
387 | ||
388 | /****************************************************************************** | |
389 | * DMA EVO channel | |
390 | *****************************************************************************/ | |
391 | ||
accdea2e BS |
392 | struct nv50_dmac_ctxdma { |
393 | struct list_head head; | |
394 | struct nvif_object object; | |
395 | }; | |
396 | ||
e225f446 BS |
397 | struct nv50_dmac { |
398 | struct nv50_chan base; | |
3376ee37 BS |
399 | dma_addr_t handle; |
400 | u32 *ptr; | |
59ad1465 | 401 | |
0ad72863 BS |
402 | struct nvif_object sync; |
403 | struct nvif_object vram; | |
accdea2e | 404 | struct list_head ctxdma; |
0ad72863 | 405 | |
59ad1465 DV |
406 | /* Protects against concurrent pushbuf access to this channel, lock is |
407 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
408 | * dropped again by evo_kick. */ | |
409 | struct mutex lock; | |
b5a794b0 BS |
410 | }; |
411 | ||
accdea2e BS |
412 | static void |
413 | nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma) | |
414 | { | |
415 | nvif_object_fini(&ctxdma->object); | |
416 | list_del(&ctxdma->head); | |
417 | kfree(ctxdma); | |
418 | } | |
419 | ||
420 | static struct nv50_dmac_ctxdma * | |
f00f0e21 | 421 | nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb) |
accdea2e BS |
422 | { |
423 | struct nouveau_drm *drm = nouveau_drm(fb->base.dev); | |
424 | struct nv50_dmac_ctxdma *ctxdma; | |
f00f0e21 BS |
425 | const u8 kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; |
426 | const u32 handle = 0xfb000000 | kind; | |
accdea2e BS |
427 | struct { |
428 | struct nv_dma_v0 base; | |
429 | union { | |
430 | struct nv50_dma_v0 nv50; | |
431 | struct gf100_dma_v0 gf100; | |
432 | struct gf119_dma_v0 gf119; | |
433 | }; | |
434 | } args = {}; | |
435 | u32 argc = sizeof(args.base); | |
436 | int ret; | |
437 | ||
438 | list_for_each_entry(ctxdma, &dmac->ctxdma, head) { | |
439 | if (ctxdma->object.handle == handle) | |
440 | return ctxdma; | |
441 | } | |
442 | ||
443 | if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) | |
444 | return ERR_PTR(-ENOMEM); | |
445 | list_add(&ctxdma->head, &dmac->ctxdma); | |
446 | ||
447 | args.base.target = NV_DMA_V0_TARGET_VRAM; | |
448 | args.base.access = NV_DMA_V0_ACCESS_RDWR; | |
449 | args.base.start = 0; | |
450 | args.base.limit = drm->device.info.ram_user - 1; | |
451 | ||
452 | if (drm->device.info.chipset < 0x80) { | |
453 | args.nv50.part = NV50_DMA_V0_PART_256; | |
454 | argc += sizeof(args.nv50); | |
455 | } else | |
456 | if (drm->device.info.chipset < 0xc0) { | |
457 | args.nv50.part = NV50_DMA_V0_PART_256; | |
458 | args.nv50.kind = kind; | |
459 | argc += sizeof(args.nv50); | |
460 | } else | |
461 | if (drm->device.info.chipset < 0xd0) { | |
462 | args.gf100.kind = kind; | |
463 | argc += sizeof(args.gf100); | |
464 | } else { | |
465 | args.gf119.page = GF119_DMA_V0_PAGE_LP; | |
466 | args.gf119.kind = kind; | |
467 | argc += sizeof(args.gf119); | |
468 | } | |
469 | ||
470 | ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY, | |
471 | &args, argc, &ctxdma->object); | |
472 | if (ret) { | |
473 | nv50_dmac_ctxdma_del(ctxdma); | |
474 | return ERR_PTR(ret); | |
475 | } | |
476 | ||
477 | return ctxdma; | |
478 | } | |
479 | ||
b5a794b0 | 480 | static void |
0ad72863 | 481 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
b5a794b0 | 482 | { |
a01ca78c | 483 | struct nvif_device *device = dmac->base.device; |
accdea2e BS |
484 | struct nv50_dmac_ctxdma *ctxdma, *ctxtmp; |
485 | ||
486 | list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) { | |
487 | nv50_dmac_ctxdma_del(ctxdma); | |
488 | } | |
a01ca78c | 489 | |
0ad72863 BS |
490 | nvif_object_fini(&dmac->vram); |
491 | nvif_object_fini(&dmac->sync); | |
492 | ||
493 | nv50_chan_destroy(&dmac->base); | |
494 | ||
b5a794b0 | 495 | if (dmac->ptr) { |
26c9e8ef BS |
496 | struct device *dev = nvxx_device(device)->dev; |
497 | dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle); | |
b5a794b0 | 498 | } |
b5a794b0 BS |
499 | } |
500 | ||
47057302 | 501 | static int |
a01ca78c | 502 | nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, |
315a8b2e | 503 | const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, |
e225f446 | 504 | struct nv50_dmac *dmac) |
47057302 | 505 | { |
648d4dfd | 506 | struct nv50_disp_core_channel_dma_v0 *args = data; |
0ad72863 | 507 | struct nvif_object pushbuf; |
47057302 BS |
508 | int ret; |
509 | ||
59ad1465 DV |
510 | mutex_init(&dmac->lock); |
511 | ||
26c9e8ef BS |
512 | dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE, |
513 | &dmac->handle, GFP_KERNEL); | |
47057302 BS |
514 | if (!dmac->ptr) |
515 | return -ENOMEM; | |
516 | ||
fcf3f91c BS |
517 | ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, |
518 | &(struct nv_dma_v0) { | |
4acfd707 BS |
519 | .target = NV_DMA_V0_TARGET_PCI_US, |
520 | .access = NV_DMA_V0_ACCESS_RD, | |
47057302 BS |
521 | .start = dmac->handle + 0x0000, |
522 | .limit = dmac->handle + 0x0fff, | |
4acfd707 | 523 | }, sizeof(struct nv_dma_v0), &pushbuf); |
b5a794b0 | 524 | if (ret) |
47057302 | 525 | return ret; |
b5a794b0 | 526 | |
bf81df9b BS |
527 | args->pushbuf = nvif_handle(&pushbuf); |
528 | ||
a01ca78c BS |
529 | ret = nv50_chan_create(device, disp, oclass, head, data, size, |
530 | &dmac->base); | |
0ad72863 | 531 | nvif_object_fini(&pushbuf); |
47057302 BS |
532 | if (ret) |
533 | return ret; | |
534 | ||
a01ca78c | 535 | ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, |
4acfd707 BS |
536 | &(struct nv_dma_v0) { |
537 | .target = NV_DMA_V0_TARGET_VRAM, | |
538 | .access = NV_DMA_V0_ACCESS_RDWR, | |
47057302 BS |
539 | .start = syncbuf + 0x0000, |
540 | .limit = syncbuf + 0x0fff, | |
4acfd707 | 541 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 542 | &dmac->sync); |
47057302 BS |
543 | if (ret) |
544 | return ret; | |
545 | ||
a01ca78c | 546 | ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, |
4acfd707 BS |
547 | &(struct nv_dma_v0) { |
548 | .target = NV_DMA_V0_TARGET_VRAM, | |
549 | .access = NV_DMA_V0_ACCESS_RDWR, | |
b5a794b0 | 550 | .start = 0, |
f392ec4b | 551 | .limit = device->info.ram_user - 1, |
4acfd707 | 552 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 553 | &dmac->vram); |
b5a794b0 | 554 | if (ret) |
47057302 BS |
555 | return ret; |
556 | ||
accdea2e | 557 | INIT_LIST_HEAD(&dmac->ctxdma); |
b5a794b0 BS |
558 | return ret; |
559 | } | |
560 | ||
410f3ec6 BS |
561 | /****************************************************************************** |
562 | * Core | |
563 | *****************************************************************************/ | |
564 | ||
e225f446 BS |
565 | struct nv50_mast { |
566 | struct nv50_dmac base; | |
b5a794b0 BS |
567 | }; |
568 | ||
410f3ec6 | 569 | static int |
a01ca78c BS |
570 | nv50_core_create(struct nvif_device *device, struct nvif_object *disp, |
571 | u64 syncbuf, struct nv50_mast *core) | |
410f3ec6 | 572 | { |
648d4dfd BS |
573 | struct nv50_disp_core_channel_dma_v0 args = { |
574 | .pushbuf = 0xb0007d00, | |
410f3ec6 | 575 | }; |
315a8b2e | 576 | static const s32 oclass[] = { |
fd47877f | 577 | GP104_DISP_CORE_CHANNEL_DMA, |
f9d5cbb3 | 578 | GP100_DISP_CORE_CHANNEL_DMA, |
db1eb528 | 579 | GM200_DISP_CORE_CHANNEL_DMA, |
648d4dfd BS |
580 | GM107_DISP_CORE_CHANNEL_DMA, |
581 | GK110_DISP_CORE_CHANNEL_DMA, | |
582 | GK104_DISP_CORE_CHANNEL_DMA, | |
583 | GF110_DISP_CORE_CHANNEL_DMA, | |
584 | GT214_DISP_CORE_CHANNEL_DMA, | |
585 | GT206_DISP_CORE_CHANNEL_DMA, | |
586 | GT200_DISP_CORE_CHANNEL_DMA, | |
587 | G82_DISP_CORE_CHANNEL_DMA, | |
588 | NV50_DISP_CORE_CHANNEL_DMA, | |
410f3ec6 BS |
589 | 0 |
590 | }; | |
591 | ||
a01ca78c BS |
592 | return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args), |
593 | syncbuf, &core->base); | |
410f3ec6 BS |
594 | } |
595 | ||
596 | /****************************************************************************** | |
597 | * Base | |
598 | *****************************************************************************/ | |
b5a794b0 | 599 | |
e225f446 BS |
600 | struct nv50_sync { |
601 | struct nv50_dmac base; | |
9f9bdaaf BS |
602 | u32 addr; |
603 | u32 data; | |
3376ee37 BS |
604 | }; |
605 | ||
410f3ec6 | 606 | static int |
a01ca78c BS |
607 | nv50_base_create(struct nvif_device *device, struct nvif_object *disp, |
608 | int head, u64 syncbuf, struct nv50_sync *base) | |
410f3ec6 | 609 | { |
648d4dfd BS |
610 | struct nv50_disp_base_channel_dma_v0 args = { |
611 | .pushbuf = 0xb0007c00 | head, | |
410f3ec6 BS |
612 | .head = head, |
613 | }; | |
315a8b2e | 614 | static const s32 oclass[] = { |
648d4dfd BS |
615 | GK110_DISP_BASE_CHANNEL_DMA, |
616 | GK104_DISP_BASE_CHANNEL_DMA, | |
617 | GF110_DISP_BASE_CHANNEL_DMA, | |
618 | GT214_DISP_BASE_CHANNEL_DMA, | |
619 | GT200_DISP_BASE_CHANNEL_DMA, | |
620 | G82_DISP_BASE_CHANNEL_DMA, | |
621 | NV50_DISP_BASE_CHANNEL_DMA, | |
410f3ec6 BS |
622 | 0 |
623 | }; | |
624 | ||
a01ca78c | 625 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
626 | syncbuf, &base->base); |
627 | } | |
628 | ||
629 | /****************************************************************************** | |
630 | * Overlay | |
631 | *****************************************************************************/ | |
632 | ||
e225f446 BS |
633 | struct nv50_ovly { |
634 | struct nv50_dmac base; | |
b5a794b0 | 635 | }; |
f20ce962 | 636 | |
410f3ec6 | 637 | static int |
a01ca78c BS |
638 | nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp, |
639 | int head, u64 syncbuf, struct nv50_ovly *ovly) | |
410f3ec6 | 640 | { |
648d4dfd BS |
641 | struct nv50_disp_overlay_channel_dma_v0 args = { |
642 | .pushbuf = 0xb0007e00 | head, | |
410f3ec6 BS |
643 | .head = head, |
644 | }; | |
315a8b2e | 645 | static const s32 oclass[] = { |
648d4dfd BS |
646 | GK104_DISP_OVERLAY_CONTROL_DMA, |
647 | GF110_DISP_OVERLAY_CONTROL_DMA, | |
648 | GT214_DISP_OVERLAY_CHANNEL_DMA, | |
649 | GT200_DISP_OVERLAY_CHANNEL_DMA, | |
650 | G82_DISP_OVERLAY_CHANNEL_DMA, | |
651 | NV50_DISP_OVERLAY_CHANNEL_DMA, | |
410f3ec6 BS |
652 | 0 |
653 | }; | |
654 | ||
a01ca78c | 655 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
410f3ec6 BS |
656 | syncbuf, &ovly->base); |
657 | } | |
26f6d88b | 658 | |
e225f446 | 659 | struct nv50_head { |
dd0e3d53 | 660 | struct nouveau_crtc base; |
e225f446 BS |
661 | struct nv50_ovly ovly; |
662 | struct nv50_oimm oimm; | |
b5a794b0 BS |
663 | }; |
664 | ||
e225f446 | 665 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
e225f446 BS |
666 | #define nv50_ovly(c) (&nv50_head(c)->ovly) |
667 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
668 | #define nv50_chan(c) (&(c)->base.base) | |
0ad72863 BS |
669 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
670 | ||
e225f446 | 671 | struct nv50_disp { |
0ad72863 | 672 | struct nvif_object *disp; |
e225f446 | 673 | struct nv50_mast mast; |
b5a794b0 | 674 | |
b5a794b0 | 675 | struct nouveau_bo *sync; |
839ca903 BS |
676 | |
677 | struct mutex mutex; | |
dd0e3d53 BS |
678 | }; |
679 | ||
e225f446 BS |
680 | static struct nv50_disp * |
681 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 682 | { |
77145f1c | 683 | return nouveau_display(dev)->priv; |
26f6d88b BS |
684 | } |
685 | ||
e225f446 | 686 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 687 | |
bdb8c212 BS |
688 | /****************************************************************************** |
689 | * EVO channel helpers | |
690 | *****************************************************************************/ | |
51beb428 | 691 | static u32 * |
b5a794b0 | 692 | evo_wait(void *evoc, int nr) |
51beb428 | 693 | { |
e225f446 | 694 | struct nv50_dmac *dmac = evoc; |
a01ca78c | 695 | struct nvif_device *device = dmac->base.device; |
0ad72863 | 696 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
51beb428 | 697 | |
59ad1465 | 698 | mutex_lock(&dmac->lock); |
de8268c5 | 699 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 700 | dmac->ptr[put] = 0x20000000; |
51beb428 | 701 | |
0ad72863 | 702 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
54442040 BS |
703 | if (nvif_msec(device, 2000, |
704 | if (!nvif_rd32(&dmac->base.user, 0x0004)) | |
705 | break; | |
706 | ) < 0) { | |
59ad1465 | 707 | mutex_unlock(&dmac->lock); |
9ad97ede | 708 | printk(KERN_ERR "nouveau: evo channel stalled\n"); |
51beb428 BS |
709 | return NULL; |
710 | } | |
711 | ||
712 | put = 0; | |
713 | } | |
714 | ||
b5a794b0 | 715 | return dmac->ptr + put; |
51beb428 BS |
716 | } |
717 | ||
718 | static void | |
b5a794b0 | 719 | evo_kick(u32 *push, void *evoc) |
51beb428 | 720 | { |
e225f446 | 721 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 722 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 723 | mutex_unlock(&dmac->lock); |
51beb428 BS |
724 | } |
725 | ||
2b1930c3 BS |
726 | #define evo_mthd(p,m,s) do { \ |
727 | const u32 _m = (m), _s = (s); \ | |
7f55a072 BS |
728 | if (drm_debug & DRM_UT_KMS) \ |
729 | printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \ | |
2b1930c3 BS |
730 | *((p)++) = ((_s << 18) | _m); \ |
731 | } while(0) | |
7f55a072 | 732 | |
2b1930c3 BS |
733 | #define evo_data(p,d) do { \ |
734 | const u32 _d = (d); \ | |
7f55a072 BS |
735 | if (drm_debug & DRM_UT_KMS) \ |
736 | printk(KERN_ERR "\t%08x\n", _d); \ | |
2b1930c3 BS |
737 | *((p)++) = _d; \ |
738 | } while(0) | |
51beb428 | 739 | |
973f10c2 BS |
740 | /****************************************************************************** |
741 | * Plane | |
742 | *****************************************************************************/ | |
743 | #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane) | |
744 | ||
745 | struct nv50_wndw { | |
746 | const struct nv50_wndw_func *func; | |
747 | struct nv50_dmac *dmac; | |
748 | ||
749 | struct drm_plane plane; | |
750 | ||
751 | struct nvif_notify notify; | |
752 | u16 ntfy; | |
753 | u16 sema; | |
754 | u32 data; | |
973f10c2 BS |
755 | }; |
756 | ||
757 | struct nv50_wndw_func { | |
758 | void *(*dtor)(struct nv50_wndw *); | |
759 | int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, | |
760 | struct nv50_head_atom *asyh); | |
761 | void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, | |
762 | struct nv50_head_atom *asyh); | |
763 | void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh, | |
764 | struct nv50_wndw_atom *asyw); | |
765 | ||
766 | void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
767 | void (*sema_clr)(struct nv50_wndw *); | |
768 | void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
769 | void (*ntfy_clr)(struct nv50_wndw *); | |
770 | int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
771 | void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
772 | void (*image_clr)(struct nv50_wndw *); | |
773 | void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
774 | void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); | |
775 | ||
776 | u32 (*update)(struct nv50_wndw *, u32 interlock); | |
777 | }; | |
778 | ||
779 | static int | |
780 | nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
781 | { | |
782 | if (asyw->set.ntfy) | |
783 | return wndw->func->ntfy_wait_begun(wndw, asyw); | |
784 | return 0; | |
785 | } | |
786 | ||
787 | static u32 | |
788 | nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush, | |
789 | struct nv50_wndw_atom *asyw) | |
790 | { | |
791 | if (asyw->clr.sema && (!asyw->set.sema || flush)) | |
792 | wndw->func->sema_clr(wndw); | |
793 | if (asyw->clr.ntfy && (!asyw->set.ntfy || flush)) | |
794 | wndw->func->ntfy_clr(wndw); | |
795 | if (asyw->clr.image && (!asyw->set.image || flush)) | |
796 | wndw->func->image_clr(wndw); | |
797 | ||
798 | return flush ? wndw->func->update(wndw, interlock) : 0; | |
799 | } | |
800 | ||
801 | static u32 | |
802 | nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock, | |
803 | struct nv50_wndw_atom *asyw) | |
804 | { | |
805 | if (interlock) { | |
806 | asyw->image.mode = 0; | |
807 | asyw->image.interval = 1; | |
808 | } | |
809 | ||
810 | if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); | |
811 | if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); | |
812 | if (asyw->set.image) wndw->func->image_set(wndw, asyw); | |
813 | if (asyw->set.lut ) wndw->func->lut (wndw, asyw); | |
814 | if (asyw->set.point) wndw->func->point (wndw, asyw); | |
815 | ||
816 | return wndw->func->update(wndw, interlock); | |
817 | } | |
818 | ||
819 | static void | |
820 | nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, | |
821 | struct nv50_wndw_atom *asyw, | |
822 | struct nv50_head_atom *asyh) | |
823 | { | |
824 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
825 | NV_ATOMIC(drm, "%s release\n", wndw->plane.name); | |
826 | wndw->func->release(wndw, asyw, asyh); | |
827 | asyw->ntfy.handle = 0; | |
828 | asyw->sema.handle = 0; | |
829 | } | |
830 | ||
831 | static int | |
832 | nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, | |
833 | struct nv50_wndw_atom *asyw, | |
834 | struct nv50_head_atom *asyh) | |
835 | { | |
836 | struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb); | |
837 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
838 | int ret; | |
839 | ||
840 | NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); | |
841 | asyw->clip.x1 = 0; | |
842 | asyw->clip.y1 = 0; | |
843 | asyw->clip.x2 = asyh->state.mode.hdisplay; | |
844 | asyw->clip.y2 = asyh->state.mode.vdisplay; | |
845 | ||
846 | asyw->image.w = fb->base.width; | |
847 | asyw->image.h = fb->base.height; | |
848 | asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; | |
849 | if (asyw->image.kind) { | |
850 | asyw->image.layout = 0; | |
851 | if (drm->device.info.chipset >= 0xc0) | |
852 | asyw->image.block = fb->nvbo->tile_mode >> 4; | |
853 | else | |
854 | asyw->image.block = fb->nvbo->tile_mode; | |
855 | asyw->image.pitch = (fb->base.pitches[0] / 4) << 4; | |
856 | } else { | |
857 | asyw->image.layout = 1; | |
858 | asyw->image.block = 0; | |
859 | asyw->image.pitch = fb->base.pitches[0]; | |
860 | } | |
861 | ||
862 | ret = wndw->func->acquire(wndw, asyw, asyh); | |
863 | if (ret) | |
864 | return ret; | |
865 | ||
866 | if (asyw->set.image) { | |
867 | if (!(asyw->image.mode = asyw->interval ? 0 : 1)) | |
868 | asyw->image.interval = asyw->interval; | |
869 | else | |
870 | asyw->image.interval = 0; | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
876 | static int | |
877 | nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) | |
878 | { | |
879 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
880 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
839ca903 BS |
881 | struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); |
882 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
973f10c2 BS |
883 | struct nv50_head_atom *harm = NULL, *asyh = NULL; |
884 | bool varm = false, asyv = false, asym = false; | |
885 | int ret; | |
886 | ||
973f10c2 BS |
887 | NV_ATOMIC(drm, "%s atomic_check\n", plane->name); |
888 | if (asyw->state.crtc) { | |
839ca903 | 889 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); |
973f10c2 BS |
890 | if (IS_ERR(asyh)) |
891 | return PTR_ERR(asyh); | |
892 | asym = drm_atomic_crtc_needs_modeset(&asyh->state); | |
893 | asyv = asyh->state.active; | |
894 | } | |
895 | ||
896 | if (armw->state.crtc) { | |
839ca903 | 897 | harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); |
973f10c2 BS |
898 | if (IS_ERR(harm)) |
899 | return PTR_ERR(harm); | |
839ca903 | 900 | varm = harm->state.crtc->state->active; |
973f10c2 BS |
901 | } |
902 | ||
903 | if (asyv) { | |
904 | asyw->point.x = asyw->state.crtc_x; | |
905 | asyw->point.y = asyw->state.crtc_y; | |
906 | if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) | |
907 | asyw->set.point = true; | |
908 | ||
909 | if (!varm || asym || armw->state.fb != asyw->state.fb) { | |
910 | ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh); | |
911 | if (ret) | |
912 | return ret; | |
913 | } | |
914 | } else | |
915 | if (varm) { | |
916 | nv50_wndw_atomic_check_release(wndw, asyw, harm); | |
917 | } else { | |
918 | return 0; | |
919 | } | |
920 | ||
921 | if (!asyv || asym) { | |
922 | asyw->clr.ntfy = armw->ntfy.handle != 0; | |
923 | asyw->clr.sema = armw->sema.handle != 0; | |
924 | if (wndw->func->image_clr) | |
925 | asyw->clr.image = armw->image.handle != 0; | |
926 | asyw->set.lut = wndw->func->lut && asyv; | |
927 | } | |
928 | ||
973f10c2 BS |
929 | return 0; |
930 | } | |
931 | ||
839ca903 BS |
932 | static void |
933 | nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) | |
934 | { | |
935 | struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb); | |
936 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
937 | ||
938 | NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); | |
939 | if (!old_state->fb) | |
940 | return; | |
941 | ||
942 | nouveau_bo_unpin(fb->nvbo); | |
943 | } | |
944 | ||
945 | static int | |
946 | nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) | |
947 | { | |
948 | struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb); | |
949 | struct nouveau_drm *drm = nouveau_drm(plane->dev); | |
950 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
951 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
952 | struct nv50_head_atom *asyh; | |
953 | struct nv50_dmac_ctxdma *ctxdma; | |
839ca903 BS |
954 | int ret; |
955 | ||
956 | NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb); | |
957 | if (!asyw->state.fb) | |
958 | return 0; | |
839ca903 BS |
959 | |
960 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true); | |
961 | if (ret) | |
962 | return ret; | |
963 | ||
f00f0e21 | 964 | ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb); |
839ca903 BS |
965 | if (IS_ERR(ctxdma)) { |
966 | nouveau_bo_unpin(fb->nvbo); | |
967 | return PTR_ERR(ctxdma); | |
968 | } | |
969 | ||
970 | asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv); | |
971 | asyw->image.handle = ctxdma->object.handle; | |
972 | asyw->image.offset = fb->nvbo->bo.offset; | |
973 | ||
974 | if (wndw->func->prepare) { | |
975 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); | |
976 | if (IS_ERR(asyh)) | |
977 | return PTR_ERR(asyh); | |
978 | ||
979 | wndw->func->prepare(wndw, asyh, asyw); | |
980 | } | |
981 | ||
982 | return 0; | |
983 | } | |
984 | ||
985 | static const struct drm_plane_helper_funcs | |
986 | nv50_wndw_helper = { | |
987 | .prepare_fb = nv50_wndw_prepare_fb, | |
988 | .cleanup_fb = nv50_wndw_cleanup_fb, | |
989 | .atomic_check = nv50_wndw_atomic_check, | |
990 | }; | |
991 | ||
973f10c2 BS |
992 | static void |
993 | nv50_wndw_atomic_destroy_state(struct drm_plane *plane, | |
994 | struct drm_plane_state *state) | |
995 | { | |
996 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); | |
997 | __drm_atomic_helper_plane_destroy_state(&asyw->state); | |
998 | dma_fence_put(asyw->state.fence); | |
999 | kfree(asyw); | |
1000 | } | |
1001 | ||
1002 | static struct drm_plane_state * | |
1003 | nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) | |
1004 | { | |
1005 | struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); | |
1006 | struct nv50_wndw_atom *asyw; | |
1007 | if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) | |
1008 | return NULL; | |
1009 | __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); | |
1010 | asyw->state.fence = NULL; | |
1011 | asyw->interval = 1; | |
1012 | asyw->sema = armw->sema; | |
1013 | asyw->ntfy = armw->ntfy; | |
1014 | asyw->image = armw->image; | |
1015 | asyw->point = armw->point; | |
1016 | asyw->lut = armw->lut; | |
1017 | asyw->clr.mask = 0; | |
1018 | asyw->set.mask = 0; | |
1019 | return &asyw->state; | |
1020 | } | |
1021 | ||
1022 | static void | |
1023 | nv50_wndw_reset(struct drm_plane *plane) | |
1024 | { | |
1025 | struct nv50_wndw_atom *asyw; | |
1026 | ||
1027 | if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) | |
1028 | return; | |
1029 | ||
1030 | if (plane->state) | |
1031 | plane->funcs->atomic_destroy_state(plane, plane->state); | |
1032 | plane->state = &asyw->state; | |
1033 | plane->state->plane = plane; | |
1034 | plane->state->rotation = DRM_ROTATE_0; | |
1035 | } | |
1036 | ||
1037 | static void | |
1038 | nv50_wndw_destroy(struct drm_plane *plane) | |
1039 | { | |
1040 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
1041 | void *data; | |
1042 | nvif_notify_fini(&wndw->notify); | |
1043 | data = wndw->func->dtor(wndw); | |
1044 | drm_plane_cleanup(&wndw->plane); | |
1045 | kfree(data); | |
1046 | } | |
1047 | ||
1048 | static const struct drm_plane_funcs | |
1049 | nv50_wndw = { | |
839ca903 BS |
1050 | .update_plane = drm_atomic_helper_update_plane, |
1051 | .disable_plane = drm_atomic_helper_disable_plane, | |
973f10c2 BS |
1052 | .destroy = nv50_wndw_destroy, |
1053 | .reset = nv50_wndw_reset, | |
1054 | .set_property = drm_atomic_helper_plane_set_property, | |
1055 | .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, | |
1056 | .atomic_destroy_state = nv50_wndw_atomic_destroy_state, | |
1057 | }; | |
1058 | ||
1059 | static void | |
1060 | nv50_wndw_fini(struct nv50_wndw *wndw) | |
1061 | { | |
1062 | nvif_notify_put(&wndw->notify); | |
1063 | } | |
1064 | ||
1065 | static void | |
1066 | nv50_wndw_init(struct nv50_wndw *wndw) | |
1067 | { | |
1068 | nvif_notify_get(&wndw->notify); | |
1069 | } | |
1070 | ||
1071 | static int | |
1072 | nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev, | |
1073 | enum drm_plane_type type, const char *name, int index, | |
1074 | struct nv50_dmac *dmac, const u32 *format, int nformat, | |
1075 | struct nv50_wndw *wndw) | |
1076 | { | |
1077 | int ret; | |
1078 | ||
1079 | wndw->func = func; | |
1080 | wndw->dmac = dmac; | |
1081 | ||
1082 | ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format, | |
1083 | nformat, type, "%s-%d", name, index); | |
1084 | if (ret) | |
1085 | return ret; | |
1086 | ||
839ca903 | 1087 | drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); |
973f10c2 BS |
1088 | return 0; |
1089 | } | |
1090 | ||
22e927d2 BS |
1091 | /****************************************************************************** |
1092 | * Cursor plane | |
1093 | *****************************************************************************/ | |
1094 | #define nv50_curs(p) container_of((p), struct nv50_curs, wndw) | |
1095 | ||
1096 | struct nv50_curs { | |
1097 | struct nv50_wndw wndw; | |
1098 | struct nvif_object chan; | |
1099 | }; | |
1100 | ||
1101 | static u32 | |
1102 | nv50_curs_update(struct nv50_wndw *wndw, u32 interlock) | |
1103 | { | |
1104 | struct nv50_curs *curs = nv50_curs(wndw); | |
1105 | nvif_wr32(&curs->chan, 0x0080, 0x00000000); | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static void | |
1110 | nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1111 | { | |
1112 | struct nv50_curs *curs = nv50_curs(wndw); | |
1113 | nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x); | |
1114 | } | |
1115 | ||
1116 | static void | |
1117 | nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh, | |
1118 | struct nv50_wndw_atom *asyw) | |
1119 | { | |
1120 | asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle; | |
1121 | asyh->curs.offset = asyw->image.offset; | |
1122 | asyh->set.curs = asyh->curs.visible; | |
1123 | } | |
1124 | ||
1125 | static void | |
1126 | nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1127 | struct nv50_head_atom *asyh) | |
1128 | { | |
1129 | asyh->curs.visible = false; | |
1130 | } | |
1131 | ||
1132 | static int | |
1133 | nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1134 | struct nv50_head_atom *asyh) | |
1135 | { | |
1136 | int ret; | |
1137 | ||
1138 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, | |
1139 | DRM_PLANE_HELPER_NO_SCALING, | |
1140 | DRM_PLANE_HELPER_NO_SCALING, | |
1141 | true, true); | |
1142 | asyh->curs.visible = asyw->state.visible; | |
1143 | if (ret || !asyh->curs.visible) | |
1144 | return ret; | |
1145 | ||
1146 | switch (asyw->state.fb->width) { | |
1147 | case 32: asyh->curs.layout = 0; break; | |
1148 | case 64: asyh->curs.layout = 1; break; | |
1149 | default: | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | ||
1153 | if (asyw->state.fb->width != asyw->state.fb->height) | |
1154 | return -EINVAL; | |
1155 | ||
1156 | switch (asyw->state.fb->pixel_format) { | |
1157 | case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break; | |
1158 | default: | |
1159 | WARN_ON(1); | |
1160 | return -EINVAL; | |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static void * | |
1167 | nv50_curs_dtor(struct nv50_wndw *wndw) | |
1168 | { | |
1169 | struct nv50_curs *curs = nv50_curs(wndw); | |
1170 | nvif_object_fini(&curs->chan); | |
1171 | return curs; | |
1172 | } | |
1173 | ||
1174 | static const u32 | |
1175 | nv50_curs_format[] = { | |
1176 | DRM_FORMAT_ARGB8888, | |
1177 | }; | |
1178 | ||
1179 | static const struct nv50_wndw_func | |
1180 | nv50_curs = { | |
1181 | .dtor = nv50_curs_dtor, | |
1182 | .acquire = nv50_curs_acquire, | |
1183 | .release = nv50_curs_release, | |
1184 | .prepare = nv50_curs_prepare, | |
1185 | .point = nv50_curs_point, | |
1186 | .update = nv50_curs_update, | |
1187 | }; | |
1188 | ||
1189 | static int | |
1190 | nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head, | |
1191 | struct nv50_curs **pcurs) | |
1192 | { | |
1193 | static const struct nvif_mclass curses[] = { | |
1194 | { GK104_DISP_CURSOR, 0 }, | |
1195 | { GF110_DISP_CURSOR, 0 }, | |
1196 | { GT214_DISP_CURSOR, 0 }, | |
1197 | { G82_DISP_CURSOR, 0 }, | |
1198 | { NV50_DISP_CURSOR, 0 }, | |
1199 | {} | |
1200 | }; | |
1201 | struct nv50_disp_cursor_v0 args = { | |
1202 | .head = head->base.index, | |
1203 | }; | |
1204 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
1205 | struct nv50_curs *curs; | |
1206 | int cid, ret; | |
1207 | ||
1208 | cid = nvif_mclass(disp->disp, curses); | |
1209 | if (cid < 0) { | |
1210 | NV_ERROR(drm, "No supported cursor immediate class\n"); | |
1211 | return cid; | |
1212 | } | |
1213 | ||
1214 | if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL))) | |
1215 | return -ENOMEM; | |
1216 | ||
1217 | ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR, | |
1218 | "curs", head->base.index, &disp->mast.base, | |
1219 | nv50_curs_format, ARRAY_SIZE(nv50_curs_format), | |
1220 | &curs->wndw); | |
1221 | if (ret) { | |
1222 | kfree(curs); | |
1223 | return ret; | |
1224 | } | |
1225 | ||
1226 | ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args, | |
1227 | sizeof(args), &curs->chan); | |
1228 | if (ret) { | |
1229 | NV_ERROR(drm, "curs%04x allocation failed: %d\n", | |
1230 | curses[cid].oclass, ret); | |
1231 | return ret; | |
1232 | } | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
973f10c2 BS |
1237 | /****************************************************************************** |
1238 | * Primary plane | |
1239 | *****************************************************************************/ | |
1240 | #define nv50_base(p) container_of((p), struct nv50_base, wndw) | |
1241 | ||
1242 | struct nv50_base { | |
1243 | struct nv50_wndw wndw; | |
1244 | struct nv50_sync chan; | |
1245 | int id; | |
1246 | }; | |
1247 | ||
1248 | static int | |
1249 | nv50_base_notify(struct nvif_notify *notify) | |
1250 | { | |
1251 | return NVIF_NOTIFY_KEEP; | |
1252 | } | |
1253 | ||
1254 | static void | |
1255 | nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1256 | { | |
1257 | struct nv50_base *base = nv50_base(wndw); | |
1258 | u32 *push; | |
1259 | if ((push = evo_wait(&base->chan, 2))) { | |
1260 | evo_mthd(push, 0x00e0, 1); | |
1261 | evo_data(push, asyw->lut.enable << 30); | |
1262 | evo_kick(push, &base->chan); | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | static void | |
1267 | nv50_base_image_clr(struct nv50_wndw *wndw) | |
1268 | { | |
1269 | struct nv50_base *base = nv50_base(wndw); | |
1270 | u32 *push; | |
1271 | if ((push = evo_wait(&base->chan, 4))) { | |
1272 | evo_mthd(push, 0x0084, 1); | |
1273 | evo_data(push, 0x00000000); | |
1274 | evo_mthd(push, 0x00c0, 1); | |
1275 | evo_data(push, 0x00000000); | |
1276 | evo_kick(push, &base->chan); | |
1277 | } | |
1278 | } | |
1279 | ||
1280 | static void | |
1281 | nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1282 | { | |
1283 | struct nv50_base *base = nv50_base(wndw); | |
1284 | const s32 oclass = base->chan.base.base.user.oclass; | |
1285 | u32 *push; | |
1286 | if ((push = evo_wait(&base->chan, 10))) { | |
1287 | evo_mthd(push, 0x0084, 1); | |
1288 | evo_data(push, (asyw->image.mode << 8) | | |
1289 | (asyw->image.interval << 4)); | |
1290 | evo_mthd(push, 0x00c0, 1); | |
1291 | evo_data(push, asyw->image.handle); | |
1292 | if (oclass < G82_DISP_BASE_CHANNEL_DMA) { | |
1293 | evo_mthd(push, 0x0800, 5); | |
1294 | evo_data(push, asyw->image.offset >> 8); | |
1295 | evo_data(push, 0x00000000); | |
1296 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1297 | evo_data(push, (asyw->image.layout << 20) | | |
1298 | asyw->image.pitch | | |
1299 | asyw->image.block); | |
1300 | evo_data(push, (asyw->image.kind << 16) | | |
1301 | (asyw->image.format << 8)); | |
1302 | } else | |
1303 | if (oclass < GF110_DISP_BASE_CHANNEL_DMA) { | |
1304 | evo_mthd(push, 0x0800, 5); | |
1305 | evo_data(push, asyw->image.offset >> 8); | |
1306 | evo_data(push, 0x00000000); | |
1307 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1308 | evo_data(push, (asyw->image.layout << 20) | | |
1309 | asyw->image.pitch | | |
1310 | asyw->image.block); | |
1311 | evo_data(push, asyw->image.format << 8); | |
1312 | } else { | |
1313 | evo_mthd(push, 0x0400, 5); | |
1314 | evo_data(push, asyw->image.offset >> 8); | |
1315 | evo_data(push, 0x00000000); | |
1316 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); | |
1317 | evo_data(push, (asyw->image.layout << 24) | | |
1318 | asyw->image.pitch | | |
1319 | asyw->image.block); | |
1320 | evo_data(push, asyw->image.format << 8); | |
1321 | } | |
1322 | evo_kick(push, &base->chan); | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | static void | |
1327 | nv50_base_ntfy_clr(struct nv50_wndw *wndw) | |
1328 | { | |
1329 | struct nv50_base *base = nv50_base(wndw); | |
1330 | u32 *push; | |
1331 | if ((push = evo_wait(&base->chan, 2))) { | |
1332 | evo_mthd(push, 0x00a4, 1); | |
1333 | evo_data(push, 0x00000000); | |
1334 | evo_kick(push, &base->chan); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | static void | |
1339 | nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1340 | { | |
1341 | struct nv50_base *base = nv50_base(wndw); | |
1342 | u32 *push; | |
1343 | if ((push = evo_wait(&base->chan, 3))) { | |
1344 | evo_mthd(push, 0x00a0, 2); | |
1345 | evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset); | |
1346 | evo_data(push, asyw->ntfy.handle); | |
1347 | evo_kick(push, &base->chan); | |
1348 | } | |
1349 | } | |
1350 | ||
1351 | static void | |
1352 | nv50_base_sema_clr(struct nv50_wndw *wndw) | |
1353 | { | |
1354 | struct nv50_base *base = nv50_base(wndw); | |
1355 | u32 *push; | |
1356 | if ((push = evo_wait(&base->chan, 2))) { | |
1357 | evo_mthd(push, 0x0094, 1); | |
1358 | evo_data(push, 0x00000000); | |
1359 | evo_kick(push, &base->chan); | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | static void | |
1364 | nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1365 | { | |
1366 | struct nv50_base *base = nv50_base(wndw); | |
1367 | u32 *push; | |
1368 | if ((push = evo_wait(&base->chan, 5))) { | |
1369 | evo_mthd(push, 0x0088, 4); | |
1370 | evo_data(push, asyw->sema.offset); | |
1371 | evo_data(push, asyw->sema.acquire); | |
1372 | evo_data(push, asyw->sema.release); | |
1373 | evo_data(push, asyw->sema.handle); | |
1374 | evo_kick(push, &base->chan); | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | static u32 | |
1379 | nv50_base_update(struct nv50_wndw *wndw, u32 interlock) | |
1380 | { | |
1381 | struct nv50_base *base = nv50_base(wndw); | |
1382 | u32 *push; | |
1383 | ||
1384 | if (!(push = evo_wait(&base->chan, 2))) | |
1385 | return 0; | |
1386 | evo_mthd(push, 0x0080, 1); | |
1387 | evo_data(push, interlock); | |
1388 | evo_kick(push, &base->chan); | |
1389 | ||
1390 | if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) | |
1391 | return interlock ? 2 << (base->id * 8) : 0; | |
1392 | return interlock ? 2 << (base->id * 4) : 0; | |
1393 | } | |
1394 | ||
1395 | static int | |
1396 | nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) | |
1397 | { | |
1398 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); | |
1399 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); | |
1400 | if (nvif_msec(&drm->device, 2000ULL, | |
1401 | u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4); | |
1402 | if ((data & 0xc0000000) == 0x40000000) | |
1403 | break; | |
1404 | usleep_range(1, 2); | |
1405 | ) < 0) | |
1406 | return -ETIMEDOUT; | |
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | static void | |
1411 | nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1412 | struct nv50_head_atom *asyh) | |
1413 | { | |
1414 | asyh->base.cpp = 0; | |
1415 | } | |
1416 | ||
1417 | static int | |
1418 | nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, | |
1419 | struct nv50_head_atom *asyh) | |
1420 | { | |
1421 | const u32 format = asyw->state.fb->pixel_format; | |
1422 | const struct drm_format_info *info; | |
1423 | int ret; | |
1424 | ||
1425 | info = drm_format_info(format); | |
1426 | if (!info || !info->depth) | |
1427 | return -EINVAL; | |
1428 | ||
1429 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, | |
1430 | DRM_PLANE_HELPER_NO_SCALING, | |
1431 | DRM_PLANE_HELPER_NO_SCALING, | |
1432 | false, true); | |
1433 | if (ret) | |
1434 | return ret; | |
1435 | ||
1436 | asyh->base.depth = info->depth; | |
1437 | asyh->base.cpp = info->cpp[0]; | |
1438 | asyh->base.x = asyw->state.src.x1 >> 16; | |
1439 | asyh->base.y = asyw->state.src.y1 >> 16; | |
1440 | asyh->base.w = asyw->state.fb->width; | |
1441 | asyh->base.h = asyw->state.fb->height; | |
1442 | ||
1443 | switch (format) { | |
1444 | case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; | |
1445 | case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; | |
1446 | case DRM_FORMAT_XRGB1555 : | |
1447 | case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; | |
1448 | case DRM_FORMAT_XRGB8888 : | |
1449 | case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; | |
1450 | case DRM_FORMAT_XBGR2101010: | |
1451 | case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break; | |
1452 | case DRM_FORMAT_XBGR8888 : | |
1453 | case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; | |
1454 | default: | |
1455 | WARN_ON(1); | |
1456 | return -EINVAL; | |
1457 | } | |
1458 | ||
1459 | asyw->lut.enable = 1; | |
1460 | asyw->set.image = true; | |
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | static void * | |
1465 | nv50_base_dtor(struct nv50_wndw *wndw) | |
1466 | { | |
1467 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); | |
1468 | struct nv50_base *base = nv50_base(wndw); | |
1469 | nv50_dmac_destroy(&base->chan.base, disp->disp); | |
1470 | return base; | |
1471 | } | |
1472 | ||
1473 | static const u32 | |
1474 | nv50_base_format[] = { | |
1475 | DRM_FORMAT_C8, | |
1476 | DRM_FORMAT_RGB565, | |
1477 | DRM_FORMAT_XRGB1555, | |
1478 | DRM_FORMAT_ARGB1555, | |
1479 | DRM_FORMAT_XRGB8888, | |
1480 | DRM_FORMAT_ARGB8888, | |
1481 | DRM_FORMAT_XBGR2101010, | |
1482 | DRM_FORMAT_ABGR2101010, | |
1483 | DRM_FORMAT_XBGR8888, | |
1484 | DRM_FORMAT_ABGR8888, | |
1485 | }; | |
1486 | ||
1487 | static const struct nv50_wndw_func | |
1488 | nv50_base = { | |
1489 | .dtor = nv50_base_dtor, | |
1490 | .acquire = nv50_base_acquire, | |
1491 | .release = nv50_base_release, | |
1492 | .sema_set = nv50_base_sema_set, | |
1493 | .sema_clr = nv50_base_sema_clr, | |
1494 | .ntfy_set = nv50_base_ntfy_set, | |
1495 | .ntfy_clr = nv50_base_ntfy_clr, | |
1496 | .ntfy_wait_begun = nv50_base_ntfy_wait_begun, | |
1497 | .image_set = nv50_base_image_set, | |
1498 | .image_clr = nv50_base_image_clr, | |
1499 | .lut = nv50_base_lut, | |
1500 | .update = nv50_base_update, | |
1501 | }; | |
1502 | ||
1503 | static int | |
1504 | nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head, | |
1505 | struct nv50_base **pbase) | |
1506 | { | |
1507 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
1508 | struct nv50_base *base; | |
1509 | int ret; | |
1510 | ||
1511 | if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL))) | |
1512 | return -ENOMEM; | |
1513 | base->id = head->base.index; | |
1514 | base->wndw.ntfy = EVO_FLIP_NTFY0(base->id); | |
1515 | base->wndw.sema = EVO_FLIP_SEM0(base->id); | |
1516 | base->wndw.data = 0x00000000; | |
1517 | ||
1518 | ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY, | |
1519 | "base", base->id, &base->chan.base, | |
1520 | nv50_base_format, ARRAY_SIZE(nv50_base_format), | |
1521 | &base->wndw); | |
1522 | if (ret) { | |
1523 | kfree(base); | |
1524 | return ret; | |
1525 | } | |
1526 | ||
1527 | ret = nv50_base_create(&drm->device, disp->disp, base->id, | |
1528 | disp->sync->bo.offset, &base->chan); | |
1529 | if (ret) | |
1530 | return ret; | |
1531 | ||
1532 | return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify, | |
1533 | false, | |
1534 | NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT, | |
1535 | &(struct nvif_notify_uevent_req) {}, | |
1536 | sizeof(struct nvif_notify_uevent_req), | |
1537 | sizeof(struct nvif_notify_uevent_rep), | |
1538 | &base->wndw.notify); | |
1539 | } | |
1540 | ||
3dbd036b BS |
1541 | /****************************************************************************** |
1542 | * Head | |
1543 | *****************************************************************************/ | |
7e08d67c BS |
1544 | static void |
1545 | nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1546 | { | |
1547 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1548 | u32 *push; | |
1549 | if ((push = evo_wait(core, 2))) { | |
1550 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1551 | evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1); | |
1552 | else | |
1553 | evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1); | |
1554 | evo_data(push, (asyh->procamp.sat.sin << 20) | | |
1555 | (asyh->procamp.sat.cos << 8)); | |
1556 | evo_kick(push, core); | |
1557 | } | |
1558 | } | |
1559 | ||
7e91833d BS |
1560 | static void |
1561 | nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1562 | { | |
1563 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1564 | u32 *push; | |
1565 | if ((push = evo_wait(core, 2))) { | |
1566 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1567 | evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1); | |
1568 | else | |
1569 | if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA) | |
1570 | evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1); | |
1571 | else | |
1572 | evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1); | |
1573 | evo_data(push, (asyh->dither.mode << 3) | | |
1574 | (asyh->dither.bits << 1) | | |
1575 | asyh->dither.enable); | |
1576 | evo_kick(push, core); | |
1577 | } | |
1578 | } | |
1579 | ||
6bbab3b6 BS |
1580 | static void |
1581 | nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1582 | { | |
1583 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1584 | u32 bounds = 0; | |
1585 | u32 *push; | |
1586 | ||
1587 | if (asyh->base.cpp) { | |
1588 | switch (asyh->base.cpp) { | |
1589 | case 8: bounds |= 0x00000500; break; | |
1590 | case 4: bounds |= 0x00000300; break; | |
1591 | case 2: bounds |= 0x00000100; break; | |
1592 | default: | |
1593 | WARN_ON(1); | |
1594 | break; | |
1595 | } | |
1596 | bounds |= 0x00000001; | |
1597 | } | |
1598 | ||
1599 | if ((push = evo_wait(core, 2))) { | |
1600 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1601 | evo_mthd(push, 0x0904 + head->base.index * 0x400, 1); | |
1602 | else | |
1603 | evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1); | |
1604 | evo_data(push, bounds); | |
1605 | evo_kick(push, core); | |
1606 | } | |
1607 | } | |
1608 | ||
1609 | static void | |
1610 | nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1611 | { | |
1612 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1613 | u32 bounds = 0; | |
1614 | u32 *push; | |
1615 | ||
1616 | if (asyh->base.cpp) { | |
1617 | switch (asyh->base.cpp) { | |
1618 | case 8: bounds |= 0x00000500; break; | |
1619 | case 4: bounds |= 0x00000300; break; | |
1620 | case 2: bounds |= 0x00000100; break; | |
1621 | case 1: bounds |= 0x00000000; break; | |
1622 | default: | |
1623 | WARN_ON(1); | |
1624 | break; | |
1625 | } | |
1626 | bounds |= 0x00000001; | |
1627 | } | |
1628 | ||
1629 | if ((push = evo_wait(core, 2))) { | |
1630 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1631 | evo_mthd(push, 0x0900 + head->base.index * 0x400, 1); | |
1632 | else | |
1633 | evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); | |
1634 | evo_data(push, bounds); | |
1635 | evo_kick(push, core); | |
1636 | } | |
1637 | } | |
1638 | ||
ea8ee390 BS |
1639 | static void |
1640 | nv50_head_curs_clr(struct nv50_head *head) | |
1641 | { | |
1642 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1643 | u32 *push; | |
1644 | if ((push = evo_wait(core, 4))) { | |
1645 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1646 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); | |
1647 | evo_data(push, 0x05000000); | |
1648 | } else | |
1649 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1650 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); | |
1651 | evo_data(push, 0x05000000); | |
1652 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); | |
1653 | evo_data(push, 0x00000000); | |
1654 | } else { | |
1655 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 1); | |
1656 | evo_data(push, 0x05000000); | |
1657 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); | |
1658 | evo_data(push, 0x00000000); | |
1659 | } | |
1660 | evo_kick(push, core); | |
1661 | } | |
1662 | } | |
1663 | ||
1664 | static void | |
1665 | nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1666 | { | |
1667 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1668 | u32 *push; | |
1669 | if ((push = evo_wait(core, 5))) { | |
1670 | if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) { | |
1671 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); | |
1672 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1673 | (asyh->curs.format << 24)); | |
1674 | evo_data(push, asyh->curs.offset >> 8); | |
1675 | } else | |
1676 | if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) { | |
1677 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); | |
1678 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1679 | (asyh->curs.format << 24)); | |
1680 | evo_data(push, asyh->curs.offset >> 8); | |
1681 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); | |
1682 | evo_data(push, asyh->curs.handle); | |
1683 | } else { | |
1684 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 2); | |
1685 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | | |
1686 | (asyh->curs.format << 24)); | |
1687 | evo_data(push, asyh->curs.offset >> 8); | |
1688 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); | |
1689 | evo_data(push, asyh->curs.handle); | |
1690 | } | |
1691 | evo_kick(push, core); | |
1692 | } | |
1693 | } | |
1694 | ||
ad633619 BS |
1695 | static void |
1696 | nv50_head_core_clr(struct nv50_head *head) | |
1697 | { | |
1698 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1699 | u32 *push; | |
1700 | if ((push = evo_wait(core, 2))) { | |
1701 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) | |
1702 | evo_mthd(push, 0x0874 + head->base.index * 0x400, 1); | |
1703 | else | |
1704 | evo_mthd(push, 0x0474 + head->base.index * 0x300, 1); | |
1705 | evo_data(push, 0x00000000); | |
1706 | evo_kick(push, core); | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | static void | |
1711 | nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1712 | { | |
1713 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1714 | u32 *push; | |
1715 | if ((push = evo_wait(core, 9))) { | |
1716 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1717 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); | |
1718 | evo_data(push, asyh->core.offset >> 8); | |
1719 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); | |
1720 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1721 | evo_data(push, asyh->core.layout << 20 | | |
1722 | (asyh->core.pitch >> 8) << 8 | | |
1723 | asyh->core.block); | |
1724 | evo_data(push, asyh->core.kind << 16 | | |
1725 | asyh->core.format << 8); | |
1726 | evo_data(push, asyh->core.handle); | |
1727 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); | |
1728 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
1729 | } else | |
1730 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1731 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); | |
1732 | evo_data(push, asyh->core.offset >> 8); | |
1733 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); | |
1734 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1735 | evo_data(push, asyh->core.layout << 20 | | |
1736 | (asyh->core.pitch >> 8) << 8 | | |
1737 | asyh->core.block); | |
1738 | evo_data(push, asyh->core.format << 8); | |
1739 | evo_data(push, asyh->core.handle); | |
1740 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); | |
1741 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
1742 | } else { | |
1743 | evo_mthd(push, 0x0460 + head->base.index * 0x300, 1); | |
1744 | evo_data(push, asyh->core.offset >> 8); | |
1745 | evo_mthd(push, 0x0468 + head->base.index * 0x300, 4); | |
1746 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); | |
1747 | evo_data(push, asyh->core.layout << 24 | | |
1748 | (asyh->core.pitch >> 8) << 8 | | |
1749 | asyh->core.block); | |
1750 | evo_data(push, asyh->core.format << 8); | |
1751 | evo_data(push, asyh->core.handle); | |
1752 | evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1); | |
1753 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); | |
1754 | } | |
1755 | evo_kick(push, core); | |
1756 | } | |
1757 | } | |
1758 | ||
a7ae1561 BS |
1759 | static void |
1760 | nv50_head_lut_clr(struct nv50_head *head) | |
1761 | { | |
1762 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1763 | u32 *push; | |
1764 | if ((push = evo_wait(core, 4))) { | |
1765 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1766 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); | |
1767 | evo_data(push, 0x40000000); | |
1768 | } else | |
1769 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1770 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); | |
1771 | evo_data(push, 0x40000000); | |
1772 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); | |
1773 | evo_data(push, 0x00000000); | |
1774 | } else { | |
1775 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1); | |
1776 | evo_data(push, 0x03000000); | |
1777 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); | |
1778 | evo_data(push, 0x00000000); | |
1779 | } | |
1780 | evo_kick(push, core); | |
1781 | } | |
1782 | } | |
1783 | ||
1784 | static void | |
1785 | nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1786 | { | |
1787 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1788 | u32 *push; | |
1789 | if ((push = evo_wait(core, 7))) { | |
1790 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { | |
1791 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); | |
1792 | evo_data(push, 0xc0000000); | |
1793 | evo_data(push, asyh->lut.offset >> 8); | |
1794 | } else | |
1795 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1796 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); | |
1797 | evo_data(push, 0xc0000000); | |
1798 | evo_data(push, asyh->lut.offset >> 8); | |
1799 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); | |
1800 | evo_data(push, asyh->lut.handle); | |
1801 | } else { | |
1802 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4); | |
1803 | evo_data(push, 0x83000000); | |
1804 | evo_data(push, asyh->lut.offset >> 8); | |
1805 | evo_data(push, 0x00000000); | |
1806 | evo_data(push, 0x00000000); | |
1807 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); | |
1808 | evo_data(push, asyh->lut.handle); | |
1809 | } | |
1810 | evo_kick(push, core); | |
1811 | } | |
1812 | } | |
1813 | ||
3dbd036b BS |
1814 | static void |
1815 | nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1816 | { | |
1817 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1818 | struct nv50_head_mode *m = &asyh->mode; | |
1819 | u32 *push; | |
1820 | if ((push = evo_wait(core, 14))) { | |
1821 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1822 | evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2); | |
1823 | evo_data(push, 0x00800000 | m->clock); | |
1824 | evo_data(push, m->interlace ? 0x00000002 : 0x00000000); | |
06ab282f | 1825 | evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7); |
3dbd036b BS |
1826 | evo_data(push, 0x00000000); |
1827 | evo_data(push, (m->v.active << 16) | m->h.active ); | |
1828 | evo_data(push, (m->v.synce << 16) | m->h.synce ); | |
1829 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); | |
1830 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); | |
1831 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); | |
06ab282f | 1832 | evo_data(push, asyh->mode.v.blankus); |
3dbd036b BS |
1833 | evo_mthd(push, 0x082c + (head->base.index * 0x400), 1); |
1834 | evo_data(push, 0x00000000); | |
1835 | } else { | |
1836 | evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6); | |
1837 | evo_data(push, 0x00000000); | |
1838 | evo_data(push, (m->v.active << 16) | m->h.active ); | |
1839 | evo_data(push, (m->v.synce << 16) | m->h.synce ); | |
1840 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); | |
1841 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); | |
1842 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); | |
1843 | evo_mthd(push, 0x042c + (head->base.index * 0x300), 2); | |
1844 | evo_data(push, 0x00000000); /* ??? */ | |
1845 | evo_data(push, 0xffffff00); | |
1846 | evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3); | |
1847 | evo_data(push, m->clock * 1000); | |
1848 | evo_data(push, 0x00200000); /* ??? */ | |
1849 | evo_data(push, m->clock * 1000); | |
1850 | } | |
1851 | evo_kick(push, core); | |
1852 | } | |
1853 | } | |
1854 | ||
c4e6812c BS |
1855 | static void |
1856 | nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1857 | { | |
1858 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; | |
1859 | u32 *push; | |
1860 | if ((push = evo_wait(core, 10))) { | |
1861 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { | |
1862 | evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1); | |
1863 | evo_data(push, 0x00000000); | |
1864 | evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1); | |
1865 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); | |
1866 | evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2); | |
1867 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1868 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1869 | } else { | |
1870 | evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1); | |
1871 | evo_data(push, 0x00000000); | |
1872 | evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1); | |
1873 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); | |
1874 | evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3); | |
1875 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1876 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1877 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); | |
1878 | } | |
1879 | evo_kick(push, core); | |
1880 | } | |
1881 | } | |
1882 | ||
ad633619 BS |
1883 | static void |
1884 | nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y) | |
1885 | { | |
a7ae1561 BS |
1886 | if (asyh->clr.core && (!asyh->set.core || y)) |
1887 | nv50_head_lut_clr(head); | |
ad633619 BS |
1888 | if (asyh->clr.core && (!asyh->set.core || y)) |
1889 | nv50_head_core_clr(head); | |
ea8ee390 BS |
1890 | if (asyh->clr.curs && (!asyh->set.curs || y)) |
1891 | nv50_head_curs_clr(head); | |
ad633619 BS |
1892 | } |
1893 | ||
3dbd036b BS |
1894 | static void |
1895 | nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) | |
1896 | { | |
c4e6812c | 1897 | if (asyh->set.view ) nv50_head_view (head, asyh); |
3dbd036b | 1898 | if (asyh->set.mode ) nv50_head_mode (head, asyh); |
a7ae1561 | 1899 | if (asyh->set.core ) nv50_head_lut_set (head, asyh); |
ad633619 | 1900 | if (asyh->set.core ) nv50_head_core_set(head, asyh); |
ea8ee390 | 1901 | if (asyh->set.curs ) nv50_head_curs_set(head, asyh); |
6bbab3b6 BS |
1902 | if (asyh->set.base ) nv50_head_base (head, asyh); |
1903 | if (asyh->set.ovly ) nv50_head_ovly (head, asyh); | |
7e91833d | 1904 | if (asyh->set.dither ) nv50_head_dither (head, asyh); |
7e08d67c BS |
1905 | if (asyh->set.procamp) nv50_head_procamp (head, asyh); |
1906 | } | |
1907 | ||
1908 | static void | |
1909 | nv50_head_atomic_check_procamp(struct nv50_head_atom *armh, | |
1910 | struct nv50_head_atom *asyh, | |
1911 | struct nouveau_conn_atom *asyc) | |
1912 | { | |
1913 | const int vib = asyc->procamp.color_vibrance - 100; | |
1914 | const int hue = asyc->procamp.vibrant_hue - 90; | |
1915 | const int adj = (vib > 0) ? 50 : 0; | |
1916 | asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; | |
1917 | asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; | |
1918 | asyh->set.procamp = true; | |
7e91833d BS |
1919 | } |
1920 | ||
1921 | static void | |
1922 | nv50_head_atomic_check_dither(struct nv50_head_atom *armh, | |
1923 | struct nv50_head_atom *asyh, | |
1924 | struct nouveau_conn_atom *asyc) | |
1925 | { | |
1926 | struct drm_connector *connector = asyc->state.connector; | |
1927 | u32 mode = 0x00; | |
1928 | ||
1929 | if (asyc->dither.mode == DITHERING_MODE_AUTO) { | |
1930 | if (asyh->base.depth > connector->display_info.bpc * 3) | |
1931 | mode = DITHERING_MODE_DYNAMIC2X2; | |
1932 | } else { | |
1933 | mode = asyc->dither.mode; | |
1934 | } | |
1935 | ||
1936 | if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { | |
1937 | if (connector->display_info.bpc >= 8) | |
1938 | mode |= DITHERING_DEPTH_8BPC; | |
1939 | } else { | |
1940 | mode |= asyc->dither.depth; | |
1941 | } | |
1942 | ||
1943 | asyh->dither.enable = mode; | |
1944 | asyh->dither.bits = mode >> 1; | |
1945 | asyh->dither.mode = mode >> 3; | |
1946 | asyh->set.dither = true; | |
3dbd036b BS |
1947 | } |
1948 | ||
c4e6812c BS |
1949 | static void |
1950 | nv50_head_atomic_check_view(struct nv50_head_atom *armh, | |
1951 | struct nv50_head_atom *asyh, | |
1952 | struct nouveau_conn_atom *asyc) | |
1953 | { | |
1954 | struct drm_connector *connector = asyc->state.connector; | |
1955 | struct drm_display_mode *omode = &asyh->state.adjusted_mode; | |
1956 | struct drm_display_mode *umode = &asyh->state.mode; | |
1957 | int mode = asyc->scaler.mode; | |
1958 | struct edid *edid; | |
1959 | ||
1960 | if (connector->edid_blob_ptr) | |
1961 | edid = (struct edid *)connector->edid_blob_ptr->data; | |
1962 | else | |
1963 | edid = NULL; | |
1964 | ||
1965 | if (!asyc->scaler.full) { | |
1966 | if (mode == DRM_MODE_SCALE_NONE) | |
1967 | omode = umode; | |
1968 | } else { | |
1969 | /* Non-EDID LVDS/eDP mode. */ | |
1970 | mode = DRM_MODE_SCALE_FULLSCREEN; | |
1971 | } | |
1972 | ||
1973 | asyh->view.iW = umode->hdisplay; | |
1974 | asyh->view.iH = umode->vdisplay; | |
1975 | asyh->view.oW = omode->hdisplay; | |
1976 | asyh->view.oH = omode->vdisplay; | |
1977 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1978 | asyh->view.oH *= 2; | |
1979 | ||
1980 | /* Add overscan compensation if necessary, will keep the aspect | |
1981 | * ratio the same as the backend mode unless overridden by the | |
1982 | * user setting both hborder and vborder properties. | |
1983 | */ | |
1984 | if ((asyc->scaler.underscan.mode == UNDERSCAN_ON || | |
1985 | (asyc->scaler.underscan.mode == UNDERSCAN_AUTO && | |
1986 | drm_detect_hdmi_monitor(edid)))) { | |
1987 | u32 bX = asyc->scaler.underscan.hborder; | |
1988 | u32 bY = asyc->scaler.underscan.vborder; | |
1989 | u32 r = (asyh->view.oH << 19) / asyh->view.oW; | |
1990 | ||
1991 | if (bX) { | |
1992 | asyh->view.oW -= (bX * 2); | |
1993 | if (bY) asyh->view.oH -= (bY * 2); | |
1994 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
1995 | } else { | |
1996 | asyh->view.oW -= (asyh->view.oW >> 4) + 32; | |
1997 | if (bY) asyh->view.oH -= (bY * 2); | |
1998 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | /* Handle CENTER/ASPECT scaling, taking into account the areas | |
2003 | * removed already for overscan compensation. | |
2004 | */ | |
2005 | switch (mode) { | |
2006 | case DRM_MODE_SCALE_CENTER: | |
2007 | asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW); | |
2008 | asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH); | |
2009 | /* fall-through */ | |
2010 | case DRM_MODE_SCALE_ASPECT: | |
2011 | if (asyh->view.oH < asyh->view.oW) { | |
2012 | u32 r = (asyh->view.iW << 19) / asyh->view.iH; | |
2013 | asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; | |
2014 | } else { | |
2015 | u32 r = (asyh->view.iH << 19) / asyh->view.iW; | |
2016 | asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; | |
2017 | } | |
2018 | break; | |
2019 | default: | |
2020 | break; | |
2021 | } | |
2022 | ||
2023 | asyh->set.view = true; | |
2024 | } | |
2025 | ||
3dbd036b BS |
2026 | static void |
2027 | nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) | |
2028 | { | |
2029 | struct drm_display_mode *mode = &asyh->state.adjusted_mode; | |
2030 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; | |
2031 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
2032 | u32 hbackp = mode->htotal - mode->hsync_end; | |
2033 | u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
2034 | u32 hfrontp = mode->hsync_start - mode->hdisplay; | |
2035 | u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
2036 | struct nv50_head_mode *m = &asyh->mode; | |
2037 | ||
2038 | m->h.active = mode->htotal; | |
2039 | m->h.synce = mode->hsync_end - mode->hsync_start - 1; | |
2040 | m->h.blanke = m->h.synce + hbackp; | |
2041 | m->h.blanks = mode->htotal - hfrontp - 1; | |
2042 | ||
2043 | m->v.active = mode->vtotal * vscan / ilace; | |
2044 | m->v.synce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
2045 | m->v.blanke = m->v.synce + vbackp; | |
2046 | m->v.blanks = m->v.active - vfrontp - 1; | |
2047 | ||
2048 | /*XXX: Safe underestimate, even "0" works */ | |
2049 | m->v.blankus = (m->v.active - mode->vdisplay - 2) * m->h.active; | |
2050 | m->v.blankus *= 1000; | |
2051 | m->v.blankus /= mode->clock; | |
2052 | ||
2053 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
2054 | m->v.blank2e = m->v.active + m->v.synce + vbackp; | |
2055 | m->v.blank2s = m->v.blank2e + (mode->vdisplay * vscan / ilace); | |
2056 | m->v.active = (m->v.active * 2) + 1; | |
2057 | m->interlace = true; | |
2058 | } else { | |
2059 | m->v.blank2e = 0; | |
2060 | m->v.blank2s = 1; | |
2061 | m->interlace = false; | |
2062 | } | |
2063 | m->clock = mode->clock; | |
2064 | ||
2065 | drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); | |
2066 | asyh->set.mode = true; | |
2067 | } | |
2068 | ||
2069 | static int | |
2070 | nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) | |
2071 | { | |
2072 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); | |
ad633619 | 2073 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
3dbd036b | 2074 | struct nv50_head *head = nv50_head(crtc); |
839ca903 | 2075 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); |
3dbd036b | 2076 | struct nv50_head_atom *asyh = nv50_head_atom(state); |
839ca903 BS |
2077 | struct nouveau_conn_atom *asyc = NULL; |
2078 | struct drm_connector_state *conns; | |
2079 | struct drm_connector *conn; | |
2080 | int i; | |
3dbd036b BS |
2081 | |
2082 | NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); | |
3dbd036b | 2083 | if (asyh->state.active) { |
839ca903 BS |
2084 | for_each_connector_in_state(asyh->state.state, conn, conns, i) { |
2085 | if (conns->crtc == crtc) { | |
2086 | asyc = nouveau_conn_atom(conns); | |
2087 | break; | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | if (armh->state.active) { | |
2092 | if (asyc) { | |
2093 | if (asyh->state.mode_changed) | |
2094 | asyc->set.scaler = true; | |
2095 | if (armh->base.depth != asyh->base.depth) | |
2096 | asyc->set.dither = true; | |
2097 | } | |
2098 | } else { | |
2099 | asyc->set.mask = ~0; | |
2100 | asyh->set.mask = ~0; | |
2101 | } | |
2102 | ||
3dbd036b BS |
2103 | if (asyh->state.mode_changed) |
2104 | nv50_head_atomic_check_mode(head, asyh); | |
ad633619 | 2105 | |
839ca903 BS |
2106 | if (asyc) { |
2107 | if (asyc->set.scaler) | |
2108 | nv50_head_atomic_check_view(armh, asyh, asyc); | |
2109 | if (asyc->set.dither) | |
2110 | nv50_head_atomic_check_dither(armh, asyh, asyc); | |
2111 | if (asyc->set.procamp) | |
2112 | nv50_head_atomic_check_procamp(armh, asyh, asyc); | |
2113 | } | |
2114 | ||
ad633619 BS |
2115 | if ((asyh->core.visible = (asyh->base.cpp != 0))) { |
2116 | asyh->core.x = asyh->base.x; | |
2117 | asyh->core.y = asyh->base.y; | |
2118 | asyh->core.w = asyh->base.w; | |
2119 | asyh->core.h = asyh->base.h; | |
2120 | } else | |
ea8ee390 | 2121 | if ((asyh->core.visible = asyh->curs.visible)) { |
ad633619 BS |
2122 | /*XXX: We need to either find some way of having the |
2123 | * primary base layer appear black, while still | |
2124 | * being able to display the other layers, or we | |
2125 | * need to allocate a dummy black surface here. | |
2126 | */ | |
2127 | asyh->core.x = 0; | |
2128 | asyh->core.y = 0; | |
2129 | asyh->core.w = asyh->state.mode.hdisplay; | |
2130 | asyh->core.h = asyh->state.mode.vdisplay; | |
2131 | } | |
2132 | asyh->core.handle = disp->mast.base.vram.handle; | |
2133 | asyh->core.offset = 0; | |
2134 | asyh->core.format = 0xcf; | |
2135 | asyh->core.kind = 0; | |
2136 | asyh->core.layout = 1; | |
2137 | asyh->core.block = 0; | |
2138 | asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; | |
a7ae1561 BS |
2139 | asyh->lut.handle = disp->mast.base.vram.handle; |
2140 | asyh->lut.offset = head->base.lut.nvbo->bo.offset; | |
6bbab3b6 BS |
2141 | asyh->set.base = armh->base.cpp != asyh->base.cpp; |
2142 | asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; | |
ad633619 BS |
2143 | } else { |
2144 | asyh->core.visible = false; | |
ea8ee390 | 2145 | asyh->curs.visible = false; |
6bbab3b6 BS |
2146 | asyh->base.cpp = 0; |
2147 | asyh->ovly.cpp = 0; | |
ad633619 BS |
2148 | } |
2149 | ||
2150 | if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { | |
2151 | if (asyh->core.visible) { | |
2152 | if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) | |
2153 | asyh->set.core = true; | |
2154 | } else | |
2155 | if (armh->core.visible) { | |
2156 | asyh->clr.core = true; | |
2157 | } | |
ea8ee390 BS |
2158 | |
2159 | if (asyh->curs.visible) { | |
2160 | if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) | |
2161 | asyh->set.curs = true; | |
2162 | } else | |
2163 | if (armh->curs.visible) { | |
2164 | asyh->clr.curs = true; | |
2165 | } | |
ad633619 BS |
2166 | } else { |
2167 | asyh->clr.core = armh->core.visible; | |
ea8ee390 | 2168 | asyh->clr.curs = armh->curs.visible; |
ad633619 | 2169 | asyh->set.core = asyh->core.visible; |
ea8ee390 | 2170 | asyh->set.curs = asyh->curs.visible; |
3dbd036b BS |
2171 | } |
2172 | ||
839ca903 BS |
2173 | if (asyh->clr.mask || asyh->set.mask) |
2174 | nv50_atom(asyh->state.state)->lock_core = true; | |
3dbd036b BS |
2175 | return 0; |
2176 | } | |
2177 | ||
438d99e3 | 2178 | static void |
9bfdee9a | 2179 | nv50_head_lut_load(struct drm_crtc *crtc) |
438d99e3 | 2180 | { |
e225f446 | 2181 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
2182 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
2183 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
2184 | int i; | |
2185 | ||
2186 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
2187 | u16 r = nv_crtc->lut.r[i] >> 2; |
2188 | u16 g = nv_crtc->lut.g[i] >> 2; | |
2189 | u16 b = nv_crtc->lut.b[i] >> 2; | |
2190 | ||
648d4dfd | 2191 | if (disp->disp->oclass < GF110_DISP) { |
de8268c5 BS |
2192 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
2193 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
2194 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
2195 | } else { | |
2196 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
2197 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
2198 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
2199 | } | |
438d99e3 BS |
2200 | } |
2201 | } | |
2202 | ||
7ea77283 | 2203 | static int |
9bfdee9a BS |
2204 | nv50_head_mode_set_base_atomic(struct drm_crtc *crtc, |
2205 | struct drm_framebuffer *fb, int x, int y, | |
2206 | enum mode_set_atomic state) | |
438d99e3 | 2207 | { |
9bfdee9a | 2208 | WARN_ON(1); |
7ea77283 | 2209 | return 0; |
438d99e3 BS |
2210 | } |
2211 | ||
9bfdee9a BS |
2212 | static const struct drm_crtc_helper_funcs |
2213 | nv50_head_help = { | |
2214 | .mode_set_base_atomic = nv50_head_mode_set_base_atomic, | |
2215 | .load_lut = nv50_head_lut_load, | |
839ca903 | 2216 | .atomic_check = nv50_head_atomic_check, |
438d99e3 BS |
2217 | }; |
2218 | ||
839ca903 BS |
2219 | /* This is identical to the version in the atomic helpers, except that |
2220 | * it supports non-vblanked ("async") page flips. | |
2221 | */ | |
2222 | static int | |
2223 | nv50_head_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2224 | struct drm_pending_vblank_event *event, u32 flags) | |
2225 | { | |
2226 | struct drm_plane *plane = crtc->primary; | |
2227 | struct drm_atomic_state *state; | |
2228 | struct drm_plane_state *plane_state; | |
2229 | struct drm_crtc_state *crtc_state; | |
2230 | int ret = 0; | |
2231 | ||
2232 | state = drm_atomic_state_alloc(plane->dev); | |
2233 | if (!state) | |
2234 | return -ENOMEM; | |
2235 | ||
2236 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
2237 | retry: | |
2238 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
2239 | if (IS_ERR(crtc_state)) { | |
2240 | ret = PTR_ERR(crtc_state); | |
2241 | goto fail; | |
2242 | } | |
2243 | crtc_state->event = event; | |
2244 | ||
2245 | plane_state = drm_atomic_get_plane_state(state, plane); | |
2246 | if (IS_ERR(plane_state)) { | |
2247 | ret = PTR_ERR(plane_state); | |
2248 | goto fail; | |
2249 | } | |
2250 | ||
2251 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
2252 | if (ret != 0) | |
2253 | goto fail; | |
2254 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
2255 | ||
2256 | /* Make sure we don't accidentally do a full modeset. */ | |
2257 | state->allow_modeset = false; | |
2258 | if (!crtc_state->active) { | |
2259 | DRM_DEBUG_ATOMIC("[CRTC:%d] disabled, rejecting legacy flip\n", | |
2260 | crtc->base.id); | |
2261 | ret = -EINVAL; | |
2262 | goto fail; | |
2263 | } | |
2264 | ||
2265 | if (flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
2266 | nv50_wndw_atom(plane_state)->interval = 0; | |
2267 | ||
2268 | ret = drm_atomic_nonblocking_commit(state); | |
2269 | fail: | |
2270 | if (ret == -EDEADLK) | |
2271 | goto backoff; | |
2272 | ||
2273 | drm_atomic_state_put(state); | |
2274 | return ret; | |
2275 | ||
2276 | backoff: | |
2277 | drm_atomic_state_clear(state); | |
2278 | drm_atomic_legacy_backoff(state); | |
2279 | ||
2280 | /* | |
2281 | * Someone might have exchanged the framebuffer while we dropped locks | |
2282 | * in the backoff code. We need to fix up the fb refcount tracking the | |
2283 | * core does for us. | |
2284 | */ | |
2285 | plane->old_fb = plane->fb; | |
2286 | ||
2287 | goto retry; | |
2288 | } | |
2289 | ||
9bfdee9a BS |
2290 | static int |
2291 | nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
2292 | uint32_t size) | |
2293 | { | |
2294 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
2295 | u32 i; | |
2296 | ||
2297 | for (i = 0; i < size; i++) { | |
2298 | nv_crtc->lut.r[i] = r[i]; | |
2299 | nv_crtc->lut.g[i] = g[i]; | |
2300 | nv_crtc->lut.b[i] = b[i]; | |
2301 | } | |
2302 | ||
2303 | nv50_head_lut_load(crtc); | |
2304 | return 0; | |
2305 | } | |
2306 | ||
839ca903 BS |
2307 | static void |
2308 | nv50_head_atomic_destroy_state(struct drm_crtc *crtc, | |
2309 | struct drm_crtc_state *state) | |
2310 | { | |
2311 | struct nv50_head_atom *asyh = nv50_head_atom(state); | |
2312 | __drm_atomic_helper_crtc_destroy_state(&asyh->state); | |
2313 | kfree(asyh); | |
2314 | } | |
2315 | ||
2316 | static struct drm_crtc_state * | |
2317 | nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) | |
2318 | { | |
2319 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); | |
2320 | struct nv50_head_atom *asyh; | |
2321 | if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) | |
2322 | return NULL; | |
2323 | __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); | |
2324 | asyh->view = armh->view; | |
2325 | asyh->mode = armh->mode; | |
2326 | asyh->lut = armh->lut; | |
2327 | asyh->core = armh->core; | |
2328 | asyh->curs = armh->curs; | |
2329 | asyh->base = armh->base; | |
2330 | asyh->ovly = armh->ovly; | |
2331 | asyh->dither = armh->dither; | |
2332 | asyh->procamp = armh->procamp; | |
2333 | asyh->clr.mask = 0; | |
2334 | asyh->set.mask = 0; | |
2335 | return &asyh->state; | |
2336 | } | |
2337 | ||
2338 | static void | |
2339 | __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, | |
2340 | struct drm_crtc_state *state) | |
2341 | { | |
2342 | if (crtc->state) | |
2343 | crtc->funcs->atomic_destroy_state(crtc, crtc->state); | |
2344 | crtc->state = state; | |
2345 | crtc->state->crtc = crtc; | |
2346 | } | |
2347 | ||
2348 | static void | |
2349 | nv50_head_reset(struct drm_crtc *crtc) | |
2350 | { | |
2351 | struct nv50_head_atom *asyh; | |
2352 | ||
2353 | if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) | |
2354 | return; | |
2355 | ||
2356 | __drm_atomic_helper_crtc_reset(crtc, &asyh->state); | |
2357 | } | |
2358 | ||
9bfdee9a BS |
2359 | static void |
2360 | nv50_head_destroy(struct drm_crtc *crtc) | |
2361 | { | |
2362 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
2363 | struct nv50_disp *disp = nv50_disp(crtc->dev); | |
2364 | struct nv50_head *head = nv50_head(crtc); | |
2365 | ||
2366 | nv50_dmac_destroy(&head->ovly.base, disp->disp); | |
2367 | nv50_pioc_destroy(&head->oimm.base); | |
2368 | ||
2369 | nouveau_bo_unmap(nv_crtc->lut.nvbo); | |
2370 | if (nv_crtc->lut.nvbo) | |
2371 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
2372 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
2373 | ||
2374 | drm_crtc_cleanup(crtc); | |
2375 | kfree(crtc); | |
2376 | } | |
2377 | ||
2378 | static const struct drm_crtc_funcs | |
2379 | nv50_head_func = { | |
839ca903 | 2380 | .reset = nv50_head_reset, |
9bfdee9a BS |
2381 | .gamma_set = nv50_head_gamma_set, |
2382 | .destroy = nv50_head_destroy, | |
839ca903 BS |
2383 | .set_config = drm_atomic_helper_set_config, |
2384 | .page_flip = nv50_head_page_flip, | |
2385 | .set_property = drm_atomic_helper_crtc_set_property, | |
2386 | .atomic_duplicate_state = nv50_head_atomic_duplicate_state, | |
2387 | .atomic_destroy_state = nv50_head_atomic_destroy_state, | |
438d99e3 BS |
2388 | }; |
2389 | ||
2390 | static int | |
9bfdee9a | 2391 | nv50_head_create(struct drm_device *dev, int index) |
438d99e3 | 2392 | { |
a01ca78c BS |
2393 | struct nouveau_drm *drm = nouveau_drm(dev); |
2394 | struct nvif_device *device = &drm->device; | |
e225f446 BS |
2395 | struct nv50_disp *disp = nv50_disp(dev); |
2396 | struct nv50_head *head; | |
973f10c2 | 2397 | struct nv50_base *base; |
22e927d2 | 2398 | struct nv50_curs *curs; |
438d99e3 BS |
2399 | struct drm_crtc *crtc; |
2400 | int ret, i; | |
2401 | ||
dd0e3d53 BS |
2402 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
2403 | if (!head) | |
438d99e3 BS |
2404 | return -ENOMEM; |
2405 | ||
dd0e3d53 | 2406 | head->base.index = index; |
438d99e3 | 2407 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
2408 | head->base.lut.r[i] = i << 8; |
2409 | head->base.lut.g[i] = i << 8; | |
2410 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
2411 | } |
2412 | ||
973f10c2 | 2413 | ret = nv50_base_new(drm, head, &base); |
22e927d2 BS |
2414 | if (ret == 0) |
2415 | ret = nv50_curs_new(drm, head, &curs); | |
973f10c2 BS |
2416 | if (ret) { |
2417 | kfree(head); | |
2418 | return ret; | |
2419 | } | |
2420 | ||
dd0e3d53 | 2421 | crtc = &head->base.base; |
839ca903 | 2422 | drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane, |
9bfdee9a | 2423 | &curs->wndw.plane, &nv50_head_func, |
839ca903 | 2424 | "head-%d", head->base.index); |
9bfdee9a | 2425 | drm_crtc_helper_add(crtc, &nv50_head_help); |
438d99e3 BS |
2426 | drm_mode_crtc_set_gamma_size(crtc, 256); |
2427 | ||
b5a794b0 | 2428 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 2429 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
b5a794b0 | 2430 | if (!ret) { |
547ad072 | 2431 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 2432 | if (!ret) { |
b5a794b0 | 2433 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
2434 | if (ret) |
2435 | nouveau_bo_unpin(head->base.lut.nvbo); | |
2436 | } | |
b5a794b0 BS |
2437 | if (ret) |
2438 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
2439 | } | |
2440 | ||
438d99e3 BS |
2441 | if (ret) |
2442 | goto out; | |
2443 | ||
b5a794b0 | 2444 | /* allocate overlay resources */ |
a01ca78c | 2445 | ret = nv50_oimm_create(device, disp->disp, index, &head->oimm); |
438d99e3 BS |
2446 | if (ret) |
2447 | goto out; | |
2448 | ||
a01ca78c BS |
2449 | ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset, |
2450 | &head->ovly); | |
b5a794b0 BS |
2451 | if (ret) |
2452 | goto out; | |
438d99e3 BS |
2453 | |
2454 | out: | |
2455 | if (ret) | |
9bfdee9a | 2456 | nv50_head_destroy(crtc); |
438d99e3 BS |
2457 | return ret; |
2458 | } | |
2459 | ||
a91d3221 | 2460 | /****************************************************************************** |
d92c8adf | 2461 | * Output path helpers |
a91d3221 | 2462 | *****************************************************************************/ |
d92c8adf BS |
2463 | static int |
2464 | nv50_outp_atomic_check_view(struct drm_encoder *encoder, | |
2465 | struct drm_crtc_state *crtc_state, | |
2466 | struct drm_connector_state *conn_state, | |
2467 | struct drm_display_mode *native_mode) | |
2468 | { | |
2469 | struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; | |
2470 | struct drm_display_mode *mode = &crtc_state->mode; | |
2471 | struct drm_connector *connector = conn_state->connector; | |
2472 | struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); | |
2473 | struct nouveau_drm *drm = nouveau_drm(encoder->dev); | |
2474 | ||
2475 | NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); | |
2476 | asyc->scaler.full = false; | |
2477 | if (!native_mode) | |
2478 | return 0; | |
2479 | ||
2480 | if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { | |
2481 | switch (connector->connector_type) { | |
2482 | case DRM_MODE_CONNECTOR_LVDS: | |
2483 | case DRM_MODE_CONNECTOR_eDP: | |
2484 | /* Force use of scaler for non-EDID modes. */ | |
2485 | if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) | |
2486 | break; | |
2487 | mode = native_mode; | |
2488 | asyc->scaler.full = true; | |
2489 | break; | |
2490 | default: | |
2491 | break; | |
2492 | } | |
2493 | } else { | |
2494 | mode = native_mode; | |
2495 | } | |
2496 | ||
2497 | if (!drm_mode_equal(adjusted_mode, mode)) { | |
2498 | drm_mode_copy(adjusted_mode, mode); | |
2499 | crtc_state->mode_changed = true; | |
2500 | } | |
2501 | ||
2502 | return 0; | |
2503 | } | |
2504 | ||
839ca903 BS |
2505 | static int |
2506 | nv50_outp_atomic_check(struct drm_encoder *encoder, | |
2507 | struct drm_crtc_state *crtc_state, | |
2508 | struct drm_connector_state *conn_state) | |
a91d3221 | 2509 | { |
839ca903 BS |
2510 | struct nouveau_connector *nv_connector = |
2511 | nouveau_connector(conn_state->connector); | |
2512 | return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, | |
2513 | nv_connector->native_mode); | |
a91d3221 BS |
2514 | } |
2515 | ||
26f6d88b BS |
2516 | /****************************************************************************** |
2517 | * DAC | |
2518 | *****************************************************************************/ | |
8eaa9669 | 2519 | static void |
e225f446 | 2520 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
2521 | { |
2522 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 2523 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
bf0eb898 BS |
2524 | struct { |
2525 | struct nv50_disp_mthd_v1 base; | |
2526 | struct nv50_disp_dac_pwr_v0 pwr; | |
2527 | } args = { | |
2528 | .base.version = 1, | |
2529 | .base.method = NV50_DISP_MTHD_V1_DAC_PWR, | |
2530 | .base.hasht = nv_encoder->dcb->hasht, | |
2531 | .base.hashm = nv_encoder->dcb->hashm, | |
2532 | .pwr.state = 1, | |
2533 | .pwr.data = 1, | |
2534 | .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && | |
2535 | mode != DRM_MODE_DPMS_OFF), | |
2536 | .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && | |
2537 | mode != DRM_MODE_DPMS_OFF), | |
2538 | }; | |
8eaa9669 | 2539 | |
bf0eb898 | 2540 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
8eaa9669 BS |
2541 | } |
2542 | ||
8eaa9669 | 2543 | static void |
839ca903 | 2544 | nv50_dac_disable(struct drm_encoder *encoder) |
8eaa9669 | 2545 | { |
f20c665c BS |
2546 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2547 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2548 | const int or = nv_encoder->or; | |
2549 | u32 *push; | |
2550 | ||
2551 | if (nv_encoder->crtc) { | |
f20c665c BS |
2552 | push = evo_wait(mast, 4); |
2553 | if (push) { | |
2554 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { | |
2555 | evo_mthd(push, 0x0400 + (or * 0x080), 1); | |
2556 | evo_data(push, 0x00000000); | |
2557 | } else { | |
2558 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
2559 | evo_data(push, 0x00000000); | |
2560 | } | |
2561 | evo_kick(push, mast); | |
2562 | } | |
2563 | } | |
2564 | ||
2565 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
2566 | } |
2567 | ||
2568 | static void | |
839ca903 | 2569 | nv50_dac_enable(struct drm_encoder *encoder) |
8eaa9669 | 2570 | { |
e225f446 | 2571 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
2572 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2573 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
839ca903 | 2574 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
97b19b5c | 2575 | u32 *push; |
8eaa9669 | 2576 | |
97b19b5c | 2577 | push = evo_wait(mast, 8); |
8eaa9669 | 2578 | if (push) { |
648d4dfd | 2579 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
2580 | u32 syncs = 0x00000000; |
2581 | ||
2582 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2583 | syncs |= 0x00000001; | |
2584 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2585 | syncs |= 0x00000002; | |
2586 | ||
2587 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
2588 | evo_data(push, 1 << nv_crtc->index); | |
2589 | evo_data(push, syncs); | |
2590 | } else { | |
2591 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
2592 | u32 syncs = 0x00000001; | |
2593 | ||
2594 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2595 | syncs |= 0x00000008; | |
2596 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2597 | syncs |= 0x00000010; | |
2598 | ||
2599 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2600 | magic |= 0x00000001; | |
2601 | ||
2602 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
2603 | evo_data(push, syncs); | |
2604 | evo_data(push, magic); | |
2605 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
2606 | evo_data(push, 1 << nv_crtc->index); | |
2607 | } | |
2608 | ||
2609 | evo_kick(push, mast); | |
8eaa9669 BS |
2610 | } |
2611 | ||
2612 | nv_encoder->crtc = encoder->crtc; | |
2613 | } | |
2614 | ||
b6d8e7ec | 2615 | static enum drm_connector_status |
e225f446 | 2616 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 2617 | { |
c4abd317 | 2618 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 2619 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
c4abd317 BS |
2620 | struct { |
2621 | struct nv50_disp_mthd_v1 base; | |
2622 | struct nv50_disp_dac_load_v0 load; | |
2623 | } args = { | |
2624 | .base.version = 1, | |
2625 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, | |
2626 | .base.hasht = nv_encoder->dcb->hasht, | |
2627 | .base.hashm = nv_encoder->dcb->hashm, | |
2628 | }; | |
2629 | int ret; | |
2630 | ||
2631 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; | |
2632 | if (args.load.data == 0) | |
2633 | args.load.data = 340; | |
b681993f | 2634 | |
c4abd317 BS |
2635 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
2636 | if (ret || !args.load.load) | |
35b21d39 | 2637 | return connector_status_disconnected; |
b681993f | 2638 | |
35b21d39 | 2639 | return connector_status_connected; |
b6d8e7ec BS |
2640 | } |
2641 | ||
f20c665c BS |
2642 | static const struct drm_encoder_helper_funcs |
2643 | nv50_dac_help = { | |
e225f446 | 2644 | .dpms = nv50_dac_dpms, |
839ca903 BS |
2645 | .atomic_check = nv50_outp_atomic_check, |
2646 | .enable = nv50_dac_enable, | |
2647 | .disable = nv50_dac_disable, | |
e225f446 | 2648 | .detect = nv50_dac_detect |
8eaa9669 BS |
2649 | }; |
2650 | ||
f20c665c BS |
2651 | static void |
2652 | nv50_dac_destroy(struct drm_encoder *encoder) | |
2653 | { | |
2654 | drm_encoder_cleanup(encoder); | |
2655 | kfree(encoder); | |
2656 | } | |
2657 | ||
2658 | static const struct drm_encoder_funcs | |
2659 | nv50_dac_func = { | |
e225f446 | 2660 | .destroy = nv50_dac_destroy, |
8eaa9669 BS |
2661 | }; |
2662 | ||
2663 | static int | |
e225f446 | 2664 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 2665 | { |
5ed50209 | 2666 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 2667 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
2aa5eac5 | 2668 | struct nvkm_i2c_bus *bus; |
8eaa9669 BS |
2669 | struct nouveau_encoder *nv_encoder; |
2670 | struct drm_encoder *encoder; | |
5ed50209 | 2671 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
2672 | |
2673 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2674 | if (!nv_encoder) | |
2675 | return -ENOMEM; | |
2676 | nv_encoder->dcb = dcbe; | |
2677 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2aa5eac5 BS |
2678 | |
2679 | bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
2680 | if (bus) | |
2681 | nv_encoder->i2c = &bus->i2c; | |
8eaa9669 BS |
2682 | |
2683 | encoder = to_drm_encoder(nv_encoder); | |
2684 | encoder->possible_crtcs = dcbe->heads; | |
2685 | encoder->possible_clones = 0; | |
5a223dac BS |
2686 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, |
2687 | "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 2688 | drm_encoder_helper_add(encoder, &nv50_dac_help); |
8eaa9669 BS |
2689 | |
2690 | drm_mode_connector_attach_encoder(connector, encoder); | |
2691 | return 0; | |
2692 | } | |
26f6d88b | 2693 | |
78951d22 BS |
2694 | /****************************************************************************** |
2695 | * Audio | |
2696 | *****************************************************************************/ | |
2697 | static void | |
f20c665c BS |
2698 | nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
2699 | { | |
2700 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2701 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
2702 | struct { | |
2703 | struct nv50_disp_mthd_v1 base; | |
2704 | struct nv50_disp_sor_hda_eld_v0 eld; | |
2705 | } args = { | |
2706 | .base.version = 1, | |
2707 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
2708 | .base.hasht = nv_encoder->dcb->hasht, | |
2709 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2710 | (0x0100 << nv_crtc->index), | |
2711 | }; | |
2712 | ||
2713 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
2714 | } | |
2715 | ||
2716 | static void | |
2717 | nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
78951d22 BS |
2718 | { |
2719 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cc2a9071 | 2720 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
78951d22 | 2721 | struct nouveau_connector *nv_connector; |
e225f446 | 2722 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
d889c524 BS |
2723 | struct __packed { |
2724 | struct { | |
2725 | struct nv50_disp_mthd_v1 mthd; | |
2726 | struct nv50_disp_sor_hda_eld_v0 eld; | |
2727 | } base; | |
120b0c39 BS |
2728 | u8 data[sizeof(nv_connector->base.eld)]; |
2729 | } args = { | |
d889c524 BS |
2730 | .base.mthd.version = 1, |
2731 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
2732 | .base.mthd.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
2733 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
2734 | (0x0100 << nv_crtc->index), | |
120b0c39 | 2735 | }; |
78951d22 BS |
2736 | |
2737 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2738 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
2739 | return; | |
2740 | ||
78951d22 | 2741 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
120b0c39 | 2742 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
78951d22 | 2743 | |
938fd8aa JN |
2744 | nvif_mthd(disp->disp, 0, &args, |
2745 | sizeof(args.base) + drm_eld_size(args.data)); | |
78951d22 BS |
2746 | } |
2747 | ||
f20c665c BS |
2748 | /****************************************************************************** |
2749 | * HDMI | |
2750 | *****************************************************************************/ | |
78951d22 | 2751 | static void |
f20c665c | 2752 | nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 BS |
2753 | { |
2754 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 2755 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
120b0c39 BS |
2756 | struct { |
2757 | struct nv50_disp_mthd_v1 base; | |
f20c665c | 2758 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; |
120b0c39 BS |
2759 | } args = { |
2760 | .base.version = 1, | |
f20c665c BS |
2761 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, |
2762 | .base.hasht = nv_encoder->dcb->hasht, | |
2763 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2764 | (0x0100 << nv_crtc->index), | |
120b0c39 | 2765 | }; |
78951d22 | 2766 | |
120b0c39 | 2767 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
2768 | } |
2769 | ||
78951d22 | 2770 | static void |
f20c665c | 2771 | nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 2772 | { |
64d9cc04 BS |
2773 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2774 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
e225f446 | 2775 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
2776 | struct { |
2777 | struct nv50_disp_mthd_v1 base; | |
2778 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
2779 | } args = { | |
2780 | .base.version = 1, | |
2781 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
2782 | .base.hasht = nv_encoder->dcb->hasht, | |
2783 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
2784 | (0x0100 << nv_crtc->index), | |
2785 | .pwr.state = 1, | |
2786 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ | |
2787 | }; | |
2788 | struct nouveau_connector *nv_connector; | |
64d9cc04 BS |
2789 | u32 max_ac_packet; |
2790 | ||
2791 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2792 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
2793 | return; | |
2794 | ||
2795 | max_ac_packet = mode->htotal - mode->hdisplay; | |
e00f2235 | 2796 | max_ac_packet -= args.pwr.rekey; |
64d9cc04 | 2797 | max_ac_packet -= 18; /* constant from tegra */ |
e00f2235 | 2798 | args.pwr.max_ac_packet = max_ac_packet / 32; |
091e40cd | 2799 | |
e00f2235 | 2800 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
f20c665c | 2801 | nv50_audio_enable(encoder, mode); |
78951d22 BS |
2802 | } |
2803 | ||
52aa30f2 BS |
2804 | /****************************************************************************** |
2805 | * MST | |
2806 | *****************************************************************************/ | |
2807 | struct nv50_mstm { | |
2808 | struct nouveau_encoder *outp; | |
2809 | ||
2810 | struct drm_dp_mst_topology_mgr mgr; | |
2811 | }; | |
2812 | ||
2813 | static int | |
2814 | nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) | |
2815 | { | |
2816 | struct nouveau_encoder *outp = mstm->outp; | |
2817 | struct { | |
2818 | struct nv50_disp_mthd_v1 base; | |
2819 | struct nv50_disp_sor_dp_mst_link_v0 mst; | |
2820 | } args = { | |
2821 | .base.version = 1, | |
2822 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, | |
2823 | .base.hasht = outp->dcb->hasht, | |
2824 | .base.hashm = outp->dcb->hashm, | |
2825 | .mst.state = state, | |
2826 | }; | |
2827 | struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); | |
2828 | struct nvif_object *disp = &drm->display->disp; | |
2829 | int ret; | |
2830 | ||
2831 | if (dpcd >= 0x12) { | |
2832 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd); | |
2833 | if (ret < 0) | |
2834 | return ret; | |
2835 | ||
2836 | dpcd &= ~DP_MST_EN; | |
2837 | if (state) | |
2838 | dpcd |= DP_MST_EN; | |
2839 | ||
2840 | ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd); | |
2841 | if (ret < 0) | |
2842 | return ret; | |
2843 | } | |
2844 | ||
2845 | return nvif_mthd(disp, 0, &args, sizeof(args)); | |
2846 | } | |
2847 | ||
2848 | int | |
2849 | nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) | |
2850 | { | |
2851 | int ret, state = 0; | |
2852 | ||
2853 | if (!mstm) | |
2854 | return 0; | |
2855 | ||
2856 | if (dpcd[0] >= 0x12 && allow) { | |
2857 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]); | |
2858 | if (ret < 0) | |
2859 | return ret; | |
2860 | ||
2861 | state = dpcd[1] & DP_MST_CAP; | |
2862 | } | |
2863 | ||
2864 | ret = nv50_mstm_enable(mstm, dpcd[0], state); | |
2865 | if (ret) | |
2866 | return ret; | |
2867 | ||
2868 | ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state); | |
2869 | if (ret) | |
2870 | return nv50_mstm_enable(mstm, dpcd[0], 0); | |
2871 | ||
2872 | return mstm->mgr.mst_state; | |
2873 | } | |
2874 | ||
2875 | static void | |
2876 | nv50_mstm_del(struct nv50_mstm **pmstm) | |
2877 | { | |
2878 | struct nv50_mstm *mstm = *pmstm; | |
2879 | if (mstm) { | |
2880 | kfree(*pmstm); | |
2881 | *pmstm = NULL; | |
2882 | } | |
2883 | } | |
2884 | ||
2885 | static int | |
2886 | nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, | |
2887 | int conn_base_id, struct nv50_mstm **pmstm) | |
2888 | { | |
2889 | const int max_payloads = hweight8(outp->dcb->heads); | |
2890 | struct drm_device *dev = outp->base.base.dev; | |
2891 | struct nv50_mstm *mstm; | |
2892 | int ret; | |
2893 | ||
2894 | if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) | |
2895 | return -ENOMEM; | |
2896 | mstm->outp = outp; | |
2897 | ||
2898 | ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev->dev, aux, aux_max, | |
2899 | max_payloads, conn_base_id); | |
2900 | if (ret) | |
2901 | return ret; | |
2902 | ||
2903 | return 0; | |
2904 | } | |
2905 | ||
26f6d88b BS |
2906 | /****************************************************************************** |
2907 | * SOR | |
2908 | *****************************************************************************/ | |
83fc083c | 2909 | static void |
e225f446 | 2910 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
2911 | { |
2912 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
d55b4af9 BS |
2913 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
2914 | struct { | |
2915 | struct nv50_disp_mthd_v1 base; | |
2916 | struct nv50_disp_sor_pwr_v0 pwr; | |
2917 | } args = { | |
2918 | .base.version = 1, | |
2919 | .base.method = NV50_DISP_MTHD_V1_SOR_PWR, | |
2920 | .base.hasht = nv_encoder->dcb->hasht, | |
2921 | .base.hashm = nv_encoder->dcb->hashm, | |
2922 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
2923 | }; | |
83fc083c | 2924 | |
8896ceef | 2925 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
83fc083c BS |
2926 | } |
2927 | ||
4cbb0f8d | 2928 | static void |
e84a35a8 | 2929 | nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) |
4cbb0f8d | 2930 | { |
e84a35a8 BS |
2931 | struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); |
2932 | u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; | |
2933 | if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { | |
648d4dfd | 2934 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
e84a35a8 BS |
2935 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
2936 | evo_data(push, (nv_encoder->ctrl = temp)); | |
2937 | } else { | |
2938 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); | |
2939 | evo_data(push, (nv_encoder->ctrl = temp)); | |
4cbb0f8d | 2940 | } |
e84a35a8 | 2941 | evo_kick(push, mast); |
4cbb0f8d | 2942 | } |
e84a35a8 BS |
2943 | } |
2944 | ||
2945 | static void | |
839ca903 | 2946 | nv50_sor_disable(struct drm_encoder *encoder) |
e84a35a8 BS |
2947 | { |
2948 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2949 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
419e8dc0 | 2950 | |
419e8dc0 | 2951 | nv_encoder->crtc = NULL; |
e84a35a8 BS |
2952 | |
2953 | if (nv_crtc) { | |
839ca903 BS |
2954 | struct nvkm_i2c_aux *aux = nv_encoder->aux; |
2955 | u8 pwr; | |
2956 | ||
2957 | if (aux) { | |
2958 | int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); | |
2959 | if (ret == 0) { | |
2960 | pwr &= ~DP_SET_POWER_MASK; | |
2961 | pwr |= DP_SET_POWER_D3; | |
2962 | nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); | |
2963 | } | |
2964 | } | |
2965 | ||
e84a35a8 | 2966 | nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0); |
f20c665c BS |
2967 | nv50_audio_disable(encoder, nv_crtc); |
2968 | nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); | |
e84a35a8 | 2969 | } |
4cbb0f8d BS |
2970 | } |
2971 | ||
83fc083c | 2972 | static void |
839ca903 | 2973 | nv50_sor_enable(struct drm_encoder *encoder) |
83fc083c | 2974 | { |
a3761fa2 BS |
2975 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
2976 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
839ca903 | 2977 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
a3761fa2 BS |
2978 | struct { |
2979 | struct nv50_disp_mthd_v1 base; | |
2980 | struct nv50_disp_sor_lvds_script_v0 lvds; | |
2981 | } lvds = { | |
2982 | .base.version = 1, | |
2983 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, | |
2984 | .base.hasht = nv_encoder->dcb->hasht, | |
2985 | .base.hashm = nv_encoder->dcb->hashm, | |
2986 | }; | |
e225f446 BS |
2987 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
2988 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 2989 | struct drm_device *dev = encoder->dev; |
77145f1c | 2990 | struct nouveau_drm *drm = nouveau_drm(dev); |
3b6d83d1 | 2991 | struct nouveau_connector *nv_connector; |
77145f1c | 2992 | struct nvbios *bios = &drm->vbios; |
a3761fa2 | 2993 | u32 mask, ctrl; |
419e8dc0 BS |
2994 | u8 owner = 1 << nv_crtc->index; |
2995 | u8 proto = 0xf; | |
2996 | u8 depth = 0x0; | |
83fc083c | 2997 | |
3b6d83d1 | 2998 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
e84a35a8 BS |
2999 | nv_encoder->crtc = encoder->crtc; |
3000 | ||
3b6d83d1 | 3001 | switch (nv_encoder->dcb->type) { |
cb75d97e | 3002 | case DCB_OUTPUT_TMDS: |
3b6d83d1 | 3003 | if (nv_encoder->dcb->sorconf.link & 1) { |
16ef53a9 HM |
3004 | proto = 0x1; |
3005 | /* Only enable dual-link if: | |
3006 | * - Need to (i.e. rate > 165MHz) | |
3007 | * - DCB says we can | |
3008 | * - Not an HDMI monitor, since there's no dual-link | |
3009 | * on HDMI. | |
3010 | */ | |
3011 | if (mode->clock >= 165000 && | |
3012 | nv_encoder->dcb->duallink_possible && | |
3013 | !drm_detect_hdmi_monitor(nv_connector->edid)) | |
3014 | proto |= 0x4; | |
3b6d83d1 | 3015 | } else { |
419e8dc0 | 3016 | proto = 0x2; |
3b6d83d1 BS |
3017 | } |
3018 | ||
f20c665c | 3019 | nv50_hdmi_enable(&nv_encoder->base.base, mode); |
3b6d83d1 | 3020 | break; |
cb75d97e | 3021 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
3022 | proto = 0x0; |
3023 | ||
3b6d83d1 BS |
3024 | if (bios->fp_no_ddc) { |
3025 | if (bios->fp.dual_link) | |
a3761fa2 | 3026 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 3027 | if (bios->fp.if_is_24bit) |
a3761fa2 | 3028 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 3029 | } else { |
befb51e9 | 3030 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 3031 | if (((u8 *)nv_connector->edid)[121] == 2) |
a3761fa2 | 3032 | lvds.lvds.script |= 0x0100; |
3b6d83d1 BS |
3033 | } else |
3034 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
a3761fa2 | 3035 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 3036 | } |
83fc083c | 3037 | |
a3761fa2 | 3038 | if (lvds.lvds.script & 0x0100) { |
3b6d83d1 | 3039 | if (bios->fp.strapless_is_24bit & 2) |
a3761fa2 | 3040 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
3041 | } else { |
3042 | if (bios->fp.strapless_is_24bit & 1) | |
a3761fa2 | 3043 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
3044 | } |
3045 | ||
3046 | if (nv_connector->base.display_info.bpc == 8) | |
a3761fa2 | 3047 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 3048 | } |
4a230fa6 | 3049 | |
a3761fa2 | 3050 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
3b6d83d1 | 3051 | break; |
cb75d97e | 3052 | case DCB_OUTPUT_DP: |
f20c665c | 3053 | if (nv_connector->base.display_info.bpc == 6) |
419e8dc0 | 3054 | depth = 0x2; |
f20c665c BS |
3055 | else |
3056 | if (nv_connector->base.display_info.bpc == 8) | |
419e8dc0 | 3057 | depth = 0x5; |
f20c665c | 3058 | else |
bf2c886a | 3059 | depth = 0x6; |
6e83fda2 BS |
3060 | |
3061 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 3062 | proto = 0x8; |
6e83fda2 | 3063 | else |
419e8dc0 | 3064 | proto = 0x9; |
f20c665c BS |
3065 | |
3066 | nv50_audio_enable(encoder, mode); | |
6e83fda2 | 3067 | break; |
3b6d83d1 BS |
3068 | default: |
3069 | BUG_ON(1); | |
3070 | break; | |
3071 | } | |
ff8ff503 | 3072 | |
648d4dfd | 3073 | if (nv50_vers(mast) >= GF110_DISP) { |
e84a35a8 BS |
3074 | u32 *push = evo_wait(mast, 3); |
3075 | if (push) { | |
419e8dc0 BS |
3076 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
3077 | u32 syncs = 0x00000001; | |
3078 | ||
3079 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3080 | syncs |= 0x00000008; | |
3081 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3082 | syncs |= 0x00000010; | |
3083 | ||
3084 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
3085 | magic |= 0x00000001; | |
3086 | ||
3087 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
3088 | evo_data(push, syncs | (depth << 6)); | |
3089 | evo_data(push, magic); | |
e84a35a8 | 3090 | evo_kick(push, mast); |
419e8dc0 BS |
3091 | } |
3092 | ||
e84a35a8 BS |
3093 | ctrl = proto << 8; |
3094 | mask = 0x00000f00; | |
3095 | } else { | |
3096 | ctrl = (depth << 16) | (proto << 8); | |
3097 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3098 | ctrl |= 0x00001000; | |
3099 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3100 | ctrl |= 0x00002000; | |
3101 | mask = 0x000f3f00; | |
83fc083c BS |
3102 | } |
3103 | ||
e84a35a8 | 3104 | nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner); |
83fc083c BS |
3105 | } |
3106 | ||
f20c665c BS |
3107 | static const struct drm_encoder_helper_funcs |
3108 | nv50_sor_help = { | |
3109 | .dpms = nv50_sor_dpms, | |
839ca903 BS |
3110 | .atomic_check = nv50_outp_atomic_check, |
3111 | .enable = nv50_sor_enable, | |
3112 | .disable = nv50_sor_disable, | |
f20c665c BS |
3113 | }; |
3114 | ||
83fc083c | 3115 | static void |
e225f446 | 3116 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c | 3117 | { |
52aa30f2 BS |
3118 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
3119 | nv50_mstm_del(&nv_encoder->dp.mstm); | |
83fc083c BS |
3120 | drm_encoder_cleanup(encoder); |
3121 | kfree(encoder); | |
3122 | } | |
3123 | ||
f20c665c BS |
3124 | static const struct drm_encoder_funcs |
3125 | nv50_sor_func = { | |
e225f446 | 3126 | .destroy = nv50_sor_destroy, |
83fc083c BS |
3127 | }; |
3128 | ||
3129 | static int | |
e225f446 | 3130 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 3131 | { |
52aa30f2 | 3132 | struct nouveau_connector *nv_connector = nouveau_connector(connector); |
5ed50209 | 3133 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 3134 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
83fc083c BS |
3135 | struct nouveau_encoder *nv_encoder; |
3136 | struct drm_encoder *encoder; | |
52aa30f2 | 3137 | int type, ret; |
5ed50209 BS |
3138 | |
3139 | switch (dcbe->type) { | |
3140 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
3141 | case DCB_OUTPUT_TMDS: | |
3142 | case DCB_OUTPUT_DP: | |
3143 | default: | |
3144 | type = DRM_MODE_ENCODER_TMDS; | |
3145 | break; | |
3146 | } | |
83fc083c BS |
3147 | |
3148 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
3149 | if (!nv_encoder) | |
3150 | return -ENOMEM; | |
3151 | nv_encoder->dcb = dcbe; | |
3152 | nv_encoder->or = ffs(dcbe->or) - 1; | |
83fc083c | 3153 | |
52aa30f2 BS |
3154 | encoder = to_drm_encoder(nv_encoder); |
3155 | encoder->possible_crtcs = dcbe->heads; | |
3156 | encoder->possible_clones = 0; | |
5a223dac BS |
3157 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, |
3158 | "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 3159 | drm_encoder_helper_add(encoder, &nv50_sor_help); |
52aa30f2 BS |
3160 | |
3161 | drm_mode_connector_attach_encoder(connector, encoder); | |
3162 | ||
2aa5eac5 BS |
3163 | if (dcbe->type == DCB_OUTPUT_DP) { |
3164 | struct nvkm_i2c_aux *aux = | |
3165 | nvkm_i2c_aux_find(i2c, dcbe->i2c_index); | |
3166 | if (aux) { | |
3167 | nv_encoder->i2c = &aux->i2c; | |
3168 | nv_encoder->aux = aux; | |
3169 | } | |
52aa30f2 BS |
3170 | |
3171 | /*TODO: Use DP Info Table to check for support. */ | |
3172 | if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) { | |
3173 | ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, | |
3174 | nv_connector->base.base.id, | |
3175 | &nv_encoder->dp.mstm); | |
3176 | if (ret) | |
3177 | return ret; | |
3178 | } | |
2aa5eac5 BS |
3179 | } else { |
3180 | struct nvkm_i2c_bus *bus = | |
3181 | nvkm_i2c_bus_find(i2c, dcbe->i2c_index); | |
3182 | if (bus) | |
3183 | nv_encoder->i2c = &bus->i2c; | |
3184 | } | |
3185 | ||
83fc083c BS |
3186 | return 0; |
3187 | } | |
26f6d88b | 3188 | |
eb6313ad BS |
3189 | /****************************************************************************** |
3190 | * PIOR | |
3191 | *****************************************************************************/ | |
eb6313ad BS |
3192 | static void |
3193 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
3194 | { | |
3195 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
3196 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
67cb49c4 BS |
3197 | struct { |
3198 | struct nv50_disp_mthd_v1 base; | |
3199 | struct nv50_disp_pior_pwr_v0 pwr; | |
3200 | } args = { | |
3201 | .base.version = 1, | |
3202 | .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, | |
3203 | .base.hasht = nv_encoder->dcb->hasht, | |
3204 | .base.hashm = nv_encoder->dcb->hashm, | |
3205 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
3206 | .pwr.type = nv_encoder->dcb->type, | |
3207 | }; | |
3208 | ||
3209 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
eb6313ad BS |
3210 | } |
3211 | ||
839ca903 BS |
3212 | static int |
3213 | nv50_pior_atomic_check(struct drm_encoder *encoder, | |
3214 | struct drm_crtc_state *crtc_state, | |
3215 | struct drm_connector_state *conn_state) | |
eb6313ad | 3216 | { |
839ca903 BS |
3217 | int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); |
3218 | if (ret) | |
3219 | return ret; | |
3220 | crtc_state->adjusted_mode.clock *= 2; | |
3221 | return 0; | |
eb6313ad BS |
3222 | } |
3223 | ||
3224 | static void | |
839ca903 | 3225 | nv50_pior_disable(struct drm_encoder *encoder) |
eb6313ad | 3226 | { |
f20c665c BS |
3227 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
3228 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
3229 | const int or = nv_encoder->or; | |
3230 | u32 *push; | |
3231 | ||
3232 | if (nv_encoder->crtc) { | |
f20c665c BS |
3233 | push = evo_wait(mast, 4); |
3234 | if (push) { | |
3235 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { | |
3236 | evo_mthd(push, 0x0700 + (or * 0x040), 1); | |
3237 | evo_data(push, 0x00000000); | |
3238 | } | |
3239 | evo_kick(push, mast); | |
3240 | } | |
3241 | } | |
3242 | ||
3243 | nv_encoder->crtc = NULL; | |
eb6313ad BS |
3244 | } |
3245 | ||
3246 | static void | |
839ca903 | 3247 | nv50_pior_enable(struct drm_encoder *encoder) |
eb6313ad BS |
3248 | { |
3249 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
3250 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
3251 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3252 | struct nouveau_connector *nv_connector; | |
839ca903 | 3253 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
eb6313ad BS |
3254 | u8 owner = 1 << nv_crtc->index; |
3255 | u8 proto, depth; | |
3256 | u32 *push; | |
3257 | ||
3258 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
3259 | switch (nv_connector->base.display_info.bpc) { | |
3260 | case 10: depth = 0x6; break; | |
3261 | case 8: depth = 0x5; break; | |
3262 | case 6: depth = 0x2; break; | |
3263 | default: depth = 0x0; break; | |
3264 | } | |
3265 | ||
3266 | switch (nv_encoder->dcb->type) { | |
3267 | case DCB_OUTPUT_TMDS: | |
3268 | case DCB_OUTPUT_DP: | |
3269 | proto = 0x0; | |
3270 | break; | |
3271 | default: | |
3272 | BUG_ON(1); | |
3273 | break; | |
3274 | } | |
3275 | ||
eb6313ad BS |
3276 | push = evo_wait(mast, 8); |
3277 | if (push) { | |
648d4dfd | 3278 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
3279 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
3280 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
3281 | ctrl |= 0x00001000; | |
3282 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
3283 | ctrl |= 0x00002000; | |
3284 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
3285 | evo_data(push, ctrl); | |
3286 | } | |
3287 | ||
3288 | evo_kick(push, mast); | |
3289 | } | |
3290 | ||
3291 | nv_encoder->crtc = encoder->crtc; | |
3292 | } | |
3293 | ||
f20c665c BS |
3294 | static const struct drm_encoder_helper_funcs |
3295 | nv50_pior_help = { | |
eb6313ad | 3296 | .dpms = nv50_pior_dpms, |
839ca903 BS |
3297 | .atomic_check = nv50_pior_atomic_check, |
3298 | .enable = nv50_pior_enable, | |
3299 | .disable = nv50_pior_disable, | |
eb6313ad BS |
3300 | }; |
3301 | ||
f20c665c BS |
3302 | static void |
3303 | nv50_pior_destroy(struct drm_encoder *encoder) | |
3304 | { | |
3305 | drm_encoder_cleanup(encoder); | |
3306 | kfree(encoder); | |
3307 | } | |
3308 | ||
3309 | static const struct drm_encoder_funcs | |
3310 | nv50_pior_func = { | |
eb6313ad BS |
3311 | .destroy = nv50_pior_destroy, |
3312 | }; | |
3313 | ||
3314 | static int | |
3315 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
3316 | { | |
3317 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
be83cd4e | 3318 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
2aa5eac5 BS |
3319 | struct nvkm_i2c_bus *bus = NULL; |
3320 | struct nvkm_i2c_aux *aux = NULL; | |
3321 | struct i2c_adapter *ddc; | |
eb6313ad BS |
3322 | struct nouveau_encoder *nv_encoder; |
3323 | struct drm_encoder *encoder; | |
3324 | int type; | |
3325 | ||
3326 | switch (dcbe->type) { | |
3327 | case DCB_OUTPUT_TMDS: | |
2aa5eac5 BS |
3328 | bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); |
3329 | ddc = bus ? &bus->i2c : NULL; | |
eb6313ad BS |
3330 | type = DRM_MODE_ENCODER_TMDS; |
3331 | break; | |
3332 | case DCB_OUTPUT_DP: | |
2aa5eac5 BS |
3333 | aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); |
3334 | ddc = aux ? &aux->i2c : NULL; | |
eb6313ad BS |
3335 | type = DRM_MODE_ENCODER_TMDS; |
3336 | break; | |
3337 | default: | |
3338 | return -ENODEV; | |
3339 | } | |
3340 | ||
3341 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
3342 | if (!nv_encoder) | |
3343 | return -ENOMEM; | |
3344 | nv_encoder->dcb = dcbe; | |
3345 | nv_encoder->or = ffs(dcbe->or) - 1; | |
3346 | nv_encoder->i2c = ddc; | |
2aa5eac5 | 3347 | nv_encoder->aux = aux; |
eb6313ad BS |
3348 | |
3349 | encoder = to_drm_encoder(nv_encoder); | |
3350 | encoder->possible_crtcs = dcbe->heads; | |
3351 | encoder->possible_clones = 0; | |
5a223dac BS |
3352 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, |
3353 | "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); | |
f20c665c | 3354 | drm_encoder_helper_add(encoder, &nv50_pior_help); |
eb6313ad BS |
3355 | |
3356 | drm_mode_connector_attach_encoder(connector, encoder); | |
3357 | return 0; | |
3358 | } | |
3359 | ||
839ca903 BS |
3360 | /****************************************************************************** |
3361 | * Atomic | |
3362 | *****************************************************************************/ | |
3363 | ||
3364 | static void | |
3365 | nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock) | |
3366 | { | |
3367 | struct nv50_disp *disp = nv50_disp(drm->dev); | |
3368 | struct nv50_dmac *core = &disp->mast.base; | |
3369 | u32 *push; | |
3370 | ||
3371 | NV_ATOMIC(drm, "commit core %08x\n", interlock); | |
3372 | ||
3373 | if ((push = evo_wait(core, 5))) { | |
3374 | evo_mthd(push, 0x0084, 1); | |
3375 | evo_data(push, 0x80000000); | |
3376 | evo_mthd(push, 0x0080, 2); | |
3377 | evo_data(push, interlock); | |
3378 | evo_data(push, 0x00000000); | |
3379 | nouveau_bo_wr32(disp->sync, 0, 0x00000000); | |
3380 | evo_kick(push, core); | |
3381 | if (nvif_msec(&drm->device, 2000ULL, | |
3382 | if (nouveau_bo_rd32(disp->sync, 0)) | |
3383 | break; | |
3384 | usleep_range(1, 2); | |
3385 | ) < 0) | |
3386 | NV_ERROR(drm, "EVO timeout\n"); | |
3387 | } | |
3388 | } | |
3389 | ||
3390 | static void | |
3391 | nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) | |
3392 | { | |
3393 | struct drm_device *dev = state->dev; | |
3394 | struct drm_crtc_state *crtc_state; | |
3395 | struct drm_crtc *crtc; | |
3396 | struct drm_plane_state *plane_state; | |
3397 | struct drm_plane *plane; | |
3398 | struct nouveau_drm *drm = nouveau_drm(dev); | |
3399 | struct nv50_disp *disp = nv50_disp(dev); | |
3400 | struct nv50_atom *atom = nv50_atom(state); | |
3401 | struct nv50_outp_atom *outp, *outt; | |
3402 | u32 interlock_core = 0; | |
3403 | u32 interlock_chan = 0; | |
3404 | int i; | |
3405 | ||
3406 | NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); | |
3407 | drm_atomic_helper_wait_for_fences(dev, state, false); | |
3408 | drm_atomic_helper_wait_for_dependencies(state); | |
3409 | drm_atomic_helper_update_legacy_modeset_state(dev, state); | |
3410 | ||
3411 | if (atom->lock_core) | |
3412 | mutex_lock(&disp->mutex); | |
3413 | ||
3414 | /* Disable head(s). */ | |
3415 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3416 | struct nv50_head_atom *asyh = nv50_head_atom(crtc->state); | |
3417 | struct nv50_head *head = nv50_head(crtc); | |
3418 | ||
3419 | NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, | |
3420 | asyh->clr.mask, asyh->set.mask); | |
3421 | ||
3422 | if (asyh->clr.mask) { | |
3423 | nv50_head_flush_clr(head, asyh, atom->flush_disable); | |
3424 | interlock_core |= 1; | |
3425 | } | |
3426 | } | |
3427 | ||
3428 | /* Disable plane(s). */ | |
3429 | for_each_plane_in_state(state, plane, plane_state, i) { | |
3430 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); | |
3431 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3432 | ||
3433 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, | |
3434 | asyw->clr.mask, asyw->set.mask); | |
3435 | if (!asyw->clr.mask) | |
3436 | continue; | |
3437 | ||
3438 | interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core, | |
3439 | atom->flush_disable, | |
3440 | asyw); | |
3441 | } | |
3442 | ||
3443 | /* Disable output path(s). */ | |
3444 | list_for_each_entry(outp, &atom->outp, head) { | |
3445 | const struct drm_encoder_helper_funcs *help; | |
3446 | struct drm_encoder *encoder; | |
3447 | ||
3448 | encoder = outp->encoder; | |
3449 | help = encoder->helper_private; | |
3450 | ||
3451 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, | |
3452 | outp->clr.mask, outp->set.mask); | |
3453 | ||
3454 | if (outp->clr.mask) { | |
3455 | help->disable(encoder); | |
3456 | interlock_core |= 1; | |
3457 | if (outp->flush_disable) { | |
3458 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
3459 | interlock_core = 0; | |
3460 | interlock_chan = 0; | |
3461 | } | |
3462 | } | |
3463 | } | |
3464 | ||
3465 | /* Flush disable. */ | |
3466 | if (interlock_core) { | |
3467 | if (atom->flush_disable) { | |
3468 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
3469 | interlock_core = 0; | |
3470 | interlock_chan = 0; | |
3471 | } | |
3472 | } | |
3473 | ||
3474 | /* Update output path(s). */ | |
3475 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { | |
3476 | const struct drm_encoder_helper_funcs *help; | |
3477 | struct drm_encoder *encoder; | |
3478 | ||
3479 | encoder = outp->encoder; | |
3480 | help = encoder->helper_private; | |
3481 | ||
3482 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, | |
3483 | outp->set.mask, outp->clr.mask); | |
3484 | ||
3485 | if (outp->set.mask) { | |
3486 | help->enable(encoder); | |
3487 | interlock_core = 1; | |
3488 | } | |
3489 | ||
3490 | list_del(&outp->head); | |
3491 | kfree(outp); | |
3492 | } | |
3493 | ||
3494 | /* Update head(s). */ | |
3495 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3496 | struct nv50_head_atom *asyh = nv50_head_atom(crtc->state); | |
3497 | struct nv50_head *head = nv50_head(crtc); | |
3498 | ||
3499 | NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, | |
3500 | asyh->set.mask, asyh->clr.mask); | |
3501 | ||
3502 | if (asyh->set.mask) { | |
3503 | nv50_head_flush_set(head, asyh); | |
3504 | interlock_core = 1; | |
3505 | } | |
3506 | } | |
3507 | ||
3508 | /* Update plane(s). */ | |
3509 | for_each_plane_in_state(state, plane, plane_state, i) { | |
3510 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); | |
3511 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3512 | ||
3513 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, | |
3514 | asyw->set.mask, asyw->clr.mask); | |
3515 | if ( !asyw->set.mask && | |
3516 | (!asyw->clr.mask || atom->flush_disable)) | |
3517 | continue; | |
3518 | ||
3519 | interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw); | |
3520 | } | |
3521 | ||
3522 | /* Flush update. */ | |
3523 | if (interlock_core) { | |
3524 | if (!interlock_chan && atom->state.legacy_cursor_update) { | |
3525 | u32 *push = evo_wait(&disp->mast, 2); | |
3526 | if (push) { | |
3527 | evo_mthd(push, 0x0080, 1); | |
3528 | evo_data(push, 0x00000000); | |
3529 | evo_kick(push, &disp->mast); | |
3530 | } | |
3531 | } else { | |
3532 | nv50_disp_atomic_commit_core(drm, interlock_chan); | |
3533 | } | |
3534 | } | |
3535 | ||
3536 | if (atom->lock_core) | |
3537 | mutex_unlock(&disp->mutex); | |
3538 | ||
3539 | /* Wait for HW to signal completion. */ | |
3540 | for_each_plane_in_state(state, plane, plane_state, i) { | |
3541 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); | |
3542 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3543 | int ret = nv50_wndw_wait_armed(wndw, asyw); | |
3544 | if (ret) | |
3545 | NV_ERROR(drm, "%s: timeout\n", plane->name); | |
3546 | } | |
3547 | ||
3548 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3549 | if (crtc->state->event) { | |
3550 | unsigned long flags; | |
3551 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
3552 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
3553 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
3554 | crtc->state->event = NULL; | |
3555 | } | |
3556 | } | |
3557 | ||
3558 | drm_atomic_helper_commit_hw_done(state); | |
3559 | drm_atomic_helper_cleanup_planes(dev, state); | |
3560 | drm_atomic_helper_commit_cleanup_done(state); | |
3561 | drm_atomic_state_put(state); | |
3562 | } | |
3563 | ||
3564 | static void | |
3565 | nv50_disp_atomic_commit_work(struct work_struct *work) | |
3566 | { | |
3567 | struct drm_atomic_state *state = | |
3568 | container_of(work, typeof(*state), commit_work); | |
3569 | nv50_disp_atomic_commit_tail(state); | |
3570 | } | |
3571 | ||
3572 | static int | |
3573 | nv50_disp_atomic_commit(struct drm_device *dev, | |
3574 | struct drm_atomic_state *state, bool nonblock) | |
3575 | { | |
3576 | struct nouveau_drm *drm = nouveau_drm(dev); | |
3577 | struct nv50_disp *disp = nv50_disp(dev); | |
3578 | struct drm_plane_state *plane_state; | |
3579 | struct drm_plane *plane; | |
3580 | struct drm_crtc *crtc; | |
3581 | bool active = false; | |
3582 | int ret, i; | |
3583 | ||
3584 | ret = pm_runtime_get_sync(dev->dev); | |
3585 | if (ret < 0 && ret != -EACCES) | |
3586 | return ret; | |
3587 | ||
3588 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
3589 | if (ret) | |
3590 | goto done; | |
3591 | ||
3592 | INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); | |
3593 | ||
3594 | ret = drm_atomic_helper_prepare_planes(dev, state); | |
3595 | if (ret) | |
3596 | goto done; | |
3597 | ||
3598 | if (!nonblock) { | |
3599 | ret = drm_atomic_helper_wait_for_fences(dev, state, true); | |
3600 | if (ret) | |
3601 | goto done; | |
3602 | } | |
3603 | ||
3604 | for_each_plane_in_state(state, plane, plane_state, i) { | |
3605 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state); | |
3606 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3607 | if (asyw->set.image) { | |
3608 | asyw->ntfy.handle = wndw->dmac->sync.handle; | |
3609 | asyw->ntfy.offset = wndw->ntfy; | |
3610 | asyw->ntfy.awaken = false; | |
3611 | asyw->set.ntfy = true; | |
3612 | nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000); | |
3613 | wndw->ntfy ^= 0x10; | |
3614 | } | |
3615 | } | |
3616 | ||
3617 | drm_atomic_helper_swap_state(state, true); | |
3618 | drm_atomic_state_get(state); | |
3619 | ||
3620 | if (nonblock) | |
3621 | queue_work(system_unbound_wq, &state->commit_work); | |
3622 | else | |
3623 | nv50_disp_atomic_commit_tail(state); | |
3624 | ||
3625 | drm_for_each_crtc(crtc, dev) { | |
3626 | if (crtc->state->enable) { | |
3627 | if (!drm->have_disp_power_ref) { | |
3628 | drm->have_disp_power_ref = true; | |
3629 | return ret; | |
3630 | } | |
3631 | active = true; | |
3632 | break; | |
3633 | } | |
3634 | } | |
3635 | ||
3636 | if (!active && drm->have_disp_power_ref) { | |
3637 | pm_runtime_put_autosuspend(dev->dev); | |
3638 | drm->have_disp_power_ref = false; | |
3639 | } | |
3640 | ||
3641 | done: | |
3642 | pm_runtime_put_autosuspend(dev->dev); | |
3643 | return ret; | |
3644 | } | |
3645 | ||
3646 | static struct nv50_outp_atom * | |
3647 | nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) | |
3648 | { | |
3649 | struct nv50_outp_atom *outp; | |
3650 | ||
3651 | list_for_each_entry(outp, &atom->outp, head) { | |
3652 | if (outp->encoder == encoder) | |
3653 | return outp; | |
3654 | } | |
3655 | ||
3656 | outp = kzalloc(sizeof(*outp), GFP_KERNEL); | |
3657 | if (!outp) | |
3658 | return ERR_PTR(-ENOMEM); | |
3659 | ||
3660 | list_add(&outp->head, &atom->outp); | |
3661 | outp->encoder = encoder; | |
3662 | return outp; | |
3663 | } | |
3664 | ||
3665 | static int | |
3666 | nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, | |
3667 | struct drm_connector *connector) | |
3668 | { | |
3669 | struct drm_encoder *encoder = connector->state->best_encoder; | |
3670 | struct drm_crtc_state *crtc_state; | |
3671 | struct drm_crtc *crtc; | |
3672 | struct nv50_outp_atom *outp; | |
3673 | ||
3674 | if (!(crtc = connector->state->crtc)) | |
3675 | return 0; | |
3676 | ||
3677 | crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc); | |
3678 | if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) { | |
3679 | outp = nv50_disp_outp_atomic_add(atom, encoder); | |
3680 | if (IS_ERR(outp)) | |
3681 | return PTR_ERR(outp); | |
3682 | ||
3683 | if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { | |
3684 | outp->flush_disable = true; | |
3685 | atom->flush_disable = true; | |
3686 | } | |
3687 | outp->clr.ctrl = true; | |
3688 | atom->lock_core = true; | |
3689 | } | |
3690 | ||
3691 | return 0; | |
3692 | } | |
3693 | ||
3694 | static int | |
3695 | nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, | |
3696 | struct drm_connector_state *connector_state) | |
3697 | { | |
3698 | struct drm_encoder *encoder = connector_state->best_encoder; | |
3699 | struct drm_crtc_state *crtc_state; | |
3700 | struct drm_crtc *crtc; | |
3701 | struct nv50_outp_atom *outp; | |
3702 | ||
3703 | if (!(crtc = connector_state->crtc)) | |
3704 | return 0; | |
3705 | ||
3706 | crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc); | |
3707 | if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) { | |
3708 | outp = nv50_disp_outp_atomic_add(atom, encoder); | |
3709 | if (IS_ERR(outp)) | |
3710 | return PTR_ERR(outp); | |
3711 | ||
3712 | outp->set.ctrl = true; | |
3713 | atom->lock_core = true; | |
3714 | } | |
3715 | ||
3716 | return 0; | |
3717 | } | |
3718 | ||
3719 | static int | |
3720 | nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) | |
3721 | { | |
3722 | struct nv50_atom *atom = nv50_atom(state); | |
3723 | struct drm_connector_state *connector_state; | |
3724 | struct drm_connector *connector; | |
3725 | int ret, i; | |
3726 | ||
3727 | ret = drm_atomic_helper_check(dev, state); | |
3728 | if (ret) | |
3729 | return ret; | |
3730 | ||
3731 | for_each_connector_in_state(state, connector, connector_state, i) { | |
3732 | ret = nv50_disp_outp_atomic_check_clr(atom, connector); | |
3733 | if (ret) | |
3734 | return ret; | |
3735 | ||
3736 | ret = nv50_disp_outp_atomic_check_set(atom, connector_state); | |
3737 | if (ret) | |
3738 | return ret; | |
3739 | } | |
3740 | ||
3741 | return 0; | |
3742 | } | |
3743 | ||
3744 | static void | |
3745 | nv50_disp_atomic_state_clear(struct drm_atomic_state *state) | |
3746 | { | |
3747 | struct nv50_atom *atom = nv50_atom(state); | |
3748 | struct nv50_outp_atom *outp, *outt; | |
3749 | ||
3750 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { | |
3751 | list_del(&outp->head); | |
3752 | kfree(outp); | |
3753 | } | |
3754 | ||
3755 | drm_atomic_state_default_clear(state); | |
3756 | } | |
3757 | ||
3758 | static void | |
3759 | nv50_disp_atomic_state_free(struct drm_atomic_state *state) | |
3760 | { | |
3761 | struct nv50_atom *atom = nv50_atom(state); | |
3762 | drm_atomic_state_default_release(&atom->state); | |
3763 | kfree(atom); | |
3764 | } | |
3765 | ||
3766 | static struct drm_atomic_state * | |
3767 | nv50_disp_atomic_state_alloc(struct drm_device *dev) | |
3768 | { | |
3769 | struct nv50_atom *atom; | |
3770 | if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || | |
3771 | drm_atomic_state_init(dev, &atom->state) < 0) { | |
3772 | kfree(atom); | |
3773 | return NULL; | |
3774 | } | |
3775 | INIT_LIST_HEAD(&atom->outp); | |
3776 | return &atom->state; | |
3777 | } | |
3778 | ||
3779 | static const struct drm_mode_config_funcs | |
3780 | nv50_disp_func = { | |
3781 | .fb_create = nouveau_user_framebuffer_create, | |
3782 | .output_poll_changed = nouveau_fbcon_output_poll_changed, | |
3783 | .atomic_check = nv50_disp_atomic_check, | |
3784 | .atomic_commit = nv50_disp_atomic_commit, | |
3785 | .atomic_state_alloc = nv50_disp_atomic_state_alloc, | |
3786 | .atomic_state_clear = nv50_disp_atomic_state_clear, | |
3787 | .atomic_state_free = nv50_disp_atomic_state_free, | |
3788 | }; | |
3789 | ||
26f6d88b BS |
3790 | /****************************************************************************** |
3791 | * Init | |
3792 | *****************************************************************************/ | |
ab0af559 | 3793 | |
2a44e499 | 3794 | void |
e225f446 | 3795 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 3796 | { |
973f10c2 BS |
3797 | struct drm_plane *plane; |
3798 | ||
3799 | drm_for_each_plane(plane, dev) { | |
3800 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3801 | if (plane->funcs != &nv50_wndw) | |
3802 | continue; | |
3803 | nv50_wndw_fini(wndw); | |
3804 | } | |
26f6d88b BS |
3805 | } |
3806 | ||
3807 | int | |
e225f446 | 3808 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 3809 | { |
354d3508 | 3810 | struct drm_encoder *encoder; |
973f10c2 | 3811 | struct drm_plane *plane; |
9f9bdaaf BS |
3812 | struct drm_crtc *crtc; |
3813 | u32 *push; | |
3814 | ||
3815 | push = evo_wait(nv50_mast(dev), 32); | |
3816 | if (!push) | |
3817 | return -EBUSY; | |
3818 | ||
9f9bdaaf | 3819 | evo_mthd(push, 0x0088, 1); |
f45f55c4 | 3820 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
9f9bdaaf | 3821 | evo_kick(push, nv50_mast(dev)); |
973f10c2 | 3822 | |
354d3508 BS |
3823 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
3824 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { | |
3825 | const struct drm_encoder_helper_funcs *help; | |
3826 | struct nouveau_encoder *nv_encoder; | |
3827 | ||
3828 | nv_encoder = nouveau_encoder(encoder); | |
354d3508 BS |
3829 | help = encoder->helper_private; |
3830 | if (help && help->dpms) | |
3831 | help->dpms(encoder, DRM_MODE_DPMS_ON); | |
354d3508 BS |
3832 | } |
3833 | } | |
3834 | ||
e1ef6b42 | 3835 | drm_for_each_crtc(crtc, dev) { |
9bfdee9a | 3836 | nv50_head_lut_load(crtc); |
e1ef6b42 BS |
3837 | } |
3838 | ||
973f10c2 BS |
3839 | drm_for_each_plane(plane, dev) { |
3840 | struct nv50_wndw *wndw = nv50_wndw(plane); | |
3841 | if (plane->funcs != &nv50_wndw) | |
3842 | continue; | |
3843 | nv50_wndw_init(wndw); | |
3844 | } | |
3845 | ||
9f9bdaaf | 3846 | return 0; |
26f6d88b BS |
3847 | } |
3848 | ||
3849 | void | |
e225f446 | 3850 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 3851 | { |
e225f446 | 3852 | struct nv50_disp *disp = nv50_disp(dev); |
bdb8c212 | 3853 | |
0ad72863 | 3854 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
26f6d88b | 3855 | |
816af2f2 | 3856 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
3857 | if (disp->sync) |
3858 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 3859 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 3860 | |
77145f1c | 3861 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
3862 | kfree(disp); |
3863 | } | |
3864 | ||
839ca903 BS |
3865 | MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); |
3866 | static int nouveau_atomic = 0; | |
3867 | module_param_named(atomic, nouveau_atomic, int, 0400); | |
3868 | ||
26f6d88b | 3869 | int |
e225f446 | 3870 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 3871 | { |
967e7bde | 3872 | struct nvif_device *device = &nouveau_drm(dev)->device; |
77145f1c | 3873 | struct nouveau_drm *drm = nouveau_drm(dev); |
77145f1c | 3874 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 3875 | struct drm_connector *connector, *tmp; |
e225f446 | 3876 | struct nv50_disp *disp; |
cb75d97e | 3877 | struct dcb_output *dcbe; |
7c5f6a87 | 3878 | int crtcs, ret, i; |
26f6d88b BS |
3879 | |
3880 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
3881 | if (!disp) | |
3882 | return -ENOMEM; | |
77145f1c | 3883 | |
839ca903 BS |
3884 | mutex_init(&disp->mutex); |
3885 | ||
77145f1c | 3886 | nouveau_display(dev)->priv = disp; |
e225f446 BS |
3887 | nouveau_display(dev)->dtor = nv50_display_destroy; |
3888 | nouveau_display(dev)->init = nv50_display_init; | |
3889 | nouveau_display(dev)->fini = nv50_display_fini; | |
0ad72863 | 3890 | disp->disp = &nouveau_display(dev)->disp; |
839ca903 BS |
3891 | dev->mode_config.funcs = &nv50_disp_func; |
3892 | if (nouveau_atomic) | |
3893 | dev->driver->driver_features |= DRIVER_ATOMIC; | |
26f6d88b | 3894 | |
b5a794b0 BS |
3895 | /* small shared memory area we use for notifiers and semaphores */ |
3896 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
bb6178b0 | 3897 | 0, 0x0000, NULL, NULL, &disp->sync); |
b5a794b0 | 3898 | if (!ret) { |
547ad072 | 3899 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 3900 | if (!ret) { |
b5a794b0 | 3901 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
3902 | if (ret) |
3903 | nouveau_bo_unpin(disp->sync); | |
3904 | } | |
b5a794b0 BS |
3905 | if (ret) |
3906 | nouveau_bo_ref(NULL, &disp->sync); | |
3907 | } | |
3908 | ||
b5a794b0 BS |
3909 | if (ret) |
3910 | goto out; | |
3911 | ||
3912 | /* allocate master evo channel */ | |
a01ca78c | 3913 | ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset, |
410f3ec6 | 3914 | &disp->mast); |
b5a794b0 BS |
3915 | if (ret) |
3916 | goto out; | |
3917 | ||
438d99e3 | 3918 | /* create crtc objects to represent the hw heads */ |
648d4dfd | 3919 | if (disp->disp->oclass >= GF110_DISP) |
a01ca78c | 3920 | crtcs = nvif_rd32(&device->object, 0x022448); |
63718a07 BS |
3921 | else |
3922 | crtcs = 2; | |
3923 | ||
7c5f6a87 | 3924 | for (i = 0; i < crtcs; i++) { |
9bfdee9a | 3925 | ret = nv50_head_create(dev, i); |
438d99e3 BS |
3926 | if (ret) |
3927 | goto out; | |
3928 | } | |
3929 | ||
83fc083c BS |
3930 | /* create encoder/connector objects based on VBIOS DCB table */ |
3931 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
3932 | connector = nouveau_connector_create(dev, dcbe->connector); | |
3933 | if (IS_ERR(connector)) | |
3934 | continue; | |
3935 | ||
eb6313ad BS |
3936 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
3937 | switch (dcbe->type) { | |
3938 | case DCB_OUTPUT_TMDS: | |
3939 | case DCB_OUTPUT_LVDS: | |
3940 | case DCB_OUTPUT_DP: | |
3941 | ret = nv50_sor_create(connector, dcbe); | |
3942 | break; | |
3943 | case DCB_OUTPUT_ANALOG: | |
3944 | ret = nv50_dac_create(connector, dcbe); | |
3945 | break; | |
3946 | default: | |
3947 | ret = -ENODEV; | |
3948 | break; | |
3949 | } | |
3950 | } else { | |
3951 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
3952 | } |
3953 | ||
eb6313ad BS |
3954 | if (ret) { |
3955 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
3956 | dcbe->location, dcbe->type, | |
3957 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 3958 | ret = 0; |
83fc083c BS |
3959 | } |
3960 | } | |
3961 | ||
3962 | /* cull any connectors we created that don't have an encoder */ | |
3963 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
3964 | if (connector->encoder_ids[0]) | |
3965 | continue; | |
3966 | ||
77145f1c | 3967 | NV_WARN(drm, "%s has no encoders, removing\n", |
8c6c361a | 3968 | connector->name); |
83fc083c BS |
3969 | connector->funcs->destroy(connector); |
3970 | } | |
3971 | ||
26f6d88b BS |
3972 | out: |
3973 | if (ret) | |
e225f446 | 3974 | nv50_display_destroy(dev); |
26f6d88b BS |
3975 | return ret; |
3976 | } |