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Commit | Line | Data |
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56d237d2 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
3cb9ae4f | 29 | #include <drm/drm_plane_helper.h> |
4874322e | 30 | #include <drm/drm_dp_helper.h> |
26f6d88b | 31 | |
fdb751ef BS |
32 | #include <nvif/class.h> |
33 | ||
77145f1c BS |
34 | #include "nouveau_drm.h" |
35 | #include "nouveau_dma.h" | |
36 | #include "nouveau_gem.h" | |
26f6d88b BS |
37 | #include "nouveau_connector.h" |
38 | #include "nouveau_encoder.h" | |
39 | #include "nouveau_crtc.h" | |
f589be88 | 40 | #include "nouveau_fence.h" |
3a89cd02 | 41 | #include "nv50_display.h" |
26f6d88b | 42 | |
8a46438a BS |
43 | #define EVO_DMA_NR 9 |
44 | ||
bdb8c212 | 45 | #define EVO_MASTER (0x00) |
a63a97eb | 46 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
47 | #define EVO_OVLY(c) (0x05 + (c)) |
48 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
49 | #define EVO_CURS(c) (0x0d + (c)) |
50 | ||
816af2f2 BS |
51 | /* offsets in shared sync bo of various structures */ |
52 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
53 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
54 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
55 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
816af2f2 | 56 | |
b5a794b0 BS |
57 | /****************************************************************************** |
58 | * EVO channel | |
59 | *****************************************************************************/ | |
60 | ||
e225f446 | 61 | struct nv50_chan { |
0ad72863 | 62 | struct nvif_object user; |
b5a794b0 BS |
63 | }; |
64 | ||
65 | static int | |
410f3ec6 | 66 | nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
e225f446 | 67 | void *data, u32 size, struct nv50_chan *chan) |
b5a794b0 | 68 | { |
6af5289e BS |
69 | const u32 handle = (oclass[0] << 16) | head; |
70 | u32 sclass[8]; | |
71 | int ret, i; | |
72 | ||
73 | ret = nvif_object_sclass(disp, sclass, ARRAY_SIZE(sclass)); | |
74 | WARN_ON(ret > ARRAY_SIZE(sclass)); | |
75 | if (ret < 0) | |
76 | return ret; | |
77 | ||
410f3ec6 | 78 | while (oclass[0]) { |
6af5289e BS |
79 | for (i = 0; i < ARRAY_SIZE(sclass); i++) { |
80 | if (sclass[i] == oclass[0]) { | |
81 | ret = nvif_object_init(disp, NULL, handle, | |
82 | oclass[0], data, size, | |
83 | &chan->user); | |
84 | if (ret == 0) | |
85 | nvif_object_map(&chan->user); | |
86 | return ret; | |
87 | } | |
b76f1529 | 88 | } |
6af5289e | 89 | oclass++; |
410f3ec6 | 90 | } |
6af5289e | 91 | |
410f3ec6 | 92 | return -ENOSYS; |
b5a794b0 BS |
93 | } |
94 | ||
95 | static void | |
0ad72863 | 96 | nv50_chan_destroy(struct nv50_chan *chan) |
b5a794b0 | 97 | { |
0ad72863 | 98 | nvif_object_fini(&chan->user); |
b5a794b0 BS |
99 | } |
100 | ||
101 | /****************************************************************************** | |
102 | * PIO EVO channel | |
103 | *****************************************************************************/ | |
104 | ||
e225f446 BS |
105 | struct nv50_pioc { |
106 | struct nv50_chan base; | |
b5a794b0 BS |
107 | }; |
108 | ||
109 | static void | |
0ad72863 | 110 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
b5a794b0 | 111 | { |
0ad72863 | 112 | nv50_chan_destroy(&pioc->base); |
b5a794b0 BS |
113 | } |
114 | ||
115 | static int | |
410f3ec6 | 116 | nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
e225f446 | 117 | void *data, u32 size, struct nv50_pioc *pioc) |
b5a794b0 | 118 | { |
410f3ec6 BS |
119 | return nv50_chan_create(disp, oclass, head, data, size, &pioc->base); |
120 | } | |
121 | ||
122 | /****************************************************************************** | |
123 | * Cursor Immediate | |
124 | *****************************************************************************/ | |
125 | ||
126 | struct nv50_curs { | |
127 | struct nv50_pioc base; | |
128 | }; | |
129 | ||
130 | static int | |
131 | nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs) | |
132 | { | |
648d4dfd | 133 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
134 | .head = head, |
135 | }; | |
136 | static const u32 oclass[] = { | |
648d4dfd BS |
137 | GK104_DISP_CURSOR, |
138 | GF110_DISP_CURSOR, | |
139 | GT214_DISP_CURSOR, | |
140 | G82_DISP_CURSOR, | |
141 | NV50_DISP_CURSOR, | |
410f3ec6 BS |
142 | 0 |
143 | }; | |
144 | ||
145 | return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), | |
146 | &curs->base); | |
147 | } | |
148 | ||
149 | /****************************************************************************** | |
150 | * Overlay Immediate | |
151 | *****************************************************************************/ | |
152 | ||
153 | struct nv50_oimm { | |
154 | struct nv50_pioc base; | |
155 | }; | |
156 | ||
157 | static int | |
158 | nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm) | |
159 | { | |
648d4dfd | 160 | struct nv50_disp_cursor_v0 args = { |
410f3ec6 BS |
161 | .head = head, |
162 | }; | |
163 | static const u32 oclass[] = { | |
648d4dfd BS |
164 | GK104_DISP_OVERLAY, |
165 | GF110_DISP_OVERLAY, | |
166 | GT214_DISP_OVERLAY, | |
167 | G82_DISP_OVERLAY, | |
168 | NV50_DISP_OVERLAY, | |
410f3ec6 BS |
169 | 0 |
170 | }; | |
171 | ||
172 | return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), | |
173 | &oimm->base); | |
b5a794b0 BS |
174 | } |
175 | ||
176 | /****************************************************************************** | |
177 | * DMA EVO channel | |
178 | *****************************************************************************/ | |
179 | ||
e225f446 BS |
180 | struct nv50_dmac { |
181 | struct nv50_chan base; | |
3376ee37 BS |
182 | dma_addr_t handle; |
183 | u32 *ptr; | |
59ad1465 | 184 | |
0ad72863 BS |
185 | struct nvif_object sync; |
186 | struct nvif_object vram; | |
187 | ||
59ad1465 DV |
188 | /* Protects against concurrent pushbuf access to this channel, lock is |
189 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
190 | * dropped again by evo_kick. */ | |
191 | struct mutex lock; | |
b5a794b0 BS |
192 | }; |
193 | ||
194 | static void | |
0ad72863 | 195 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
b5a794b0 | 196 | { |
0ad72863 BS |
197 | nvif_object_fini(&dmac->vram); |
198 | nvif_object_fini(&dmac->sync); | |
199 | ||
200 | nv50_chan_destroy(&dmac->base); | |
201 | ||
b5a794b0 | 202 | if (dmac->ptr) { |
989aa5b7 | 203 | struct pci_dev *pdev = nvxx_device(nvif_device(disp))->pdev; |
b5a794b0 BS |
204 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); |
205 | } | |
b5a794b0 BS |
206 | } |
207 | ||
47057302 | 208 | static int |
410f3ec6 | 209 | nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head, |
47057302 | 210 | void *data, u32 size, u64 syncbuf, |
e225f446 | 211 | struct nv50_dmac *dmac) |
47057302 | 212 | { |
f392ec4b | 213 | struct nvif_device *device = nvif_device(disp); |
648d4dfd | 214 | struct nv50_disp_core_channel_dma_v0 *args = data; |
0ad72863 | 215 | struct nvif_object pushbuf; |
47057302 BS |
216 | int ret; |
217 | ||
59ad1465 DV |
218 | mutex_init(&dmac->lock); |
219 | ||
989aa5b7 | 220 | dmac->ptr = pci_alloc_consistent(nvxx_device(device)->pdev, |
0ad72863 | 221 | PAGE_SIZE, &dmac->handle); |
47057302 BS |
222 | if (!dmac->ptr) |
223 | return -ENOMEM; | |
224 | ||
f392ec4b | 225 | ret = nvif_object_init(nvif_object(device), NULL, |
648d4dfd | 226 | args->pushbuf, NV_DMA_FROM_MEMORY, |
4acfd707 BS |
227 | &(struct nv_dma_v0) { |
228 | .target = NV_DMA_V0_TARGET_PCI_US, | |
229 | .access = NV_DMA_V0_ACCESS_RD, | |
47057302 BS |
230 | .start = dmac->handle + 0x0000, |
231 | .limit = dmac->handle + 0x0fff, | |
4acfd707 | 232 | }, sizeof(struct nv_dma_v0), &pushbuf); |
b5a794b0 | 233 | if (ret) |
47057302 | 234 | return ret; |
b5a794b0 | 235 | |
410f3ec6 | 236 | ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base); |
0ad72863 | 237 | nvif_object_fini(&pushbuf); |
47057302 BS |
238 | if (ret) |
239 | return ret; | |
240 | ||
f45f55c4 | 241 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000, |
4acfd707 BS |
242 | NV_DMA_IN_MEMORY, |
243 | &(struct nv_dma_v0) { | |
244 | .target = NV_DMA_V0_TARGET_VRAM, | |
245 | .access = NV_DMA_V0_ACCESS_RDWR, | |
47057302 BS |
246 | .start = syncbuf + 0x0000, |
247 | .limit = syncbuf + 0x0fff, | |
4acfd707 | 248 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 249 | &dmac->sync); |
47057302 BS |
250 | if (ret) |
251 | return ret; | |
252 | ||
f45f55c4 | 253 | ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001, |
4acfd707 BS |
254 | NV_DMA_IN_MEMORY, |
255 | &(struct nv_dma_v0) { | |
256 | .target = NV_DMA_V0_TARGET_VRAM, | |
257 | .access = NV_DMA_V0_ACCESS_RDWR, | |
b5a794b0 | 258 | .start = 0, |
f392ec4b | 259 | .limit = device->info.ram_user - 1, |
4acfd707 | 260 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 261 | &dmac->vram); |
b5a794b0 | 262 | if (ret) |
47057302 BS |
263 | return ret; |
264 | ||
b5a794b0 BS |
265 | return ret; |
266 | } | |
267 | ||
410f3ec6 BS |
268 | /****************************************************************************** |
269 | * Core | |
270 | *****************************************************************************/ | |
271 | ||
e225f446 BS |
272 | struct nv50_mast { |
273 | struct nv50_dmac base; | |
b5a794b0 BS |
274 | }; |
275 | ||
410f3ec6 BS |
276 | static int |
277 | nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core) | |
278 | { | |
648d4dfd BS |
279 | struct nv50_disp_core_channel_dma_v0 args = { |
280 | .pushbuf = 0xb0007d00, | |
410f3ec6 BS |
281 | }; |
282 | static const u32 oclass[] = { | |
dbbd6bcf | 283 | GM204_DISP_CORE_CHANNEL_DMA, |
648d4dfd BS |
284 | GM107_DISP_CORE_CHANNEL_DMA, |
285 | GK110_DISP_CORE_CHANNEL_DMA, | |
286 | GK104_DISP_CORE_CHANNEL_DMA, | |
287 | GF110_DISP_CORE_CHANNEL_DMA, | |
288 | GT214_DISP_CORE_CHANNEL_DMA, | |
289 | GT206_DISP_CORE_CHANNEL_DMA, | |
290 | GT200_DISP_CORE_CHANNEL_DMA, | |
291 | G82_DISP_CORE_CHANNEL_DMA, | |
292 | NV50_DISP_CORE_CHANNEL_DMA, | |
410f3ec6 BS |
293 | 0 |
294 | }; | |
295 | ||
296 | return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf, | |
297 | &core->base); | |
298 | } | |
299 | ||
300 | /****************************************************************************** | |
301 | * Base | |
302 | *****************************************************************************/ | |
b5a794b0 | 303 | |
e225f446 BS |
304 | struct nv50_sync { |
305 | struct nv50_dmac base; | |
9f9bdaaf BS |
306 | u32 addr; |
307 | u32 data; | |
3376ee37 BS |
308 | }; |
309 | ||
410f3ec6 BS |
310 | static int |
311 | nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf, | |
312 | struct nv50_sync *base) | |
313 | { | |
648d4dfd BS |
314 | struct nv50_disp_base_channel_dma_v0 args = { |
315 | .pushbuf = 0xb0007c00 | head, | |
410f3ec6 BS |
316 | .head = head, |
317 | }; | |
318 | static const u32 oclass[] = { | |
648d4dfd BS |
319 | GK110_DISP_BASE_CHANNEL_DMA, |
320 | GK104_DISP_BASE_CHANNEL_DMA, | |
321 | GF110_DISP_BASE_CHANNEL_DMA, | |
322 | GT214_DISP_BASE_CHANNEL_DMA, | |
323 | GT200_DISP_BASE_CHANNEL_DMA, | |
324 | G82_DISP_BASE_CHANNEL_DMA, | |
325 | NV50_DISP_BASE_CHANNEL_DMA, | |
410f3ec6 BS |
326 | 0 |
327 | }; | |
328 | ||
329 | return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), | |
330 | syncbuf, &base->base); | |
331 | } | |
332 | ||
333 | /****************************************************************************** | |
334 | * Overlay | |
335 | *****************************************************************************/ | |
336 | ||
e225f446 BS |
337 | struct nv50_ovly { |
338 | struct nv50_dmac base; | |
b5a794b0 | 339 | }; |
f20ce962 | 340 | |
410f3ec6 BS |
341 | static int |
342 | nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf, | |
343 | struct nv50_ovly *ovly) | |
344 | { | |
648d4dfd BS |
345 | struct nv50_disp_overlay_channel_dma_v0 args = { |
346 | .pushbuf = 0xb0007e00 | head, | |
410f3ec6 BS |
347 | .head = head, |
348 | }; | |
349 | static const u32 oclass[] = { | |
648d4dfd BS |
350 | GK104_DISP_OVERLAY_CONTROL_DMA, |
351 | GF110_DISP_OVERLAY_CONTROL_DMA, | |
352 | GT214_DISP_OVERLAY_CHANNEL_DMA, | |
353 | GT200_DISP_OVERLAY_CHANNEL_DMA, | |
354 | G82_DISP_OVERLAY_CHANNEL_DMA, | |
355 | NV50_DISP_OVERLAY_CHANNEL_DMA, | |
410f3ec6 BS |
356 | 0 |
357 | }; | |
358 | ||
359 | return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), | |
360 | syncbuf, &ovly->base); | |
361 | } | |
26f6d88b | 362 | |
e225f446 | 363 | struct nv50_head { |
dd0e3d53 | 364 | struct nouveau_crtc base; |
8dda53fc | 365 | struct nouveau_bo *image; |
e225f446 BS |
366 | struct nv50_curs curs; |
367 | struct nv50_sync sync; | |
368 | struct nv50_ovly ovly; | |
369 | struct nv50_oimm oimm; | |
b5a794b0 BS |
370 | }; |
371 | ||
e225f446 BS |
372 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
373 | #define nv50_curs(c) (&nv50_head(c)->curs) | |
374 | #define nv50_sync(c) (&nv50_head(c)->sync) | |
375 | #define nv50_ovly(c) (&nv50_head(c)->ovly) | |
376 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
377 | #define nv50_chan(c) (&(c)->base.base) | |
0ad72863 BS |
378 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
379 | ||
380 | struct nv50_fbdma { | |
381 | struct list_head head; | |
382 | struct nvif_object core; | |
383 | struct nvif_object base[4]; | |
384 | }; | |
b5a794b0 | 385 | |
e225f446 | 386 | struct nv50_disp { |
0ad72863 | 387 | struct nvif_object *disp; |
e225f446 | 388 | struct nv50_mast mast; |
b5a794b0 | 389 | |
8a423647 | 390 | struct list_head fbdma; |
b5a794b0 BS |
391 | |
392 | struct nouveau_bo *sync; | |
dd0e3d53 BS |
393 | }; |
394 | ||
e225f446 BS |
395 | static struct nv50_disp * |
396 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 397 | { |
77145f1c | 398 | return nouveau_display(dev)->priv; |
26f6d88b BS |
399 | } |
400 | ||
e225f446 | 401 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 402 | |
bdb8c212 | 403 | static struct drm_crtc * |
e225f446 | 404 | nv50_display_crtc_get(struct drm_encoder *encoder) |
bdb8c212 BS |
405 | { |
406 | return nouveau_encoder(encoder)->crtc; | |
407 | } | |
408 | ||
409 | /****************************************************************************** | |
410 | * EVO channel helpers | |
411 | *****************************************************************************/ | |
51beb428 | 412 | static u32 * |
b5a794b0 | 413 | evo_wait(void *evoc, int nr) |
51beb428 | 414 | { |
e225f446 | 415 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 416 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
51beb428 | 417 | |
59ad1465 | 418 | mutex_lock(&dmac->lock); |
de8268c5 | 419 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 420 | dmac->ptr[put] = 0x20000000; |
51beb428 | 421 | |
0ad72863 | 422 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
989aa5b7 | 423 | if (!nvxx_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) { |
59ad1465 | 424 | mutex_unlock(&dmac->lock); |
989aa5b7 | 425 | nv_error(nvxx_object(&dmac->base.user), "channel stalled\n"); |
51beb428 BS |
426 | return NULL; |
427 | } | |
428 | ||
429 | put = 0; | |
430 | } | |
431 | ||
b5a794b0 | 432 | return dmac->ptr + put; |
51beb428 BS |
433 | } |
434 | ||
435 | static void | |
b5a794b0 | 436 | evo_kick(u32 *push, void *evoc) |
51beb428 | 437 | { |
e225f446 | 438 | struct nv50_dmac *dmac = evoc; |
0ad72863 | 439 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 440 | mutex_unlock(&dmac->lock); |
51beb428 BS |
441 | } |
442 | ||
2b1930c3 | 443 | #if 1 |
51beb428 BS |
444 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) |
445 | #define evo_data(p,d) *((p)++) = (d) | |
2b1930c3 BS |
446 | #else |
447 | #define evo_mthd(p,m,s) do { \ | |
448 | const u32 _m = (m), _s = (s); \ | |
449 | printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \ | |
450 | *((p)++) = ((_s << 18) | _m); \ | |
451 | } while(0) | |
452 | #define evo_data(p,d) do { \ | |
453 | const u32 _d = (d); \ | |
454 | printk(KERN_ERR "\t%08x\n", _d); \ | |
455 | *((p)++) = _d; \ | |
456 | } while(0) | |
457 | #endif | |
51beb428 | 458 | |
3376ee37 BS |
459 | static bool |
460 | evo_sync_wait(void *data) | |
461 | { | |
5cc027f6 BS |
462 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
463 | return true; | |
464 | usleep_range(1, 2); | |
465 | return false; | |
3376ee37 BS |
466 | } |
467 | ||
468 | static int | |
b5a794b0 | 469 | evo_sync(struct drm_device *dev) |
3376ee37 | 470 | { |
967e7bde | 471 | struct nvif_device *device = &nouveau_drm(dev)->device; |
e225f446 BS |
472 | struct nv50_disp *disp = nv50_disp(dev); |
473 | struct nv50_mast *mast = nv50_mast(dev); | |
b5a794b0 | 474 | u32 *push = evo_wait(mast, 8); |
3376ee37 | 475 | if (push) { |
816af2f2 | 476 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 477 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 478 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
479 | evo_mthd(push, 0x0080, 2); |
480 | evo_data(push, 0x00000000); | |
481 | evo_data(push, 0x00000000); | |
b5a794b0 | 482 | evo_kick(push, mast); |
989aa5b7 | 483 | if (nv_wait_cb(nvxx_device(device), evo_sync_wait, disp->sync)) |
3376ee37 BS |
484 | return 0; |
485 | } | |
486 | ||
487 | return -EBUSY; | |
488 | } | |
489 | ||
490 | /****************************************************************************** | |
a63a97eb | 491 | * Page flipping channel |
3376ee37 BS |
492 | *****************************************************************************/ |
493 | struct nouveau_bo * | |
e225f446 | 494 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
3376ee37 | 495 | { |
e225f446 | 496 | return nv50_disp(dev)->sync; |
3376ee37 BS |
497 | } |
498 | ||
9f9bdaaf BS |
499 | struct nv50_display_flip { |
500 | struct nv50_disp *disp; | |
501 | struct nv50_sync *chan; | |
502 | }; | |
503 | ||
504 | static bool | |
505 | nv50_display_flip_wait(void *data) | |
506 | { | |
507 | struct nv50_display_flip *flip = data; | |
508 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == | |
b1ea3e6e | 509 | flip->chan->data) |
9f9bdaaf BS |
510 | return true; |
511 | usleep_range(1, 2); | |
512 | return false; | |
513 | } | |
514 | ||
3376ee37 | 515 | void |
e225f446 | 516 | nv50_display_flip_stop(struct drm_crtc *crtc) |
3376ee37 | 517 | { |
967e7bde | 518 | struct nvif_device *device = &nouveau_drm(crtc->dev)->device; |
9f9bdaaf BS |
519 | struct nv50_display_flip flip = { |
520 | .disp = nv50_disp(crtc->dev), | |
521 | .chan = nv50_sync(crtc), | |
522 | }; | |
3376ee37 BS |
523 | u32 *push; |
524 | ||
9f9bdaaf | 525 | push = evo_wait(flip.chan, 8); |
3376ee37 BS |
526 | if (push) { |
527 | evo_mthd(push, 0x0084, 1); | |
528 | evo_data(push, 0x00000000); | |
529 | evo_mthd(push, 0x0094, 1); | |
530 | evo_data(push, 0x00000000); | |
531 | evo_mthd(push, 0x00c0, 1); | |
532 | evo_data(push, 0x00000000); | |
533 | evo_mthd(push, 0x0080, 1); | |
534 | evo_data(push, 0x00000000); | |
9f9bdaaf | 535 | evo_kick(push, flip.chan); |
3376ee37 | 536 | } |
9f9bdaaf | 537 | |
989aa5b7 | 538 | nv_wait_cb(nvxx_device(device), nv50_display_flip_wait, &flip); |
3376ee37 BS |
539 | } |
540 | ||
541 | int | |
e225f446 | 542 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3376ee37 BS |
543 | struct nouveau_channel *chan, u32 swap_interval) |
544 | { | |
545 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
3376ee37 | 546 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
8dda53fc | 547 | struct nv50_head *head = nv50_head(crtc); |
e225f446 | 548 | struct nv50_sync *sync = nv50_sync(crtc); |
3376ee37 | 549 | u32 *push; |
8dda53fc | 550 | int ret; |
3376ee37 | 551 | |
9ba83106 BS |
552 | if (crtc->primary->fb->width != fb->width || |
553 | crtc->primary->fb->height != fb->height) | |
554 | return -EINVAL; | |
555 | ||
3376ee37 BS |
556 | swap_interval <<= 4; |
557 | if (swap_interval == 0) | |
558 | swap_interval |= 0x100; | |
f60b6e7a BS |
559 | if (chan == NULL) |
560 | evo_sync(crtc->dev); | |
3376ee37 | 561 | |
b5a794b0 | 562 | push = evo_wait(sync, 128); |
3376ee37 BS |
563 | if (unlikely(push == NULL)) |
564 | return -EBUSY; | |
565 | ||
bbf8906b | 566 | if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) { |
9f9bdaaf BS |
567 | ret = RING_SPACE(chan, 8); |
568 | if (ret) | |
569 | return ret; | |
570 | ||
571 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); | |
8dda53fc | 572 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
9f9bdaaf BS |
573 | OUT_RING (chan, sync->addr ^ 0x10); |
574 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); | |
575 | OUT_RING (chan, sync->data + 1); | |
576 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); | |
577 | OUT_RING (chan, sync->addr); | |
578 | OUT_RING (chan, sync->data); | |
579 | } else | |
bbf8906b | 580 | if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) { |
8dda53fc | 581 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
582 | ret = RING_SPACE(chan, 12); |
583 | if (ret) | |
584 | return ret; | |
585 | ||
586 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
0ad72863 | 587 | OUT_RING (chan, chan->vram.handle); |
9f9bdaaf BS |
588 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
589 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
590 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
591 | OUT_RING (chan, sync->data + 1); | |
592 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
593 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
594 | OUT_RING (chan, upper_32_bits(addr)); | |
595 | OUT_RING (chan, lower_32_bits(addr)); | |
596 | OUT_RING (chan, sync->data); | |
597 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); | |
598 | } else | |
599 | if (chan) { | |
8dda53fc | 600 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
601 | ret = RING_SPACE(chan, 10); |
602 | if (ret) | |
603 | return ret; | |
604 | ||
605 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
606 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
607 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
608 | OUT_RING (chan, sync->data + 1); | |
609 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | | |
610 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
611 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
612 | OUT_RING (chan, upper_32_bits(addr)); | |
613 | OUT_RING (chan, lower_32_bits(addr)); | |
614 | OUT_RING (chan, sync->data); | |
615 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | | |
616 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
617 | } | |
35bcf5d5 | 618 | |
9f9bdaaf BS |
619 | if (chan) { |
620 | sync->addr ^= 0x10; | |
621 | sync->data++; | |
3376ee37 | 622 | FIRE_RING (chan); |
3376ee37 BS |
623 | } |
624 | ||
625 | /* queue the flip */ | |
626 | evo_mthd(push, 0x0100, 1); | |
627 | evo_data(push, 0xfffe0000); | |
628 | evo_mthd(push, 0x0084, 1); | |
629 | evo_data(push, swap_interval); | |
630 | if (!(swap_interval & 0x00000100)) { | |
631 | evo_mthd(push, 0x00e0, 1); | |
632 | evo_data(push, 0x40000000); | |
633 | } | |
634 | evo_mthd(push, 0x0088, 4); | |
9f9bdaaf BS |
635 | evo_data(push, sync->addr); |
636 | evo_data(push, sync->data++); | |
637 | evo_data(push, sync->data); | |
f45f55c4 | 638 | evo_data(push, sync->base.sync.handle); |
3376ee37 BS |
639 | evo_mthd(push, 0x00a0, 2); |
640 | evo_data(push, 0x00000000); | |
641 | evo_data(push, 0x00000000); | |
642 | evo_mthd(push, 0x00c0, 1); | |
8a423647 | 643 | evo_data(push, nv_fb->r_handle); |
3376ee37 BS |
644 | evo_mthd(push, 0x0110, 2); |
645 | evo_data(push, 0x00000000); | |
646 | evo_data(push, 0x00000000); | |
648d4dfd | 647 | if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) { |
ed5085a5 BS |
648 | evo_mthd(push, 0x0800, 5); |
649 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
650 | evo_data(push, 0); | |
651 | evo_data(push, (fb->height << 16) | fb->width); | |
652 | evo_data(push, nv_fb->r_pitch); | |
653 | evo_data(push, nv_fb->r_format); | |
654 | } else { | |
655 | evo_mthd(push, 0x0400, 5); | |
656 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
657 | evo_data(push, 0); | |
658 | evo_data(push, (fb->height << 16) | fb->width); | |
659 | evo_data(push, nv_fb->r_pitch); | |
660 | evo_data(push, nv_fb->r_format); | |
661 | } | |
3376ee37 BS |
662 | evo_mthd(push, 0x0080, 1); |
663 | evo_data(push, 0x00000000); | |
b5a794b0 | 664 | evo_kick(push, sync); |
8dda53fc BS |
665 | |
666 | nouveau_bo_ref(nv_fb->nvbo, &head->image); | |
3376ee37 BS |
667 | return 0; |
668 | } | |
669 | ||
438d99e3 BS |
670 | /****************************************************************************** |
671 | * CRTC | |
672 | *****************************************************************************/ | |
673 | static int | |
e225f446 | 674 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 675 | { |
e225f446 | 676 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de691855 BS |
677 | struct nouveau_connector *nv_connector; |
678 | struct drm_connector *connector; | |
679 | u32 *push, mode = 0x00; | |
438d99e3 | 680 | |
488ff207 | 681 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
682 | connector = &nv_connector->base; |
683 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
f4510a27 | 684 | if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) |
de691855 BS |
685 | mode = DITHERING_MODE_DYNAMIC2X2; |
686 | } else { | |
687 | mode = nv_connector->dithering_mode; | |
688 | } | |
689 | ||
690 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
691 | if (connector->display_info.bpc >= 8) | |
692 | mode |= DITHERING_DEPTH_8BPC; | |
693 | } else { | |
694 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
695 | } |
696 | ||
de8268c5 | 697 | push = evo_wait(mast, 4); |
438d99e3 | 698 | if (push) { |
648d4dfd | 699 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
700 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
701 | evo_data(push, mode); | |
702 | } else | |
648d4dfd | 703 | if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
704 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
705 | evo_data(push, mode); | |
706 | } else { | |
707 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); | |
708 | evo_data(push, mode); | |
709 | } | |
710 | ||
438d99e3 BS |
711 | if (update) { |
712 | evo_mthd(push, 0x0080, 1); | |
713 | evo_data(push, 0x00000000); | |
714 | } | |
de8268c5 | 715 | evo_kick(push, mast); |
438d99e3 BS |
716 | } |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static int | |
e225f446 | 722 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 723 | { |
e225f446 | 724 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
92854622 | 725 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
3376ee37 | 726 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 727 | struct nouveau_connector *nv_connector; |
92854622 BS |
728 | int mode = DRM_MODE_SCALE_NONE; |
729 | u32 oX, oY, *push; | |
f3fdc52d | 730 | |
92854622 BS |
731 | /* start off at the resolution we programmed the crtc for, this |
732 | * effectively handles NONE/FULL scaling | |
733 | */ | |
f3fdc52d | 734 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
576f7911 | 735 | if (nv_connector && nv_connector->native_mode) { |
92854622 | 736 | mode = nv_connector->scaling_mode; |
576f7911 BS |
737 | if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */ |
738 | mode = DRM_MODE_SCALE_FULLSCREEN; | |
739 | } | |
92854622 BS |
740 | |
741 | if (mode != DRM_MODE_SCALE_NONE) | |
742 | omode = nv_connector->native_mode; | |
743 | else | |
744 | omode = umode; | |
745 | ||
746 | oX = omode->hdisplay; | |
747 | oY = omode->vdisplay; | |
748 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
749 | oY *= 2; | |
750 | ||
751 | /* add overscan compensation if necessary, will keep the aspect | |
752 | * ratio the same as the backend mode unless overridden by the | |
753 | * user setting both hborder and vborder properties. | |
754 | */ | |
755 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
756 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
757 | nv_connector->edid && | |
758 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
759 | u32 bX = nv_connector->underscan_hborder; | |
760 | u32 bY = nv_connector->underscan_vborder; | |
761 | u32 aspect = (oY << 19) / oX; | |
762 | ||
763 | if (bX) { | |
764 | oX -= (bX * 2); | |
765 | if (bY) oY -= (bY * 2); | |
766 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
767 | } else { | |
768 | oX -= (oX >> 4) + 32; | |
769 | if (bY) oY -= (bY * 2); | |
770 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
771 | } | |
772 | } | |
773 | ||
774 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
775 | * removed already for overscan compensation | |
776 | */ | |
777 | switch (mode) { | |
778 | case DRM_MODE_SCALE_CENTER: | |
779 | oX = min((u32)umode->hdisplay, oX); | |
780 | oY = min((u32)umode->vdisplay, oY); | |
781 | /* fall-through */ | |
782 | case DRM_MODE_SCALE_ASPECT: | |
783 | if (oY < oX) { | |
784 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
785 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
786 | } else { | |
787 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
788 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 789 | } |
92854622 BS |
790 | break; |
791 | default: | |
792 | break; | |
f3fdc52d | 793 | } |
438d99e3 | 794 | |
de8268c5 | 795 | push = evo_wait(mast, 8); |
438d99e3 | 796 | if (push) { |
648d4dfd | 797 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
798 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
799 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); | |
800 | evo_data(push, (oY << 16) | oX); | |
801 | evo_data(push, (oY << 16) | oX); | |
802 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); | |
803 | evo_data(push, 0x00000000); | |
804 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); | |
805 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
806 | } else { | |
807 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
808 | evo_data(push, (oY << 16) | oX); | |
809 | evo_data(push, (oY << 16) | oX); | |
810 | evo_data(push, (oY << 16) | oX); | |
811 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); | |
812 | evo_data(push, 0x00000000); | |
813 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); | |
814 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
815 | } | |
816 | ||
817 | evo_kick(push, mast); | |
818 | ||
438d99e3 | 819 | if (update) { |
e225f446 | 820 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
821 | nv50_display_flip_next(crtc, crtc->primary->fb, |
822 | NULL, 1); | |
438d99e3 | 823 | } |
438d99e3 BS |
824 | } |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
eae7382b RS |
829 | static int |
830 | nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec) | |
831 | { | |
832 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); | |
833 | u32 *push; | |
834 | ||
835 | push = evo_wait(mast, 8); | |
836 | if (!push) | |
837 | return -ENOMEM; | |
838 | ||
839 | evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1); | |
840 | evo_data(push, usec); | |
841 | evo_kick(push, mast); | |
842 | return 0; | |
843 | } | |
844 | ||
f9887d09 | 845 | static int |
e225f446 | 846 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
f9887d09 | 847 | { |
e225f446 | 848 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
f9887d09 BS |
849 | u32 *push, hue, vib; |
850 | int adj; | |
851 | ||
852 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
853 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
854 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
855 | ||
856 | push = evo_wait(mast, 16); | |
857 | if (push) { | |
648d4dfd | 858 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
f9887d09 BS |
859 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
860 | evo_data(push, (hue << 20) | (vib << 8)); | |
861 | } else { | |
862 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); | |
863 | evo_data(push, (hue << 20) | (vib << 8)); | |
864 | } | |
865 | ||
866 | if (update) { | |
867 | evo_mthd(push, 0x0080, 1); | |
868 | evo_data(push, 0x00000000); | |
869 | } | |
870 | evo_kick(push, mast); | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
438d99e3 | 876 | static int |
e225f446 | 877 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
438d99e3 BS |
878 | int x, int y, bool update) |
879 | { | |
880 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
e225f446 | 881 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
438d99e3 BS |
882 | u32 *push; |
883 | ||
de8268c5 | 884 | push = evo_wait(mast, 16); |
438d99e3 | 885 | if (push) { |
648d4dfd | 886 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
887 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
888 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
889 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); | |
890 | evo_data(push, (fb->height << 16) | fb->width); | |
891 | evo_data(push, nvfb->r_pitch); | |
892 | evo_data(push, nvfb->r_format); | |
893 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); | |
894 | evo_data(push, (y << 16) | x); | |
648d4dfd | 895 | if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 896 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 897 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
898 | } |
899 | } else { | |
900 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
901 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
902 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
903 | evo_data(push, (fb->height << 16) | fb->width); | |
904 | evo_data(push, nvfb->r_pitch); | |
905 | evo_data(push, nvfb->r_format); | |
8a423647 | 906 | evo_data(push, nvfb->r_handle); |
de8268c5 BS |
907 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
908 | evo_data(push, (y << 16) | x); | |
909 | } | |
910 | ||
a46232ee BS |
911 | if (update) { |
912 | evo_mthd(push, 0x0080, 1); | |
913 | evo_data(push, 0x00000000); | |
914 | } | |
de8268c5 | 915 | evo_kick(push, mast); |
438d99e3 BS |
916 | } |
917 | ||
8a423647 | 918 | nv_crtc->fb.handle = nvfb->r_handle; |
438d99e3 BS |
919 | return 0; |
920 | } | |
921 | ||
922 | static void | |
e225f446 | 923 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
438d99e3 | 924 | { |
e225f446 | 925 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 926 | u32 *push = evo_wait(mast, 16); |
438d99e3 | 927 | if (push) { |
648d4dfd | 928 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
929 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
930 | evo_data(push, 0x85000000); | |
4dc63933 | 931 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
de8268c5 | 932 | } else |
648d4dfd | 933 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
934 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
935 | evo_data(push, 0x85000000); | |
4dc63933 | 936 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
de8268c5 | 937 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); |
f45f55c4 | 938 | evo_data(push, mast->base.vram.handle); |
de8268c5 | 939 | } else { |
438d99e3 BS |
940 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
941 | evo_data(push, 0x85000000); | |
4dc63933 | 942 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); |
438d99e3 | 943 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); |
f45f55c4 | 944 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
945 | } |
946 | evo_kick(push, mast); | |
947 | } | |
4dc63933 | 948 | nv_crtc->cursor.visible = true; |
de8268c5 BS |
949 | } |
950 | ||
951 | static void | |
e225f446 | 952 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
de8268c5 | 953 | { |
e225f446 | 954 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
955 | u32 *push = evo_wait(mast, 16); |
956 | if (push) { | |
648d4dfd | 957 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
958 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
959 | evo_data(push, 0x05000000); | |
960 | } else | |
648d4dfd | 961 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
962 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
963 | evo_data(push, 0x05000000); | |
964 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
965 | evo_data(push, 0x00000000); | |
438d99e3 BS |
966 | } else { |
967 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
968 | evo_data(push, 0x05000000); | |
969 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
970 | evo_data(push, 0x00000000); | |
971 | } | |
de8268c5 BS |
972 | evo_kick(push, mast); |
973 | } | |
4dc63933 | 974 | nv_crtc->cursor.visible = false; |
de8268c5 | 975 | } |
438d99e3 | 976 | |
de8268c5 | 977 | static void |
e225f446 | 978 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
de8268c5 | 979 | { |
e225f446 | 980 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 981 | |
697bb728 | 982 | if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled) |
e225f446 | 983 | nv50_crtc_cursor_show(nv_crtc); |
de8268c5 | 984 | else |
e225f446 | 985 | nv50_crtc_cursor_hide(nv_crtc); |
de8268c5 BS |
986 | |
987 | if (update) { | |
988 | u32 *push = evo_wait(mast, 2); | |
989 | if (push) { | |
438d99e3 BS |
990 | evo_mthd(push, 0x0080, 1); |
991 | evo_data(push, 0x00000000); | |
de8268c5 | 992 | evo_kick(push, mast); |
438d99e3 | 993 | } |
438d99e3 BS |
994 | } |
995 | } | |
996 | ||
997 | static void | |
e225f446 | 998 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
438d99e3 BS |
999 | { |
1000 | } | |
1001 | ||
1002 | static void | |
e225f446 | 1003 | nv50_crtc_prepare(struct drm_crtc *crtc) |
438d99e3 BS |
1004 | { |
1005 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 1006 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1007 | u32 *push; |
1008 | ||
e225f446 | 1009 | nv50_display_flip_stop(crtc); |
3376ee37 | 1010 | |
56d237d2 | 1011 | push = evo_wait(mast, 6); |
438d99e3 | 1012 | if (push) { |
648d4dfd | 1013 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1014 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1015 | evo_data(push, 0x00000000); | |
1016 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
1017 | evo_data(push, 0x40000000); | |
1018 | } else | |
648d4dfd | 1019 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1020 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1021 | evo_data(push, 0x00000000); | |
1022 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
1023 | evo_data(push, 0x40000000); | |
1024 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
1025 | evo_data(push, 0x00000000); | |
1026 | } else { | |
1027 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
1028 | evo_data(push, 0x00000000); | |
1029 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
1030 | evo_data(push, 0x03000000); | |
1031 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
1032 | evo_data(push, 0x00000000); | |
1033 | } | |
1034 | ||
1035 | evo_kick(push, mast); | |
438d99e3 BS |
1036 | } |
1037 | ||
e225f446 | 1038 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
438d99e3 BS |
1039 | } |
1040 | ||
1041 | static void | |
e225f446 | 1042 | nv50_crtc_commit(struct drm_crtc *crtc) |
438d99e3 BS |
1043 | { |
1044 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 1045 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1046 | u32 *push; |
1047 | ||
de8268c5 | 1048 | push = evo_wait(mast, 32); |
438d99e3 | 1049 | if (push) { |
648d4dfd | 1050 | if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1051 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1052 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1053 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1054 | evo_data(push, 0xc0000000); | |
1055 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1056 | } else | |
648d4dfd | 1057 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 | 1058 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
8a423647 | 1059 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1060 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); |
1061 | evo_data(push, 0xc0000000); | |
1062 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1063 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
f45f55c4 | 1064 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1065 | } else { |
1066 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
8a423647 | 1067 | evo_data(push, nv_crtc->fb.handle); |
de8268c5 BS |
1068 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); |
1069 | evo_data(push, 0x83000000); | |
1070 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1071 | evo_data(push, 0x00000000); | |
1072 | evo_data(push, 0x00000000); | |
1073 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
f45f55c4 | 1074 | evo_data(push, mast->base.vram.handle); |
de8268c5 BS |
1075 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
1076 | evo_data(push, 0xffffff00); | |
1077 | } | |
1078 | ||
1079 | evo_kick(push, mast); | |
438d99e3 BS |
1080 | } |
1081 | ||
5a560252 | 1082 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); |
f4510a27 | 1083 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); |
438d99e3 BS |
1084 | } |
1085 | ||
1086 | static bool | |
e225f446 | 1087 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
438d99e3 BS |
1088 | struct drm_display_mode *adjusted_mode) |
1089 | { | |
eb2e9686 | 1090 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
438d99e3 BS |
1091 | return true; |
1092 | } | |
1093 | ||
1094 | static int | |
e225f446 | 1095 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
438d99e3 | 1096 | { |
f4510a27 | 1097 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); |
8dda53fc | 1098 | struct nv50_head *head = nv50_head(crtc); |
438d99e3 BS |
1099 | int ret; |
1100 | ||
547ad072 | 1101 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true); |
8dda53fc BS |
1102 | if (ret == 0) { |
1103 | if (head->image) | |
1104 | nouveau_bo_unpin(head->image); | |
1105 | nouveau_bo_ref(nvfb->nvbo, &head->image); | |
438d99e3 BS |
1106 | } |
1107 | ||
8dda53fc | 1108 | return ret; |
438d99e3 BS |
1109 | } |
1110 | ||
1111 | static int | |
e225f446 | 1112 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
438d99e3 BS |
1113 | struct drm_display_mode *mode, int x, int y, |
1114 | struct drm_framebuffer *old_fb) | |
1115 | { | |
e225f446 | 1116 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1117 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1118 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
1119 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1120 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
1121 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
1122 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
1dce6264 | 1123 | u32 vblan2e = 0, vblan2s = 1, vblankus = 0; |
3488c57b | 1124 | u32 *push; |
438d99e3 BS |
1125 | int ret; |
1126 | ||
2d1d898b BS |
1127 | hactive = mode->htotal; |
1128 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
1129 | hbackp = mode->htotal - mode->hsync_end; | |
1130 | hblanke = hsynce + hbackp; | |
1131 | hfrontp = mode->hsync_start - mode->hdisplay; | |
1132 | hblanks = mode->htotal - hfrontp - 1; | |
1133 | ||
1134 | vactive = mode->vtotal * vscan / ilace; | |
1135 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
1136 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
1137 | vblanke = vsynce + vbackp; | |
1138 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
1139 | vblanks = vactive - vfrontp - 1; | |
1dce6264 RS |
1140 | /* XXX: Safe underestimate, even "0" works */ |
1141 | vblankus = (vactive - mode->vdisplay - 2) * hactive; | |
1142 | vblankus *= 1000; | |
1143 | vblankus /= mode->clock; | |
1144 | ||
2d1d898b BS |
1145 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
1146 | vblan2e = vactive + vsynce + vbackp; | |
1147 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
1148 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
1149 | } |
1150 | ||
e225f446 | 1151 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1152 | if (ret) |
1153 | return ret; | |
1154 | ||
de8268c5 | 1155 | push = evo_wait(mast, 64); |
438d99e3 | 1156 | if (push) { |
648d4dfd | 1157 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
de8268c5 BS |
1158 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1159 | evo_data(push, 0x00800000 | mode->clock); | |
1160 | evo_data(push, (ilace == 2) ? 2 : 0); | |
eae7382b | 1161 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); |
de8268c5 BS |
1162 | evo_data(push, 0x00000000); |
1163 | evo_data(push, (vactive << 16) | hactive); | |
1164 | evo_data(push, ( vsynce << 16) | hsynce); | |
1165 | evo_data(push, (vblanke << 16) | hblanke); | |
1166 | evo_data(push, (vblanks << 16) | hblanks); | |
1167 | evo_data(push, (vblan2e << 16) | vblan2s); | |
eae7382b | 1168 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); |
de8268c5 BS |
1169 | evo_data(push, 0x00000000); |
1170 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); | |
1171 | evo_data(push, 0x00000311); | |
1172 | evo_data(push, 0x00000100); | |
1173 | } else { | |
1174 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); | |
1175 | evo_data(push, 0x00000000); | |
1176 | evo_data(push, (vactive << 16) | hactive); | |
1177 | evo_data(push, ( vsynce << 16) | hsynce); | |
1178 | evo_data(push, (vblanke << 16) | hblanke); | |
1179 | evo_data(push, (vblanks << 16) | hblanks); | |
1180 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1181 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); | |
1182 | evo_data(push, 0x00000000); /* ??? */ | |
1183 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
1184 | evo_data(push, mode->clock * 1000); | |
1185 | evo_data(push, 0x00200000); /* ??? */ | |
1186 | evo_data(push, mode->clock * 1000); | |
1187 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); | |
1188 | evo_data(push, 0x00000311); | |
1189 | evo_data(push, 0x00000100); | |
1190 | } | |
1191 | ||
1192 | evo_kick(push, mast); | |
438d99e3 BS |
1193 | } |
1194 | ||
1195 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
e225f446 BS |
1196 | nv50_crtc_set_dither(nv_crtc, false); |
1197 | nv50_crtc_set_scale(nv_crtc, false); | |
eae7382b RS |
1198 | |
1199 | /* G94 only accepts this after setting scale */ | |
1200 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) | |
1201 | nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus); | |
1202 | ||
e225f446 | 1203 | nv50_crtc_set_color_vibrance(nv_crtc, false); |
f4510a27 | 1204 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); |
438d99e3 BS |
1205 | return 0; |
1206 | } | |
1207 | ||
1208 | static int | |
e225f446 | 1209 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
438d99e3 BS |
1210 | struct drm_framebuffer *old_fb) |
1211 | { | |
77145f1c | 1212 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
438d99e3 BS |
1213 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1214 | int ret; | |
1215 | ||
f4510a27 | 1216 | if (!crtc->primary->fb) { |
77145f1c | 1217 | NV_DEBUG(drm, "No FB bound\n"); |
84e2ad8b BS |
1218 | return 0; |
1219 | } | |
1220 | ||
e225f446 | 1221 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1222 | if (ret) |
1223 | return ret; | |
1224 | ||
e225f446 | 1225 | nv50_display_flip_stop(crtc); |
f4510a27 MR |
1226 | nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); |
1227 | nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); | |
438d99e3 BS |
1228 | return 0; |
1229 | } | |
1230 | ||
1231 | static int | |
e225f446 | 1232 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
438d99e3 BS |
1233 | struct drm_framebuffer *fb, int x, int y, |
1234 | enum mode_set_atomic state) | |
1235 | { | |
1236 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1237 | nv50_display_flip_stop(crtc); |
1238 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); | |
438d99e3 BS |
1239 | return 0; |
1240 | } | |
1241 | ||
1242 | static void | |
e225f446 | 1243 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
438d99e3 | 1244 | { |
e225f446 | 1245 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
1246 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1247 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
1248 | int i; | |
1249 | ||
1250 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
1251 | u16 r = nv_crtc->lut.r[i] >> 2; |
1252 | u16 g = nv_crtc->lut.g[i] >> 2; | |
1253 | u16 b = nv_crtc->lut.b[i] >> 2; | |
1254 | ||
648d4dfd | 1255 | if (disp->disp->oclass < GF110_DISP) { |
de8268c5 BS |
1256 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
1257 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
1258 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
1259 | } else { | |
1260 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
1261 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
1262 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
1263 | } | |
438d99e3 BS |
1264 | } |
1265 | } | |
1266 | ||
8dda53fc BS |
1267 | static void |
1268 | nv50_crtc_disable(struct drm_crtc *crtc) | |
1269 | { | |
1270 | struct nv50_head *head = nv50_head(crtc); | |
efa366fd | 1271 | evo_sync(crtc->dev); |
8dda53fc BS |
1272 | if (head->image) |
1273 | nouveau_bo_unpin(head->image); | |
1274 | nouveau_bo_ref(NULL, &head->image); | |
1275 | } | |
1276 | ||
438d99e3 | 1277 | static int |
e225f446 | 1278 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
438d99e3 BS |
1279 | uint32_t handle, uint32_t width, uint32_t height) |
1280 | { | |
1281 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1282 | struct drm_device *dev = crtc->dev; | |
5a560252 BS |
1283 | struct drm_gem_object *gem = NULL; |
1284 | struct nouveau_bo *nvbo = NULL; | |
1285 | int ret = 0; | |
438d99e3 | 1286 | |
5a560252 | 1287 | if (handle) { |
438d99e3 BS |
1288 | if (width != 64 || height != 64) |
1289 | return -EINVAL; | |
1290 | ||
1291 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
1292 | if (unlikely(!gem)) | |
1293 | return -ENOENT; | |
1294 | nvbo = nouveau_gem_object(gem); | |
1295 | ||
5a560252 | 1296 | ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true); |
438d99e3 BS |
1297 | } |
1298 | ||
5a560252 | 1299 | if (ret == 0) { |
4dc63933 ML |
1300 | if (nv_crtc->cursor.nvbo) |
1301 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
1302 | nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo); | |
438d99e3 | 1303 | } |
5a560252 | 1304 | drm_gem_object_unreference_unlocked(gem); |
438d99e3 | 1305 | |
5a560252 | 1306 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); |
438d99e3 BS |
1307 | return ret; |
1308 | } | |
1309 | ||
1310 | static int | |
e225f446 | 1311 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
438d99e3 | 1312 | { |
4dc63933 | 1313 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
e225f446 BS |
1314 | struct nv50_curs *curs = nv50_curs(crtc); |
1315 | struct nv50_chan *chan = nv50_chan(curs); | |
0ad72863 BS |
1316 | nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1317 | nvif_wr32(&chan->user, 0x0080, 0x00000000); | |
4dc63933 ML |
1318 | |
1319 | nv_crtc->cursor_saved_x = x; | |
1320 | nv_crtc->cursor_saved_y = y; | |
438d99e3 BS |
1321 | return 0; |
1322 | } | |
1323 | ||
1324 | static void | |
e225f446 | 1325 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
438d99e3 BS |
1326 | uint32_t start, uint32_t size) |
1327 | { | |
1328 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
bdefc8cb | 1329 | u32 end = min_t(u32, start + size, 256); |
438d99e3 BS |
1330 | u32 i; |
1331 | ||
1332 | for (i = start; i < end; i++) { | |
1333 | nv_crtc->lut.r[i] = r[i]; | |
1334 | nv_crtc->lut.g[i] = g[i]; | |
1335 | nv_crtc->lut.b[i] = b[i]; | |
1336 | } | |
1337 | ||
e225f446 | 1338 | nv50_crtc_lut_load(crtc); |
438d99e3 BS |
1339 | } |
1340 | ||
4dc63933 ML |
1341 | static void |
1342 | nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y) | |
1343 | { | |
1344 | nv50_crtc_cursor_move(&nv_crtc->base, x, y); | |
1345 | ||
1346 | nv50_crtc_cursor_show_hide(nv_crtc, true, true); | |
1347 | } | |
1348 | ||
438d99e3 | 1349 | static void |
e225f446 | 1350 | nv50_crtc_destroy(struct drm_crtc *crtc) |
438d99e3 BS |
1351 | { |
1352 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1353 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1354 | struct nv50_head *head = nv50_head(crtc); | |
0ad72863 | 1355 | struct nv50_fbdma *fbdma; |
8dda53fc | 1356 | |
0ad72863 BS |
1357 | list_for_each_entry(fbdma, &disp->fbdma, head) { |
1358 | nvif_object_fini(&fbdma->base[nv_crtc->index]); | |
1359 | } | |
1360 | ||
1361 | nv50_dmac_destroy(&head->ovly.base, disp->disp); | |
1362 | nv50_pioc_destroy(&head->oimm.base); | |
1363 | nv50_dmac_destroy(&head->sync.base, disp->disp); | |
1364 | nv50_pioc_destroy(&head->curs.base); | |
8dda53fc BS |
1365 | |
1366 | /*XXX: this shouldn't be necessary, but the core doesn't call | |
1367 | * disconnect() during the cleanup paths | |
1368 | */ | |
1369 | if (head->image) | |
1370 | nouveau_bo_unpin(head->image); | |
1371 | nouveau_bo_ref(NULL, &head->image); | |
1372 | ||
5a560252 | 1373 | /*XXX: ditto */ |
4dc63933 ML |
1374 | if (nv_crtc->cursor.nvbo) |
1375 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
1376 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
8dda53fc | 1377 | |
438d99e3 | 1378 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
04c8c210 MS |
1379 | if (nv_crtc->lut.nvbo) |
1380 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
438d99e3 | 1381 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
8dda53fc | 1382 | |
438d99e3 BS |
1383 | drm_crtc_cleanup(crtc); |
1384 | kfree(crtc); | |
1385 | } | |
1386 | ||
e225f446 BS |
1387 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1388 | .dpms = nv50_crtc_dpms, | |
1389 | .prepare = nv50_crtc_prepare, | |
1390 | .commit = nv50_crtc_commit, | |
1391 | .mode_fixup = nv50_crtc_mode_fixup, | |
1392 | .mode_set = nv50_crtc_mode_set, | |
1393 | .mode_set_base = nv50_crtc_mode_set_base, | |
1394 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, | |
1395 | .load_lut = nv50_crtc_lut_load, | |
8dda53fc | 1396 | .disable = nv50_crtc_disable, |
438d99e3 BS |
1397 | }; |
1398 | ||
e225f446 BS |
1399 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1400 | .cursor_set = nv50_crtc_cursor_set, | |
1401 | .cursor_move = nv50_crtc_cursor_move, | |
1402 | .gamma_set = nv50_crtc_gamma_set, | |
5addcf0a | 1403 | .set_config = nouveau_crtc_set_config, |
e225f446 | 1404 | .destroy = nv50_crtc_destroy, |
3376ee37 | 1405 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
1406 | }; |
1407 | ||
1408 | static int | |
0ad72863 | 1409 | nv50_crtc_create(struct drm_device *dev, int index) |
438d99e3 | 1410 | { |
e225f446 BS |
1411 | struct nv50_disp *disp = nv50_disp(dev); |
1412 | struct nv50_head *head; | |
438d99e3 BS |
1413 | struct drm_crtc *crtc; |
1414 | int ret, i; | |
1415 | ||
dd0e3d53 BS |
1416 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1417 | if (!head) | |
438d99e3 BS |
1418 | return -ENOMEM; |
1419 | ||
dd0e3d53 | 1420 | head->base.index = index; |
e225f446 BS |
1421 | head->base.set_dither = nv50_crtc_set_dither; |
1422 | head->base.set_scale = nv50_crtc_set_scale; | |
1423 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; | |
f9887d09 BS |
1424 | head->base.color_vibrance = 50; |
1425 | head->base.vibrant_hue = 0; | |
4dc63933 | 1426 | head->base.cursor.set_pos = nv50_crtc_cursor_restore; |
438d99e3 | 1427 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
1428 | head->base.lut.r[i] = i << 8; |
1429 | head->base.lut.g[i] = i << 8; | |
1430 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
1431 | } |
1432 | ||
dd0e3d53 | 1433 | crtc = &head->base.base; |
e225f446 BS |
1434 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1435 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); | |
438d99e3 BS |
1436 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1437 | ||
b5a794b0 | 1438 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
bb6178b0 | 1439 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
b5a794b0 | 1440 | if (!ret) { |
547ad072 | 1441 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 1442 | if (!ret) { |
b5a794b0 | 1443 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
1444 | if (ret) |
1445 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1446 | } | |
b5a794b0 BS |
1447 | if (ret) |
1448 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
1449 | } | |
1450 | ||
1451 | if (ret) | |
1452 | goto out; | |
1453 | ||
b5a794b0 | 1454 | /* allocate cursor resources */ |
410f3ec6 | 1455 | ret = nv50_curs_create(disp->disp, index, &head->curs); |
438d99e3 BS |
1456 | if (ret) |
1457 | goto out; | |
1458 | ||
b5a794b0 | 1459 | /* allocate page flip / sync resources */ |
410f3ec6 BS |
1460 | ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset, |
1461 | &head->sync); | |
b5a794b0 BS |
1462 | if (ret) |
1463 | goto out; | |
1464 | ||
9f9bdaaf BS |
1465 | head->sync.addr = EVO_FLIP_SEM0(index); |
1466 | head->sync.data = 0x00000000; | |
438d99e3 | 1467 | |
b5a794b0 | 1468 | /* allocate overlay resources */ |
410f3ec6 | 1469 | ret = nv50_oimm_create(disp->disp, index, &head->oimm); |
438d99e3 BS |
1470 | if (ret) |
1471 | goto out; | |
1472 | ||
410f3ec6 BS |
1473 | ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset, |
1474 | &head->ovly); | |
b5a794b0 BS |
1475 | if (ret) |
1476 | goto out; | |
438d99e3 BS |
1477 | |
1478 | out: | |
1479 | if (ret) | |
e225f446 | 1480 | nv50_crtc_destroy(crtc); |
438d99e3 BS |
1481 | return ret; |
1482 | } | |
1483 | ||
a91d3221 BS |
1484 | /****************************************************************************** |
1485 | * Encoder helpers | |
1486 | *****************************************************************************/ | |
1487 | static bool | |
1488 | nv50_encoder_mode_fixup(struct drm_encoder *encoder, | |
1489 | const struct drm_display_mode *mode, | |
1490 | struct drm_display_mode *adjusted_mode) | |
1491 | { | |
1492 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1493 | struct nouveau_connector *nv_connector; | |
1494 | ||
1495 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1496 | if (nv_connector && nv_connector->native_mode) { | |
576f7911 BS |
1497 | nv_connector->scaling_full = false; |
1498 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) { | |
1499 | switch (nv_connector->type) { | |
1500 | case DCB_CONNECTOR_LVDS: | |
1501 | case DCB_CONNECTOR_LVDS_SPWG: | |
1502 | case DCB_CONNECTOR_eDP: | |
1503 | /* force use of scaler for non-edid modes */ | |
1504 | if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) | |
1505 | return true; | |
1506 | nv_connector->scaling_full = true; | |
1507 | break; | |
1508 | default: | |
1509 | return true; | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | drm_mode_copy(adjusted_mode, nv_connector->native_mode); | |
a91d3221 BS |
1514 | } |
1515 | ||
1516 | return true; | |
1517 | } | |
1518 | ||
26f6d88b BS |
1519 | /****************************************************************************** |
1520 | * DAC | |
1521 | *****************************************************************************/ | |
8eaa9669 | 1522 | static void |
e225f446 | 1523 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
1524 | { |
1525 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1526 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
bf0eb898 BS |
1527 | struct { |
1528 | struct nv50_disp_mthd_v1 base; | |
1529 | struct nv50_disp_dac_pwr_v0 pwr; | |
1530 | } args = { | |
1531 | .base.version = 1, | |
1532 | .base.method = NV50_DISP_MTHD_V1_DAC_PWR, | |
1533 | .base.hasht = nv_encoder->dcb->hasht, | |
1534 | .base.hashm = nv_encoder->dcb->hashm, | |
1535 | .pwr.state = 1, | |
1536 | .pwr.data = 1, | |
1537 | .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && | |
1538 | mode != DRM_MODE_DPMS_OFF), | |
1539 | .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && | |
1540 | mode != DRM_MODE_DPMS_OFF), | |
1541 | }; | |
8eaa9669 | 1542 | |
bf0eb898 | 1543 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
8eaa9669 BS |
1544 | } |
1545 | ||
8eaa9669 | 1546 | static void |
e225f446 | 1547 | nv50_dac_commit(struct drm_encoder *encoder) |
8eaa9669 BS |
1548 | { |
1549 | } | |
1550 | ||
1551 | static void | |
e225f446 | 1552 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
8eaa9669 BS |
1553 | struct drm_display_mode *adjusted_mode) |
1554 | { | |
e225f446 | 1555 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
1556 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1557 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
97b19b5c | 1558 | u32 *push; |
8eaa9669 | 1559 | |
e225f446 | 1560 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
8eaa9669 | 1561 | |
97b19b5c | 1562 | push = evo_wait(mast, 8); |
8eaa9669 | 1563 | if (push) { |
648d4dfd | 1564 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1565 | u32 syncs = 0x00000000; |
1566 | ||
1567 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1568 | syncs |= 0x00000001; | |
1569 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1570 | syncs |= 0x00000002; | |
1571 | ||
1572 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
1573 | evo_data(push, 1 << nv_crtc->index); | |
1574 | evo_data(push, syncs); | |
1575 | } else { | |
1576 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1577 | u32 syncs = 0x00000001; | |
1578 | ||
1579 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1580 | syncs |= 0x00000008; | |
1581 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1582 | syncs |= 0x00000010; | |
1583 | ||
1584 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1585 | magic |= 0x00000001; | |
1586 | ||
1587 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1588 | evo_data(push, syncs); | |
1589 | evo_data(push, magic); | |
1590 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
1591 | evo_data(push, 1 << nv_crtc->index); | |
1592 | } | |
1593 | ||
1594 | evo_kick(push, mast); | |
8eaa9669 BS |
1595 | } |
1596 | ||
1597 | nv_encoder->crtc = encoder->crtc; | |
1598 | } | |
1599 | ||
1600 | static void | |
e225f446 | 1601 | nv50_dac_disconnect(struct drm_encoder *encoder) |
8eaa9669 BS |
1602 | { |
1603 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1604 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
97b19b5c | 1605 | const int or = nv_encoder->or; |
8eaa9669 BS |
1606 | u32 *push; |
1607 | ||
1608 | if (nv_encoder->crtc) { | |
e225f446 | 1609 | nv50_crtc_prepare(nv_encoder->crtc); |
8eaa9669 | 1610 | |
97b19b5c | 1611 | push = evo_wait(mast, 4); |
8eaa9669 | 1612 | if (push) { |
648d4dfd | 1613 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
97b19b5c BS |
1614 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1615 | evo_data(push, 0x00000000); | |
1616 | } else { | |
1617 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
1618 | evo_data(push, 0x00000000); | |
1619 | } | |
97b19b5c | 1620 | evo_kick(push, mast); |
8eaa9669 | 1621 | } |
8eaa9669 | 1622 | } |
97b19b5c BS |
1623 | |
1624 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
1625 | } |
1626 | ||
b6d8e7ec | 1627 | static enum drm_connector_status |
e225f446 | 1628 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 1629 | { |
c4abd317 | 1630 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1631 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
c4abd317 BS |
1632 | struct { |
1633 | struct nv50_disp_mthd_v1 base; | |
1634 | struct nv50_disp_dac_load_v0 load; | |
1635 | } args = { | |
1636 | .base.version = 1, | |
1637 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, | |
1638 | .base.hasht = nv_encoder->dcb->hasht, | |
1639 | .base.hashm = nv_encoder->dcb->hashm, | |
1640 | }; | |
1641 | int ret; | |
1642 | ||
1643 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; | |
1644 | if (args.load.data == 0) | |
1645 | args.load.data = 340; | |
b681993f | 1646 | |
c4abd317 BS |
1647 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
1648 | if (ret || !args.load.load) | |
35b21d39 | 1649 | return connector_status_disconnected; |
b681993f | 1650 | |
35b21d39 | 1651 | return connector_status_connected; |
b6d8e7ec BS |
1652 | } |
1653 | ||
8eaa9669 | 1654 | static void |
e225f446 | 1655 | nv50_dac_destroy(struct drm_encoder *encoder) |
8eaa9669 BS |
1656 | { |
1657 | drm_encoder_cleanup(encoder); | |
1658 | kfree(encoder); | |
1659 | } | |
1660 | ||
e225f446 BS |
1661 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1662 | .dpms = nv50_dac_dpms, | |
a91d3221 | 1663 | .mode_fixup = nv50_encoder_mode_fixup, |
e225f446 BS |
1664 | .prepare = nv50_dac_disconnect, |
1665 | .commit = nv50_dac_commit, | |
1666 | .mode_set = nv50_dac_mode_set, | |
1667 | .disable = nv50_dac_disconnect, | |
1668 | .get_crtc = nv50_display_crtc_get, | |
1669 | .detect = nv50_dac_detect | |
8eaa9669 BS |
1670 | }; |
1671 | ||
e225f446 BS |
1672 | static const struct drm_encoder_funcs nv50_dac_func = { |
1673 | .destroy = nv50_dac_destroy, | |
8eaa9669 BS |
1674 | }; |
1675 | ||
1676 | static int | |
e225f446 | 1677 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 1678 | { |
5ed50209 | 1679 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 1680 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
8eaa9669 BS |
1681 | struct nouveau_encoder *nv_encoder; |
1682 | struct drm_encoder *encoder; | |
5ed50209 | 1683 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
1684 | |
1685 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1686 | if (!nv_encoder) | |
1687 | return -ENOMEM; | |
1688 | nv_encoder->dcb = dcbe; | |
1689 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1690 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
8eaa9669 BS |
1691 | |
1692 | encoder = to_drm_encoder(nv_encoder); | |
1693 | encoder->possible_crtcs = dcbe->heads; | |
1694 | encoder->possible_clones = 0; | |
5ed50209 | 1695 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
e225f446 | 1696 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
8eaa9669 BS |
1697 | |
1698 | drm_mode_connector_attach_encoder(connector, encoder); | |
1699 | return 0; | |
1700 | } | |
26f6d88b | 1701 | |
78951d22 BS |
1702 | /****************************************************************************** |
1703 | * Audio | |
1704 | *****************************************************************************/ | |
1705 | static void | |
e225f446 | 1706 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 BS |
1707 | { |
1708 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cc2a9071 | 1709 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
78951d22 | 1710 | struct nouveau_connector *nv_connector; |
e225f446 | 1711 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
d889c524 BS |
1712 | struct __packed { |
1713 | struct { | |
1714 | struct nv50_disp_mthd_v1 mthd; | |
1715 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1716 | } base; | |
120b0c39 BS |
1717 | u8 data[sizeof(nv_connector->base.eld)]; |
1718 | } args = { | |
d889c524 BS |
1719 | .base.mthd.version = 1, |
1720 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1721 | .base.mthd.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1722 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1723 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1724 | }; |
78951d22 BS |
1725 | |
1726 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1727 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1728 | return; | |
1729 | ||
78951d22 | 1730 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
120b0c39 | 1731 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
78951d22 | 1732 | |
938fd8aa JN |
1733 | nvif_mthd(disp->disp, 0, &args, |
1734 | sizeof(args.base) + drm_eld_size(args.data)); | |
78951d22 BS |
1735 | } |
1736 | ||
1737 | static void | |
cc2a9071 | 1738 | nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 BS |
1739 | { |
1740 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1741 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
120b0c39 BS |
1742 | struct { |
1743 | struct nv50_disp_mthd_v1 base; | |
1744 | struct nv50_disp_sor_hda_eld_v0 eld; | |
1745 | } args = { | |
1746 | .base.version = 1, | |
1747 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, | |
1748 | .base.hasht = nv_encoder->dcb->hasht, | |
cc2a9071 BS |
1749 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
1750 | (0x0100 << nv_crtc->index), | |
120b0c39 | 1751 | }; |
78951d22 | 1752 | |
120b0c39 | 1753 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1754 | } |
1755 | ||
1756 | /****************************************************************************** | |
1757 | * HDMI | |
1758 | *****************************************************************************/ | |
1759 | static void | |
e225f446 | 1760 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 1761 | { |
64d9cc04 BS |
1762 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1763 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
e225f446 | 1764 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1765 | struct { |
1766 | struct nv50_disp_mthd_v1 base; | |
1767 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1768 | } args = { | |
1769 | .base.version = 1, | |
1770 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1771 | .base.hasht = nv_encoder->dcb->hasht, | |
1772 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1773 | (0x0100 << nv_crtc->index), | |
1774 | .pwr.state = 1, | |
1775 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ | |
1776 | }; | |
1777 | struct nouveau_connector *nv_connector; | |
64d9cc04 BS |
1778 | u32 max_ac_packet; |
1779 | ||
1780 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1781 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1782 | return; | |
1783 | ||
1784 | max_ac_packet = mode->htotal - mode->hdisplay; | |
e00f2235 | 1785 | max_ac_packet -= args.pwr.rekey; |
64d9cc04 | 1786 | max_ac_packet -= 18; /* constant from tegra */ |
e00f2235 | 1787 | args.pwr.max_ac_packet = max_ac_packet / 32; |
091e40cd | 1788 | |
e00f2235 | 1789 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
e225f446 | 1790 | nv50_audio_mode_set(encoder, mode); |
78951d22 BS |
1791 | } |
1792 | ||
1793 | static void | |
e84a35a8 | 1794 | nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
78951d22 | 1795 | { |
64d9cc04 | 1796 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
e225f446 | 1797 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
e00f2235 BS |
1798 | struct { |
1799 | struct nv50_disp_mthd_v1 base; | |
1800 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; | |
1801 | } args = { | |
1802 | .base.version = 1, | |
1803 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, | |
1804 | .base.hasht = nv_encoder->dcb->hasht, | |
1805 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | | |
1806 | (0x0100 << nv_crtc->index), | |
1807 | }; | |
64d9cc04 | 1808 | |
e00f2235 | 1809 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
78951d22 BS |
1810 | } |
1811 | ||
26f6d88b BS |
1812 | /****************************************************************************** |
1813 | * SOR | |
1814 | *****************************************************************************/ | |
83fc083c | 1815 | static void |
e225f446 | 1816 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
1817 | { |
1818 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
d55b4af9 BS |
1819 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1820 | struct { | |
1821 | struct nv50_disp_mthd_v1 base; | |
1822 | struct nv50_disp_sor_pwr_v0 pwr; | |
1823 | } args = { | |
1824 | .base.version = 1, | |
1825 | .base.method = NV50_DISP_MTHD_V1_SOR_PWR, | |
1826 | .base.hasht = nv_encoder->dcb->hasht, | |
1827 | .base.hashm = nv_encoder->dcb->hashm, | |
1828 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1829 | }; | |
c02ed2bf BS |
1830 | struct { |
1831 | struct nv50_disp_mthd_v1 base; | |
1832 | struct nv50_disp_sor_dp_pwr_v0 pwr; | |
1833 | } link = { | |
1834 | .base.version = 1, | |
1835 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR, | |
1836 | .base.hasht = nv_encoder->dcb->hasht, | |
1837 | .base.hashm = nv_encoder->dcb->hashm, | |
1838 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
1839 | }; | |
83fc083c BS |
1840 | struct drm_device *dev = encoder->dev; |
1841 | struct drm_encoder *partner; | |
83fc083c BS |
1842 | |
1843 | nv_encoder->last_dpms = mode; | |
1844 | ||
1845 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1846 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1847 | ||
1848 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1849 | continue; | |
1850 | ||
1851 | if (nv_partner != nv_encoder && | |
26cfa813 | 1852 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1853 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1854 | return; | |
1855 | break; | |
1856 | } | |
1857 | } | |
1858 | ||
4874322e | 1859 | if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { |
d55b4af9 BS |
1860 | args.pwr.state = 1; |
1861 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
c02ed2bf | 1862 | nvif_mthd(disp->disp, 0, &link, sizeof(link)); |
4874322e | 1863 | } else { |
d55b4af9 | 1864 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
4874322e | 1865 | } |
83fc083c BS |
1866 | } |
1867 | ||
4cbb0f8d | 1868 | static void |
e84a35a8 | 1869 | nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) |
4cbb0f8d | 1870 | { |
e84a35a8 BS |
1871 | struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); |
1872 | u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; | |
1873 | if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { | |
648d4dfd | 1874 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
e84a35a8 BS |
1875 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
1876 | evo_data(push, (nv_encoder->ctrl = temp)); | |
1877 | } else { | |
1878 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); | |
1879 | evo_data(push, (nv_encoder->ctrl = temp)); | |
4cbb0f8d | 1880 | } |
e84a35a8 | 1881 | evo_kick(push, mast); |
4cbb0f8d | 1882 | } |
e84a35a8 BS |
1883 | } |
1884 | ||
1885 | static void | |
1886 | nv50_sor_disconnect(struct drm_encoder *encoder) | |
1887 | { | |
1888 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1889 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
419e8dc0 BS |
1890 | |
1891 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1892 | nv_encoder->crtc = NULL; | |
e84a35a8 BS |
1893 | |
1894 | if (nv_crtc) { | |
1895 | nv50_crtc_prepare(&nv_crtc->base); | |
1896 | nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0); | |
cc2a9071 | 1897 | nv50_audio_disconnect(encoder, nv_crtc); |
e84a35a8 BS |
1898 | nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc); |
1899 | } | |
4cbb0f8d BS |
1900 | } |
1901 | ||
83fc083c | 1902 | static void |
e225f446 | 1903 | nv50_sor_commit(struct drm_encoder *encoder) |
83fc083c BS |
1904 | { |
1905 | } | |
1906 | ||
1907 | static void | |
e225f446 | 1908 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
3b6d83d1 | 1909 | struct drm_display_mode *mode) |
83fc083c | 1910 | { |
a3761fa2 BS |
1911 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1912 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1913 | struct { | |
1914 | struct nv50_disp_mthd_v1 base; | |
1915 | struct nv50_disp_sor_lvds_script_v0 lvds; | |
1916 | } lvds = { | |
1917 | .base.version = 1, | |
1918 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, | |
1919 | .base.hasht = nv_encoder->dcb->hasht, | |
1920 | .base.hashm = nv_encoder->dcb->hashm, | |
1921 | }; | |
e225f446 BS |
1922 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1923 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 1924 | struct drm_device *dev = encoder->dev; |
77145f1c | 1925 | struct nouveau_drm *drm = nouveau_drm(dev); |
3b6d83d1 | 1926 | struct nouveau_connector *nv_connector; |
77145f1c | 1927 | struct nvbios *bios = &drm->vbios; |
a3761fa2 | 1928 | u32 mask, ctrl; |
419e8dc0 BS |
1929 | u8 owner = 1 << nv_crtc->index; |
1930 | u8 proto = 0xf; | |
1931 | u8 depth = 0x0; | |
83fc083c | 1932 | |
3b6d83d1 | 1933 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
e84a35a8 BS |
1934 | nv_encoder->crtc = encoder->crtc; |
1935 | ||
3b6d83d1 | 1936 | switch (nv_encoder->dcb->type) { |
cb75d97e | 1937 | case DCB_OUTPUT_TMDS: |
3b6d83d1 BS |
1938 | if (nv_encoder->dcb->sorconf.link & 1) { |
1939 | if (mode->clock < 165000) | |
419e8dc0 | 1940 | proto = 0x1; |
3b6d83d1 | 1941 | else |
419e8dc0 | 1942 | proto = 0x5; |
3b6d83d1 | 1943 | } else { |
419e8dc0 | 1944 | proto = 0x2; |
3b6d83d1 BS |
1945 | } |
1946 | ||
e84a35a8 | 1947 | nv50_hdmi_mode_set(&nv_encoder->base.base, mode); |
3b6d83d1 | 1948 | break; |
cb75d97e | 1949 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
1950 | proto = 0x0; |
1951 | ||
3b6d83d1 BS |
1952 | if (bios->fp_no_ddc) { |
1953 | if (bios->fp.dual_link) | |
a3761fa2 | 1954 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1955 | if (bios->fp.if_is_24bit) |
a3761fa2 | 1956 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 1957 | } else { |
befb51e9 | 1958 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 1959 | if (((u8 *)nv_connector->edid)[121] == 2) |
a3761fa2 | 1960 | lvds.lvds.script |= 0x0100; |
3b6d83d1 BS |
1961 | } else |
1962 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
a3761fa2 | 1963 | lvds.lvds.script |= 0x0100; |
3b6d83d1 | 1964 | } |
83fc083c | 1965 | |
a3761fa2 | 1966 | if (lvds.lvds.script & 0x0100) { |
3b6d83d1 | 1967 | if (bios->fp.strapless_is_24bit & 2) |
a3761fa2 | 1968 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1969 | } else { |
1970 | if (bios->fp.strapless_is_24bit & 1) | |
a3761fa2 | 1971 | lvds.lvds.script |= 0x0200; |
3b6d83d1 BS |
1972 | } |
1973 | ||
1974 | if (nv_connector->base.display_info.bpc == 8) | |
a3761fa2 | 1975 | lvds.lvds.script |= 0x0200; |
3b6d83d1 | 1976 | } |
4a230fa6 | 1977 | |
a3761fa2 | 1978 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
3b6d83d1 | 1979 | break; |
cb75d97e | 1980 | case DCB_OUTPUT_DP: |
3488c57b | 1981 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 1982 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
419e8dc0 | 1983 | depth = 0x2; |
bf2c886a BS |
1984 | } else |
1985 | if (nv_connector->base.display_info.bpc == 8) { | |
6e83fda2 | 1986 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
419e8dc0 | 1987 | depth = 0x5; |
bf2c886a BS |
1988 | } else { |
1989 | nv_encoder->dp.datarate = mode->clock * 30 / 8; | |
1990 | depth = 0x6; | |
3488c57b | 1991 | } |
6e83fda2 BS |
1992 | |
1993 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 1994 | proto = 0x8; |
6e83fda2 | 1995 | else |
419e8dc0 | 1996 | proto = 0x9; |
3eee8646 | 1997 | nv50_audio_mode_set(encoder, mode); |
6e83fda2 | 1998 | break; |
3b6d83d1 BS |
1999 | default: |
2000 | BUG_ON(1); | |
2001 | break; | |
2002 | } | |
ff8ff503 | 2003 | |
e84a35a8 | 2004 | nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON); |
83fc083c | 2005 | |
648d4dfd | 2006 | if (nv50_vers(mast) >= GF110_DISP) { |
e84a35a8 BS |
2007 | u32 *push = evo_wait(mast, 3); |
2008 | if (push) { | |
419e8dc0 BS |
2009 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
2010 | u32 syncs = 0x00000001; | |
2011 | ||
2012 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2013 | syncs |= 0x00000008; | |
2014 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2015 | syncs |= 0x00000010; | |
2016 | ||
2017 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
2018 | magic |= 0x00000001; | |
2019 | ||
2020 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
2021 | evo_data(push, syncs | (depth << 6)); | |
2022 | evo_data(push, magic); | |
e84a35a8 | 2023 | evo_kick(push, mast); |
419e8dc0 BS |
2024 | } |
2025 | ||
e84a35a8 BS |
2026 | ctrl = proto << 8; |
2027 | mask = 0x00000f00; | |
2028 | } else { | |
2029 | ctrl = (depth << 16) | (proto << 8); | |
2030 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2031 | ctrl |= 0x00001000; | |
2032 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2033 | ctrl |= 0x00002000; | |
2034 | mask = 0x000f3f00; | |
83fc083c BS |
2035 | } |
2036 | ||
e84a35a8 | 2037 | nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner); |
83fc083c BS |
2038 | } |
2039 | ||
83fc083c | 2040 | static void |
e225f446 | 2041 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c BS |
2042 | { |
2043 | drm_encoder_cleanup(encoder); | |
2044 | kfree(encoder); | |
2045 | } | |
2046 | ||
e225f446 BS |
2047 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
2048 | .dpms = nv50_sor_dpms, | |
a91d3221 | 2049 | .mode_fixup = nv50_encoder_mode_fixup, |
5a885f0b | 2050 | .prepare = nv50_sor_disconnect, |
e225f446 BS |
2051 | .commit = nv50_sor_commit, |
2052 | .mode_set = nv50_sor_mode_set, | |
2053 | .disable = nv50_sor_disconnect, | |
2054 | .get_crtc = nv50_display_crtc_get, | |
83fc083c BS |
2055 | }; |
2056 | ||
e225f446 BS |
2057 | static const struct drm_encoder_funcs nv50_sor_func = { |
2058 | .destroy = nv50_sor_destroy, | |
83fc083c BS |
2059 | }; |
2060 | ||
2061 | static int | |
e225f446 | 2062 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 2063 | { |
5ed50209 | 2064 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
be83cd4e | 2065 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
83fc083c BS |
2066 | struct nouveau_encoder *nv_encoder; |
2067 | struct drm_encoder *encoder; | |
5ed50209 BS |
2068 | int type; |
2069 | ||
2070 | switch (dcbe->type) { | |
2071 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
2072 | case DCB_OUTPUT_TMDS: | |
2073 | case DCB_OUTPUT_DP: | |
2074 | default: | |
2075 | type = DRM_MODE_ENCODER_TMDS; | |
2076 | break; | |
2077 | } | |
83fc083c BS |
2078 | |
2079 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2080 | if (!nv_encoder) | |
2081 | return -ENOMEM; | |
2082 | nv_encoder->dcb = dcbe; | |
2083 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 2084 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
83fc083c BS |
2085 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
2086 | ||
2087 | encoder = to_drm_encoder(nv_encoder); | |
2088 | encoder->possible_crtcs = dcbe->heads; | |
2089 | encoder->possible_clones = 0; | |
5ed50209 | 2090 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
e225f446 | 2091 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
83fc083c BS |
2092 | |
2093 | drm_mode_connector_attach_encoder(connector, encoder); | |
2094 | return 0; | |
2095 | } | |
26f6d88b | 2096 | |
eb6313ad BS |
2097 | /****************************************************************************** |
2098 | * PIOR | |
2099 | *****************************************************************************/ | |
2100 | ||
2101 | static void | |
2102 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
2103 | { | |
2104 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2105 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
67cb49c4 BS |
2106 | struct { |
2107 | struct nv50_disp_mthd_v1 base; | |
2108 | struct nv50_disp_pior_pwr_v0 pwr; | |
2109 | } args = { | |
2110 | .base.version = 1, | |
2111 | .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, | |
2112 | .base.hasht = nv_encoder->dcb->hasht, | |
2113 | .base.hashm = nv_encoder->dcb->hashm, | |
2114 | .pwr.state = mode == DRM_MODE_DPMS_ON, | |
2115 | .pwr.type = nv_encoder->dcb->type, | |
2116 | }; | |
2117 | ||
2118 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); | |
eb6313ad BS |
2119 | } |
2120 | ||
2121 | static bool | |
2122 | nv50_pior_mode_fixup(struct drm_encoder *encoder, | |
2123 | const struct drm_display_mode *mode, | |
2124 | struct drm_display_mode *adjusted_mode) | |
2125 | { | |
a91d3221 BS |
2126 | if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode)) |
2127 | return false; | |
eb6313ad BS |
2128 | adjusted_mode->clock *= 2; |
2129 | return true; | |
2130 | } | |
2131 | ||
2132 | static void | |
2133 | nv50_pior_commit(struct drm_encoder *encoder) | |
2134 | { | |
2135 | } | |
2136 | ||
2137 | static void | |
2138 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
2139 | struct drm_display_mode *adjusted_mode) | |
2140 | { | |
2141 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2142 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2143 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
2144 | struct nouveau_connector *nv_connector; | |
2145 | u8 owner = 1 << nv_crtc->index; | |
2146 | u8 proto, depth; | |
2147 | u32 *push; | |
2148 | ||
2149 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2150 | switch (nv_connector->base.display_info.bpc) { | |
2151 | case 10: depth = 0x6; break; | |
2152 | case 8: depth = 0x5; break; | |
2153 | case 6: depth = 0x2; break; | |
2154 | default: depth = 0x0; break; | |
2155 | } | |
2156 | ||
2157 | switch (nv_encoder->dcb->type) { | |
2158 | case DCB_OUTPUT_TMDS: | |
2159 | case DCB_OUTPUT_DP: | |
2160 | proto = 0x0; | |
2161 | break; | |
2162 | default: | |
2163 | BUG_ON(1); | |
2164 | break; | |
2165 | } | |
2166 | ||
2167 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); | |
2168 | ||
2169 | push = evo_wait(mast, 8); | |
2170 | if (push) { | |
648d4dfd | 2171 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2172 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
2173 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2174 | ctrl |= 0x00001000; | |
2175 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2176 | ctrl |= 0x00002000; | |
2177 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
2178 | evo_data(push, ctrl); | |
2179 | } | |
2180 | ||
2181 | evo_kick(push, mast); | |
2182 | } | |
2183 | ||
2184 | nv_encoder->crtc = encoder->crtc; | |
2185 | } | |
2186 | ||
2187 | static void | |
2188 | nv50_pior_disconnect(struct drm_encoder *encoder) | |
2189 | { | |
2190 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2191 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2192 | const int or = nv_encoder->or; | |
2193 | u32 *push; | |
2194 | ||
2195 | if (nv_encoder->crtc) { | |
2196 | nv50_crtc_prepare(nv_encoder->crtc); | |
2197 | ||
2198 | push = evo_wait(mast, 4); | |
2199 | if (push) { | |
648d4dfd | 2200 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
eb6313ad BS |
2201 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
2202 | evo_data(push, 0x00000000); | |
2203 | } | |
eb6313ad BS |
2204 | evo_kick(push, mast); |
2205 | } | |
2206 | } | |
2207 | ||
2208 | nv_encoder->crtc = NULL; | |
2209 | } | |
2210 | ||
2211 | static void | |
2212 | nv50_pior_destroy(struct drm_encoder *encoder) | |
2213 | { | |
2214 | drm_encoder_cleanup(encoder); | |
2215 | kfree(encoder); | |
2216 | } | |
2217 | ||
2218 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { | |
2219 | .dpms = nv50_pior_dpms, | |
2220 | .mode_fixup = nv50_pior_mode_fixup, | |
2221 | .prepare = nv50_pior_disconnect, | |
2222 | .commit = nv50_pior_commit, | |
2223 | .mode_set = nv50_pior_mode_set, | |
2224 | .disable = nv50_pior_disconnect, | |
2225 | .get_crtc = nv50_display_crtc_get, | |
2226 | }; | |
2227 | ||
2228 | static const struct drm_encoder_funcs nv50_pior_func = { | |
2229 | .destroy = nv50_pior_destroy, | |
2230 | }; | |
2231 | ||
2232 | static int | |
2233 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
2234 | { | |
2235 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
be83cd4e BS |
2236 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); |
2237 | struct nvkm_i2c_port *ddc = NULL; | |
eb6313ad BS |
2238 | struct nouveau_encoder *nv_encoder; |
2239 | struct drm_encoder *encoder; | |
2240 | int type; | |
2241 | ||
2242 | switch (dcbe->type) { | |
2243 | case DCB_OUTPUT_TMDS: | |
2244 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); | |
2245 | type = DRM_MODE_ENCODER_TMDS; | |
2246 | break; | |
2247 | case DCB_OUTPUT_DP: | |
2248 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); | |
2249 | type = DRM_MODE_ENCODER_TMDS; | |
2250 | break; | |
2251 | default: | |
2252 | return -ENODEV; | |
2253 | } | |
2254 | ||
2255 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2256 | if (!nv_encoder) | |
2257 | return -ENOMEM; | |
2258 | nv_encoder->dcb = dcbe; | |
2259 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2260 | nv_encoder->i2c = ddc; | |
2261 | ||
2262 | encoder = to_drm_encoder(nv_encoder); | |
2263 | encoder->possible_crtcs = dcbe->heads; | |
2264 | encoder->possible_clones = 0; | |
2265 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); | |
2266 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); | |
2267 | ||
2268 | drm_mode_connector_attach_encoder(connector, encoder); | |
2269 | return 0; | |
2270 | } | |
2271 | ||
ab0af559 BS |
2272 | /****************************************************************************** |
2273 | * Framebuffer | |
2274 | *****************************************************************************/ | |
2275 | ||
8a423647 | 2276 | static void |
0ad72863 | 2277 | nv50_fbdma_fini(struct nv50_fbdma *fbdma) |
8a423647 | 2278 | { |
0ad72863 BS |
2279 | int i; |
2280 | for (i = 0; i < ARRAY_SIZE(fbdma->base); i++) | |
2281 | nvif_object_fini(&fbdma->base[i]); | |
2282 | nvif_object_fini(&fbdma->core); | |
8a423647 BS |
2283 | list_del(&fbdma->head); |
2284 | kfree(fbdma); | |
2285 | } | |
2286 | ||
2287 | static int | |
2288 | nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind) | |
2289 | { | |
2290 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2291 | struct nv50_disp *disp = nv50_disp(dev); | |
2292 | struct nv50_mast *mast = nv50_mast(dev); | |
4acfd707 BS |
2293 | struct __attribute__ ((packed)) { |
2294 | struct nv_dma_v0 base; | |
2295 | union { | |
2296 | struct nv50_dma_v0 nv50; | |
2297 | struct gf100_dma_v0 gf100; | |
2298 | struct gf110_dma_v0 gf110; | |
2299 | }; | |
2300 | } args = {}; | |
8a423647 BS |
2301 | struct nv50_fbdma *fbdma; |
2302 | struct drm_crtc *crtc; | |
4acfd707 | 2303 | u32 size = sizeof(args.base); |
8a423647 BS |
2304 | int ret; |
2305 | ||
2306 | list_for_each_entry(fbdma, &disp->fbdma, head) { | |
0ad72863 | 2307 | if (fbdma->core.handle == name) |
8a423647 BS |
2308 | return 0; |
2309 | } | |
2310 | ||
2311 | fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL); | |
2312 | if (!fbdma) | |
2313 | return -ENOMEM; | |
2314 | list_add(&fbdma->head, &disp->fbdma); | |
8a423647 | 2315 | |
4acfd707 BS |
2316 | args.base.target = NV_DMA_V0_TARGET_VRAM; |
2317 | args.base.access = NV_DMA_V0_ACCESS_RDWR; | |
2318 | args.base.start = offset; | |
2319 | args.base.limit = offset + length - 1; | |
8a423647 | 2320 | |
967e7bde | 2321 | if (drm->device.info.chipset < 0x80) { |
4acfd707 BS |
2322 | args.nv50.part = NV50_DMA_V0_PART_256; |
2323 | size += sizeof(args.nv50); | |
8a423647 | 2324 | } else |
967e7bde | 2325 | if (drm->device.info.chipset < 0xc0) { |
4acfd707 BS |
2326 | args.nv50.part = NV50_DMA_V0_PART_256; |
2327 | args.nv50.kind = kind; | |
2328 | size += sizeof(args.nv50); | |
8a423647 | 2329 | } else |
967e7bde | 2330 | if (drm->device.info.chipset < 0xd0) { |
4acfd707 BS |
2331 | args.gf100.kind = kind; |
2332 | size += sizeof(args.gf100); | |
8a423647 | 2333 | } else { |
4acfd707 BS |
2334 | args.gf110.page = GF110_DMA_V0_PAGE_LP; |
2335 | args.gf110.kind = kind; | |
2336 | size += sizeof(args.gf110); | |
8a423647 BS |
2337 | } |
2338 | ||
2339 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
0ad72863 BS |
2340 | struct nv50_head *head = nv50_head(crtc); |
2341 | int ret = nvif_object_init(&head->sync.base.base.user, NULL, | |
4acfd707 | 2342 | name, NV_DMA_IN_MEMORY, &args, size, |
0ad72863 | 2343 | &fbdma->base[head->base.index]); |
8a423647 | 2344 | if (ret) { |
0ad72863 | 2345 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2346 | return ret; |
2347 | } | |
2348 | } | |
2349 | ||
0ad72863 | 2350 | ret = nvif_object_init(&mast->base.base.user, NULL, name, |
4acfd707 | 2351 | NV_DMA_IN_MEMORY, &args, size, |
0ad72863 | 2352 | &fbdma->core); |
8a423647 | 2353 | if (ret) { |
0ad72863 | 2354 | nv50_fbdma_fini(fbdma); |
8a423647 BS |
2355 | return ret; |
2356 | } | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
ab0af559 BS |
2361 | static void |
2362 | nv50_fb_dtor(struct drm_framebuffer *fb) | |
2363 | { | |
2364 | } | |
2365 | ||
2366 | static int | |
2367 | nv50_fb_ctor(struct drm_framebuffer *fb) | |
2368 | { | |
2369 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
2370 | struct nouveau_drm *drm = nouveau_drm(fb->dev); | |
2371 | struct nouveau_bo *nvbo = nv_fb->nvbo; | |
8a423647 | 2372 | struct nv50_disp *disp = nv50_disp(fb->dev); |
8a423647 BS |
2373 | u8 kind = nouveau_bo_tile_layout(nvbo) >> 8; |
2374 | u8 tile = nvbo->tile_mode; | |
ab0af559 | 2375 | |
967e7bde | 2376 | if (drm->device.info.chipset >= 0xc0) |
8a423647 BS |
2377 | tile >>= 4; /* yep.. */ |
2378 | ||
ab0af559 BS |
2379 | switch (fb->depth) { |
2380 | case 8: nv_fb->r_format = 0x1e00; break; | |
2381 | case 15: nv_fb->r_format = 0xe900; break; | |
2382 | case 16: nv_fb->r_format = 0xe800; break; | |
2383 | case 24: | |
2384 | case 32: nv_fb->r_format = 0xcf00; break; | |
2385 | case 30: nv_fb->r_format = 0xd100; break; | |
2386 | default: | |
2387 | NV_ERROR(drm, "unknown depth %d\n", fb->depth); | |
2388 | return -EINVAL; | |
2389 | } | |
2390 | ||
648d4dfd | 2391 | if (disp->disp->oclass < G82_DISP) { |
8a423647 BS |
2392 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2393 | (fb->pitches[0] | 0x00100000); | |
2394 | nv_fb->r_format |= kind << 16; | |
2395 | } else | |
648d4dfd | 2396 | if (disp->disp->oclass < GF110_DISP) { |
8a423647 BS |
2397 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2398 | (fb->pitches[0] | 0x00100000); | |
ab0af559 | 2399 | } else { |
8a423647 BS |
2400 | nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : |
2401 | (fb->pitches[0] | 0x01000000); | |
ab0af559 | 2402 | } |
8a423647 | 2403 | nv_fb->r_handle = 0xffff0000 | kind; |
ab0af559 | 2404 | |
f392ec4b BS |
2405 | return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0, |
2406 | drm->device.info.ram_user, kind); | |
ab0af559 BS |
2407 | } |
2408 | ||
26f6d88b BS |
2409 | /****************************************************************************** |
2410 | * Init | |
2411 | *****************************************************************************/ | |
ab0af559 | 2412 | |
2a44e499 | 2413 | void |
e225f446 | 2414 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 2415 | { |
26f6d88b BS |
2416 | } |
2417 | ||
2418 | int | |
e225f446 | 2419 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 2420 | { |
9f9bdaaf BS |
2421 | struct nv50_disp *disp = nv50_disp(dev); |
2422 | struct drm_crtc *crtc; | |
2423 | u32 *push; | |
2424 | ||
2425 | push = evo_wait(nv50_mast(dev), 32); | |
2426 | if (!push) | |
2427 | return -EBUSY; | |
2428 | ||
2429 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2430 | struct nv50_sync *sync = nv50_sync(crtc); | |
4dc63933 ML |
2431 | |
2432 | nv50_crtc_lut_load(crtc); | |
9f9bdaaf | 2433 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); |
bdb8c212 | 2434 | } |
efd272a7 | 2435 | |
9f9bdaaf | 2436 | evo_mthd(push, 0x0088, 1); |
f45f55c4 | 2437 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
9f9bdaaf BS |
2438 | evo_kick(push, nv50_mast(dev)); |
2439 | return 0; | |
26f6d88b BS |
2440 | } |
2441 | ||
2442 | void | |
e225f446 | 2443 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 2444 | { |
e225f446 | 2445 | struct nv50_disp *disp = nv50_disp(dev); |
8a423647 BS |
2446 | struct nv50_fbdma *fbdma, *fbtmp; |
2447 | ||
2448 | list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) { | |
0ad72863 | 2449 | nv50_fbdma_fini(fbdma); |
8a423647 | 2450 | } |
bdb8c212 | 2451 | |
0ad72863 | 2452 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
26f6d88b | 2453 | |
816af2f2 | 2454 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
2455 | if (disp->sync) |
2456 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 2457 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 2458 | |
77145f1c | 2459 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
2460 | kfree(disp); |
2461 | } | |
2462 | ||
2463 | int | |
e225f446 | 2464 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 2465 | { |
967e7bde | 2466 | struct nvif_device *device = &nouveau_drm(dev)->device; |
77145f1c | 2467 | struct nouveau_drm *drm = nouveau_drm(dev); |
77145f1c | 2468 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 2469 | struct drm_connector *connector, *tmp; |
e225f446 | 2470 | struct nv50_disp *disp; |
cb75d97e | 2471 | struct dcb_output *dcbe; |
7c5f6a87 | 2472 | int crtcs, ret, i; |
26f6d88b BS |
2473 | |
2474 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
2475 | if (!disp) | |
2476 | return -ENOMEM; | |
8a423647 | 2477 | INIT_LIST_HEAD(&disp->fbdma); |
77145f1c BS |
2478 | |
2479 | nouveau_display(dev)->priv = disp; | |
e225f446 BS |
2480 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2481 | nouveau_display(dev)->init = nv50_display_init; | |
2482 | nouveau_display(dev)->fini = nv50_display_fini; | |
ab0af559 BS |
2483 | nouveau_display(dev)->fb_ctor = nv50_fb_ctor; |
2484 | nouveau_display(dev)->fb_dtor = nv50_fb_dtor; | |
0ad72863 | 2485 | disp->disp = &nouveau_display(dev)->disp; |
26f6d88b | 2486 | |
b5a794b0 BS |
2487 | /* small shared memory area we use for notifiers and semaphores */ |
2488 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
bb6178b0 | 2489 | 0, 0x0000, NULL, NULL, &disp->sync); |
b5a794b0 | 2490 | if (!ret) { |
547ad072 | 2491 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); |
04c8c210 | 2492 | if (!ret) { |
b5a794b0 | 2493 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
2494 | if (ret) |
2495 | nouveau_bo_unpin(disp->sync); | |
2496 | } | |
b5a794b0 BS |
2497 | if (ret) |
2498 | nouveau_bo_ref(NULL, &disp->sync); | |
2499 | } | |
2500 | ||
b5a794b0 BS |
2501 | if (ret) |
2502 | goto out; | |
2503 | ||
2504 | /* allocate master evo channel */ | |
410f3ec6 BS |
2505 | ret = nv50_core_create(disp->disp, disp->sync->bo.offset, |
2506 | &disp->mast); | |
b5a794b0 BS |
2507 | if (ret) |
2508 | goto out; | |
2509 | ||
438d99e3 | 2510 | /* create crtc objects to represent the hw heads */ |
648d4dfd | 2511 | if (disp->disp->oclass >= GF110_DISP) |
db2bec18 | 2512 | crtcs = nvif_rd32(device, 0x022448); |
63718a07 BS |
2513 | else |
2514 | crtcs = 2; | |
2515 | ||
7c5f6a87 | 2516 | for (i = 0; i < crtcs; i++) { |
0ad72863 | 2517 | ret = nv50_crtc_create(dev, i); |
438d99e3 BS |
2518 | if (ret) |
2519 | goto out; | |
2520 | } | |
2521 | ||
83fc083c BS |
2522 | /* create encoder/connector objects based on VBIOS DCB table */ |
2523 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
2524 | connector = nouveau_connector_create(dev, dcbe->connector); | |
2525 | if (IS_ERR(connector)) | |
2526 | continue; | |
2527 | ||
eb6313ad BS |
2528 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2529 | switch (dcbe->type) { | |
2530 | case DCB_OUTPUT_TMDS: | |
2531 | case DCB_OUTPUT_LVDS: | |
2532 | case DCB_OUTPUT_DP: | |
2533 | ret = nv50_sor_create(connector, dcbe); | |
2534 | break; | |
2535 | case DCB_OUTPUT_ANALOG: | |
2536 | ret = nv50_dac_create(connector, dcbe); | |
2537 | break; | |
2538 | default: | |
2539 | ret = -ENODEV; | |
2540 | break; | |
2541 | } | |
2542 | } else { | |
2543 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
2544 | } |
2545 | ||
eb6313ad BS |
2546 | if (ret) { |
2547 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
2548 | dcbe->location, dcbe->type, | |
2549 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 2550 | ret = 0; |
83fc083c BS |
2551 | } |
2552 | } | |
2553 | ||
2554 | /* cull any connectors we created that don't have an encoder */ | |
2555 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2556 | if (connector->encoder_ids[0]) | |
2557 | continue; | |
2558 | ||
77145f1c | 2559 | NV_WARN(drm, "%s has no encoders, removing\n", |
8c6c361a | 2560 | connector->name); |
83fc083c BS |
2561 | connector->funcs->destroy(connector); |
2562 | } | |
2563 | ||
26f6d88b BS |
2564 | out: |
2565 | if (ret) | |
e225f446 | 2566 | nv50_display_destroy(dev); |
26f6d88b BS |
2567 | return ret; |
2568 | } |