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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
ebb945a9 BS |
25 | #include <core/object.h> |
26 | #include <core/class.h> | |
27 | ||
28 | #include "nouveau_drm.h" | |
f589be88 | 29 | #include "nouveau_dma.h" |
f589be88 | 30 | #include "nouveau_fence.h" |
f589be88 | 31 | |
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32 | #include "nv50_display.h" |
33 | ||
f589be88 BS |
34 | struct nv50_fence_chan { |
35 | struct nouveau_fence_chan base; | |
36 | }; | |
37 | ||
38 | struct nv50_fence_priv { | |
39 | struct nouveau_fence_priv base; | |
40 | struct nouveau_bo *bo; | |
41 | spinlock_t lock; | |
42 | u32 sequence; | |
43 | }; | |
44 | ||
45 | static int | |
46 | nv50_fence_context_new(struct nouveau_channel *chan) | |
47 | { | |
77145f1c | 48 | struct drm_device *dev = chan->drm->dev; |
ebb945a9 | 49 | struct nv50_fence_priv *priv = chan->drm->fence; |
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50 | struct nv50_fence_chan *fctx; |
51 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; | |
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52 | struct nouveau_object *object; |
53 | int ret, i; | |
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54 | |
55 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
56 | if (!fctx) | |
57 | return -ENOMEM; | |
58 | ||
59 | nouveau_fence_context_new(&fctx->base); | |
60 | ||
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61 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, |
62 | NvSema, 0x0002, | |
63 | &(struct nv_dma_class) { | |
64 | .flags = NV_DMA_TARGET_VRAM | | |
65 | NV_DMA_ACCESS_RDWR, | |
66 | .start = mem->start * PAGE_SIZE, | |
67 | .limit = mem->size - 1, | |
68 | }, sizeof(struct nv_dma_class), | |
69 | &object); | |
f589be88 BS |
70 | |
71 | /* dma objects for display sync channel semaphore blocks */ | |
77145f1c | 72 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { |
e225f446 | 73 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); |
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74 | |
75 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | |
76 | NvEvoSema0 + i, 0x003d, | |
77 | &(struct nv_dma_class) { | |
78 | .flags = NV_DMA_TARGET_VRAM | | |
79 | NV_DMA_ACCESS_RDWR, | |
80 | .start = bo->bo.offset, | |
81 | .limit = bo->bo.offset + 0xfff, | |
82 | }, sizeof(struct nv_dma_class), | |
83 | &object); | |
f589be88 BS |
84 | } |
85 | ||
86 | if (ret) | |
87 | nv10_fence_context_del(chan); | |
88 | return ret; | |
89 | } | |
90 | ||
91 | int | |
ebb945a9 | 92 | nv50_fence_create(struct nouveau_drm *drm) |
f589be88 | 93 | { |
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94 | struct nv50_fence_priv *priv; |
95 | int ret = 0; | |
96 | ||
ebb945a9 | 97 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
f589be88 BS |
98 | if (!priv) |
99 | return -ENOMEM; | |
100 | ||
101 | priv->base.dtor = nv10_fence_destroy; | |
102 | priv->base.context_new = nv50_fence_context_new; | |
103 | priv->base.context_del = nv10_fence_context_del; | |
104 | priv->base.emit = nv10_fence_emit; | |
105 | priv->base.read = nv10_fence_read; | |
106 | priv->base.sync = nv17_fence_sync; | |
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107 | spin_lock_init(&priv->lock); |
108 | ||
ebb945a9 | 109 | ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
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110 | 0, 0x0000, NULL, &priv->bo); |
111 | if (!ret) { | |
112 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); | |
04c8c210 | 113 | if (!ret) { |
f589be88 | 114 | ret = nouveau_bo_map(priv->bo); |
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115 | if (ret) |
116 | nouveau_bo_unpin(priv->bo); | |
117 | } | |
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118 | if (ret) |
119 | nouveau_bo_ref(NULL, &priv->bo); | |
120 | } | |
121 | ||
ebb945a9 | 122 | if (ret == 0) { |
f589be88 | 123 | nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); |
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124 | priv->base.sync = nv17_fence_sync; |
125 | } | |
126 | ||
127 | if (ret) | |
128 | nv10_fence_destroy(drm); | |
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129 | return ret; |
130 | } |