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f589be88 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
fdb751ef BS |
25 | #include <nvif/os.h> |
26 | #include <nvif/class.h> | |
ebb945a9 BS |
27 | |
28 | #include "nouveau_drm.h" | |
f589be88 | 29 | #include "nouveau_dma.h" |
a4cea27b | 30 | #include "nv10_fence.h" |
f589be88 | 31 | |
77145f1c BS |
32 | #include "nv50_display.h" |
33 | ||
f589be88 BS |
34 | static int |
35 | nv50_fence_context_new(struct nouveau_channel *chan) | |
36 | { | |
77145f1c | 37 | struct drm_device *dev = chan->drm->dev; |
a4cea27b MS |
38 | struct nv10_fence_priv *priv = chan->drm->fence; |
39 | struct nv10_fence_chan *fctx; | |
f589be88 | 40 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; |
7a7da592 ML |
41 | u32 start = mem->start * PAGE_SIZE; |
42 | u32 limit = start + mem->size - 1; | |
ebb945a9 | 43 | int ret, i; |
f589be88 BS |
44 | |
45 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
46 | if (!fctx) | |
47 | return -ENOMEM; | |
48 | ||
29ba89b2 | 49 | nouveau_fence_context_new(chan, &fctx->base); |
827520ce BS |
50 | fctx->base.emit = nv10_fence_emit; |
51 | fctx->base.read = nv10_fence_read; | |
52 | fctx->base.sync = nv17_fence_sync; | |
f589be88 | 53 | |
4acfd707 BS |
54 | ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY, |
55 | &(struct nv_dma_v0) { | |
56 | .target = NV_DMA_V0_TARGET_VRAM, | |
57 | .access = NV_DMA_V0_ACCESS_RDWR, | |
7a7da592 ML |
58 | .start = start, |
59 | .limit = limit, | |
4acfd707 | 60 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 61 | &fctx->sema); |
f589be88 BS |
62 | |
63 | /* dma objects for display sync channel semaphore blocks */ | |
77145f1c | 64 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { |
e225f446 | 65 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); |
7a7da592 ML |
66 | u32 start = bo->bo.mem.start * PAGE_SIZE; |
67 | u32 limit = start + bo->bo.mem.size - 1; | |
ebb945a9 | 68 | |
0ad72863 | 69 | ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i, |
4acfd707 BS |
70 | NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { |
71 | .target = NV_DMA_V0_TARGET_VRAM, | |
72 | .access = NV_DMA_V0_ACCESS_RDWR, | |
7a7da592 ML |
73 | .start = start, |
74 | .limit = limit, | |
4acfd707 | 75 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 76 | &fctx->head[i]); |
f589be88 BS |
77 | } |
78 | ||
79 | if (ret) | |
80 | nv10_fence_context_del(chan); | |
81 | return ret; | |
82 | } | |
83 | ||
84 | int | |
ebb945a9 | 85 | nv50_fence_create(struct nouveau_drm *drm) |
f589be88 | 86 | { |
a4cea27b | 87 | struct nv10_fence_priv *priv; |
f589be88 BS |
88 | int ret = 0; |
89 | ||
ebb945a9 | 90 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
f589be88 BS |
91 | if (!priv) |
92 | return -ENOMEM; | |
93 | ||
94 | priv->base.dtor = nv10_fence_destroy; | |
827520ce | 95 | priv->base.resume = nv17_fence_resume; |
f589be88 BS |
96 | priv->base.context_new = nv50_fence_context_new; |
97 | priv->base.context_del = nv10_fence_context_del; | |
29ba89b2 ML |
98 | priv->base.contexts = 127; |
99 | priv->base.context_base = fence_context_alloc(priv->base.contexts); | |
f589be88 BS |
100 | spin_lock_init(&priv->lock); |
101 | ||
ebb945a9 | 102 | ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
bb6178b0 | 103 | 0, 0x0000, NULL, NULL, &priv->bo); |
f589be88 | 104 | if (!ret) { |
ad76b3f7 | 105 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); |
04c8c210 | 106 | if (!ret) { |
f589be88 | 107 | ret = nouveau_bo_map(priv->bo); |
04c8c210 MS |
108 | if (ret) |
109 | nouveau_bo_unpin(priv->bo); | |
110 | } | |
f589be88 BS |
111 | if (ret) |
112 | nouveau_bo_ref(NULL, &priv->bo); | |
113 | } | |
114 | ||
827520ce BS |
115 | if (ret) { |
116 | nv10_fence_destroy(drm); | |
117 | return ret; | |
ebb945a9 BS |
118 | } |
119 | ||
827520ce | 120 | nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); |
f589be88 BS |
121 | return ret; |
122 | } |