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6ee73861 | 1 | /* |
c420b2dc | 2 | * Copyright (C) 2012 Ben Skeggs. |
6ee73861 BS |
3 | * All Rights Reserved. |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
760285e7 | 27 | #include <drm/drmP.h> |
6ee73861 | 28 | #include "nouveau_drv.h" |
c420b2dc | 29 | #include "nouveau_fifo.h" |
a8eaebc6 | 30 | #include "nouveau_ramht.h" |
a11c3198 | 31 | #include "nouveau_vm.h" |
6ee73861 | 32 | |
c420b2dc BS |
33 | struct nv50_fifo_priv { |
34 | struct nouveau_fifo_priv base; | |
35 | struct nouveau_gpuobj *playlist[2]; | |
36 | int cur_playlist; | |
37 | }; | |
38 | ||
39 | struct nv50_fifo_chan { | |
40 | struct nouveau_fifo_chan base; | |
41 | }; | |
42 | ||
43 | void | |
ac94a343 | 44 | nv50_fifo_playlist_update(struct drm_device *dev) |
6ee73861 | 45 | { |
c420b2dc | 46 | struct nv50_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO); |
6ee73861 | 47 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
a8eaebc6 | 48 | struct nouveau_gpuobj *cur; |
694931d2 | 49 | int i, p; |
6ee73861 | 50 | |
c420b2dc BS |
51 | cur = priv->playlist[priv->cur_playlist]; |
52 | priv->cur_playlist = !priv->cur_playlist; | |
6ee73861 | 53 | |
c420b2dc | 54 | for (i = 0, p = 0; i < priv->base.channels; i++) { |
694931d2 BS |
55 | if (nv_rd32(dev, 0x002600 + (i * 4)) & 0x80000000) |
56 | nv_wo32(cur, p++ * 4, i); | |
6ee73861 | 57 | } |
694931d2 | 58 | |
f56cb86f | 59 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 60 | |
c420b2dc BS |
61 | nv_wr32(dev, 0x0032f4, cur->vinst >> 12); |
62 | nv_wr32(dev, 0x0032ec, p); | |
63 | nv_wr32(dev, 0x002500, 0x00000101); | |
6ee73861 BS |
64 | } |
65 | ||
c420b2dc BS |
66 | static int |
67 | nv50_fifo_context_new(struct nouveau_channel *chan, int engine) | |
6ee73861 | 68 | { |
c420b2dc BS |
69 | struct nv50_fifo_priv *priv = nv_engine(chan->dev, engine); |
70 | struct nv50_fifo_chan *fctx; | |
6ee73861 BS |
71 | struct drm_device *dev = chan->dev; |
72 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c420b2dc BS |
73 | u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4; |
74 | u64 instance = chan->ramin->vinst >> 12; | |
ff9e5279 | 75 | unsigned long flags; |
c420b2dc | 76 | int ret = 0, i; |
6ee73861 | 77 | |
c420b2dc BS |
78 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); |
79 | if (!fctx) | |
80 | return -ENOMEM; | |
81 | atomic_inc(&chan->vm->engref[engine]); | |
6ee73861 | 82 | |
d908175c BS |
83 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + |
84 | NV50_USER(chan->id), PAGE_SIZE); | |
c420b2dc BS |
85 | if (!chan->user) { |
86 | ret = -ENOMEM; | |
87 | goto error; | |
6ee73861 BS |
88 | } |
89 | ||
c420b2dc BS |
90 | for (i = 0; i < 0x100; i += 4) |
91 | nv_wo32(chan->ramin, i, 0x00000000); | |
92 | nv_wo32(chan->ramin, 0x3c, 0x403f6078); | |
93 | nv_wo32(chan->ramin, 0x40, 0x00000000); | |
94 | nv_wo32(chan->ramin, 0x44, 0x01003fff); | |
95 | nv_wo32(chan->ramin, 0x48, chan->pushbuf->cinst >> 4); | |
96 | nv_wo32(chan->ramin, 0x50, lower_32_bits(ib_offset)); | |
97 | nv_wo32(chan->ramin, 0x54, upper_32_bits(ib_offset) | | |
98 | drm_order(chan->dma.ib_max + 1) << 16); | |
99 | nv_wo32(chan->ramin, 0x60, 0x7fffffff); | |
100 | nv_wo32(chan->ramin, 0x78, 0x00000000); | |
101 | nv_wo32(chan->ramin, 0x7c, 0x30000001); | |
102 | nv_wo32(chan->ramin, 0x80, ((chan->ramht->bits - 9) << 27) | | |
103 | (4 << 24) /* SEARCH_FULL */ | | |
104 | (chan->ramht->gpuobj->cinst >> 4)); | |
105 | ||
f56cb86f | 106 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 107 | |
c420b2dc BS |
108 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
109 | nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance); | |
ac94a343 | 110 | nv50_fifo_playlist_update(dev); |
ff9e5279 | 111 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
c420b2dc BS |
112 | |
113 | error: | |
114 | if (ret) | |
115 | priv->base.base.context_del(chan, engine); | |
116 | return ret; | |
6ee73861 BS |
117 | } |
118 | ||
03bd6efa | 119 | static bool |
c420b2dc | 120 | nv50_fifo_kickoff(struct nouveau_channel *chan) |
03bd6efa | 121 | { |
c420b2dc BS |
122 | struct drm_device *dev = chan->dev; |
123 | bool done = true; | |
124 | u32 me; | |
125 | ||
126 | /* HW bug workaround: | |
127 | * | |
128 | * PFIFO will hang forever if the connected engines don't report | |
129 | * that they've processed the context switch request. | |
130 | * | |
131 | * In order for the kickoff to work, we need to ensure all the | |
132 | * connected engines are in a state where they can answer. | |
133 | * | |
134 | * Newer chipsets don't seem to suffer from this issue, and well, | |
135 | * there's also a "ignore these engines" bitmask reg we can use | |
136 | * if we hit the issue there.. | |
137 | */ | |
138 | ||
139 | /* PME: make sure engine is enabled */ | |
140 | me = nv_mask(dev, 0x00b860, 0x00000001, 0x00000001); | |
141 | ||
142 | /* do the kickoff... */ | |
143 | nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12); | |
144 | if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) { | |
145 | NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id); | |
146 | done = false; | |
03bd6efa BS |
147 | } |
148 | ||
c420b2dc BS |
149 | /* restore any engine states we changed, and exit */ |
150 | nv_wr32(dev, 0x00b860, me); | |
151 | return done; | |
03bd6efa BS |
152 | } |
153 | ||
c420b2dc BS |
154 | static void |
155 | nv50_fifo_context_del(struct nouveau_channel *chan, int engine) | |
6ee73861 | 156 | { |
c420b2dc | 157 | struct nv50_fifo_chan *fctx = chan->engctx[engine]; |
6ee73861 | 158 | struct drm_device *dev = chan->dev; |
3945e475 | 159 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
3945e475 | 160 | unsigned long flags; |
6ee73861 | 161 | |
03bd6efa | 162 | /* remove channel from playlist, will context switch if active */ |
3945e475 | 163 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
03bd6efa | 164 | nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000); |
ac94a343 | 165 | nv50_fifo_playlist_update(dev); |
a87ff62a | 166 | |
03bd6efa | 167 | /* tell any engines on this channel to unload their contexts */ |
c420b2dc | 168 | nv50_fifo_kickoff(chan); |
03bd6efa BS |
169 | |
170 | nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000); | |
3945e475 FJ |
171 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
172 | ||
03bd6efa | 173 | /* clean up */ |
d908175c BS |
174 | if (chan->user) { |
175 | iounmap(chan->user); | |
176 | chan->user = NULL; | |
177 | } | |
03bd6efa | 178 | |
c420b2dc BS |
179 | atomic_dec(&chan->vm->engref[engine]); |
180 | chan->engctx[engine] = NULL; | |
181 | kfree(fctx); | |
6ee73861 BS |
182 | } |
183 | ||
c420b2dc BS |
184 | static int |
185 | nv50_fifo_init(struct drm_device *dev, int engine) | |
6ee73861 | 186 | { |
c420b2dc BS |
187 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
188 | u32 instance; | |
189 | int i; | |
190 | ||
191 | nv_mask(dev, 0x000200, 0x00000100, 0x00000000); | |
192 | nv_mask(dev, 0x000200, 0x00000100, 0x00000100); | |
193 | nv_wr32(dev, 0x00250c, 0x6f3cfc34); | |
194 | nv_wr32(dev, 0x002044, 0x01003fff); | |
195 | ||
196 | nv_wr32(dev, 0x002100, 0xffffffff); | |
197 | nv_wr32(dev, 0x002140, 0xffffffff); | |
198 | ||
199 | for (i = 0; i < 128; i++) { | |
200 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; | |
201 | if (chan && chan->engctx[engine]) | |
202 | instance = 0x80000000 | chan->ramin->vinst >> 12; | |
203 | else | |
204 | instance = 0x00000000; | |
205 | nv_wr32(dev, 0x002600 + (i * 4), instance); | |
206 | } | |
207 | ||
208 | nv50_fifo_playlist_update(dev); | |
209 | ||
210 | nv_wr32(dev, 0x003200, 1); | |
211 | nv_wr32(dev, 0x003250, 1); | |
212 | nv_wr32(dev, 0x002500, 1); | |
6ee73861 BS |
213 | return 0; |
214 | } | |
215 | ||
c420b2dc BS |
216 | static int |
217 | nv50_fifo_fini(struct drm_device *dev, int engine, bool suspend) | |
6ee73861 BS |
218 | { |
219 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c420b2dc | 220 | struct nv50_fifo_priv *priv = nv_engine(dev, engine); |
03bd6efa | 221 | int i; |
6ee73861 | 222 | |
03bd6efa BS |
223 | /* set playlist length to zero, fifo will unload context */ |
224 | nv_wr32(dev, 0x0032ec, 0); | |
225 | ||
226 | /* tell all connected engines to unload their contexts */ | |
c420b2dc | 227 | for (i = 0; i < priv->base.channels; i++) { |
03bd6efa | 228 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; |
c420b2dc | 229 | if (chan && !nv50_fifo_kickoff(chan)) |
03bd6efa | 230 | return -EBUSY; |
6ee73861 BS |
231 | } |
232 | ||
c420b2dc | 233 | nv_wr32(dev, 0x002140, 0); |
6ee73861 BS |
234 | return 0; |
235 | } | |
236 | ||
56ac7475 | 237 | void |
c420b2dc | 238 | nv50_fifo_tlb_flush(struct drm_device *dev, int engine) |
56ac7475 | 239 | { |
a11c3198 | 240 | nv50_vm_flush_engine(dev, 5); |
56ac7475 | 241 | } |
c420b2dc BS |
242 | |
243 | void | |
244 | nv50_fifo_destroy(struct drm_device *dev, int engine) | |
245 | { | |
246 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
247 | struct nv50_fifo_priv *priv = nv_engine(dev, engine); | |
248 | ||
249 | nouveau_irq_unregister(dev, 8); | |
250 | ||
251 | nouveau_gpuobj_ref(NULL, &priv->playlist[0]); | |
252 | nouveau_gpuobj_ref(NULL, &priv->playlist[1]); | |
253 | ||
254 | dev_priv->eng[engine] = NULL; | |
255 | kfree(priv); | |
256 | } | |
257 | ||
258 | int | |
259 | nv50_fifo_create(struct drm_device *dev) | |
260 | { | |
261 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
262 | struct nv50_fifo_priv *priv; | |
263 | int ret; | |
264 | ||
265 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
266 | if (!priv) | |
267 | return -ENOMEM; | |
268 | ||
269 | priv->base.base.destroy = nv50_fifo_destroy; | |
270 | priv->base.base.init = nv50_fifo_init; | |
271 | priv->base.base.fini = nv50_fifo_fini; | |
272 | priv->base.base.context_new = nv50_fifo_context_new; | |
273 | priv->base.base.context_del = nv50_fifo_context_del; | |
274 | priv->base.base.tlb_flush = nv50_fifo_tlb_flush; | |
275 | priv->base.channels = 127; | |
276 | dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base; | |
277 | ||
278 | ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000, | |
279 | NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]); | |
280 | if (ret) | |
281 | goto error; | |
282 | ||
283 | ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000, | |
284 | NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]); | |
285 | if (ret) | |
286 | goto error; | |
287 | ||
288 | nouveau_irq_register(dev, 8, nv04_fifo_isr); | |
289 | error: | |
290 | if (ret) | |
291 | priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO); | |
292 | return ret; | |
293 | } |