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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2007 Ben Skeggs. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm.h" | |
29 | #include "nouveau_drv.h" | |
a8eaebc6 | 30 | #include "nouveau_ramht.h" |
d5f3c90d | 31 | #include "nouveau_grctx.h" |
332b242f | 32 | #include "nouveau_dma.h" |
a11c3198 | 33 | #include "nouveau_vm.h" |
332b242f | 34 | #include "nv50_evo.h" |
6ee73861 | 35 | |
274fec93 BS |
36 | static int nv50_graph_register(struct drm_device *); |
37 | static void nv50_graph_isr(struct drm_device *); | |
b8c157d3 | 38 | |
6ee73861 BS |
39 | static void |
40 | nv50_graph_init_reset(struct drm_device *dev) | |
41 | { | |
42 | uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21); | |
43 | ||
44 | NV_DEBUG(dev, "\n"); | |
45 | ||
46 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e); | |
47 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e); | |
48 | } | |
49 | ||
50 | static void | |
51 | nv50_graph_init_intr(struct drm_device *dev) | |
52 | { | |
53 | NV_DEBUG(dev, "\n"); | |
54 | ||
274fec93 | 55 | nouveau_irq_register(dev, 12, nv50_graph_isr); |
6ee73861 BS |
56 | nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff); |
57 | nv_wr32(dev, 0x400138, 0xffffffff); | |
58 | nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff); | |
59 | } | |
60 | ||
61 | static void | |
62 | nv50_graph_init_regs__nv(struct drm_device *dev) | |
63 | { | |
304424e1 MK |
64 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
65 | uint32_t units = nv_rd32(dev, 0x1540); | |
66 | int i; | |
67 | ||
6ee73861 BS |
68 | NV_DEBUG(dev, "\n"); |
69 | ||
70 | nv_wr32(dev, 0x400804, 0xc0000000); | |
71 | nv_wr32(dev, 0x406800, 0xc0000000); | |
72 | nv_wr32(dev, 0x400c04, 0xc0000000); | |
716abaa8 | 73 | nv_wr32(dev, 0x401800, 0xc0000000); |
6ee73861 BS |
74 | nv_wr32(dev, 0x405018, 0xc0000000); |
75 | nv_wr32(dev, 0x402000, 0xc0000000); | |
76 | ||
304424e1 MK |
77 | for (i = 0; i < 16; i++) { |
78 | if (units & 1 << i) { | |
79 | if (dev_priv->chipset < 0xa0) { | |
80 | nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000); | |
81 | nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000); | |
82 | nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000); | |
83 | } else { | |
84 | nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000); | |
85 | nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000); | |
86 | nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000); | |
87 | } | |
88 | } | |
89 | } | |
90 | ||
6ee73861 BS |
91 | nv_wr32(dev, 0x400108, 0xffffffff); |
92 | ||
93 | nv_wr32(dev, 0x400824, 0x00004000); | |
94 | nv_wr32(dev, 0x400500, 0x00010001); | |
95 | } | |
96 | ||
97 | static void | |
562af10c | 98 | nv50_graph_init_zcull(struct drm_device *dev) |
6ee73861 | 99 | { |
562af10c BS |
100 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
101 | int i; | |
102 | ||
6ee73861 BS |
103 | NV_DEBUG(dev, "\n"); |
104 | ||
562af10c BS |
105 | switch (dev_priv->chipset & 0xf0) { |
106 | case 0x50: | |
107 | case 0x80: | |
108 | case 0x90: | |
109 | nv_wr32(dev, 0x402ca8, 0x00000800); | |
110 | break; | |
111 | case 0xa0: | |
112 | default: | |
113 | nv_wr32(dev, 0x402cc0, 0x00000000); | |
114 | if (dev_priv->chipset == 0xa0 || | |
115 | dev_priv->chipset == 0xaa || | |
116 | dev_priv->chipset == 0xac) { | |
117 | nv_wr32(dev, 0x402ca8, 0x00000802); | |
118 | } else { | |
119 | nv_wr32(dev, 0x402cc0, 0x00000000); | |
120 | nv_wr32(dev, 0x402ca8, 0x00000002); | |
121 | } | |
122 | ||
123 | break; | |
124 | } | |
125 | ||
126 | /* zero out zcull regions */ | |
127 | for (i = 0; i < 8; i++) { | |
128 | nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000); | |
129 | nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000); | |
130 | nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000); | |
131 | nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000); | |
132 | } | |
6ee73861 BS |
133 | } |
134 | ||
135 | static int | |
136 | nv50_graph_init_ctxctl(struct drm_device *dev) | |
137 | { | |
054b93e4 | 138 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
ec91db26 BS |
139 | struct nouveau_grctx ctx = {}; |
140 | uint32_t *cp; | |
141 | int i; | |
054b93e4 | 142 | |
6ee73861 BS |
143 | NV_DEBUG(dev, "\n"); |
144 | ||
ec91db26 BS |
145 | cp = kmalloc(512 * 4, GFP_KERNEL); |
146 | if (!cp) { | |
147 | NV_ERROR(dev, "failed to allocate ctxprog\n"); | |
148 | dev_priv->engine.graph.accel_blocked = true; | |
149 | return 0; | |
d5f3c90d | 150 | } |
ec91db26 BS |
151 | |
152 | ctx.dev = dev; | |
153 | ctx.mode = NOUVEAU_GRCTX_PROG; | |
154 | ctx.data = cp; | |
155 | ctx.ctxprog_max = 512; | |
156 | if (!nv50_grctx_init(&ctx)) { | |
157 | dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; | |
158 | ||
159 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); | |
160 | for (i = 0; i < ctx.ctxprog_len; i++) | |
161 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); | |
162 | } else { | |
163 | dev_priv->engine.graph.accel_blocked = true; | |
d5f3c90d | 164 | } |
ec91db26 | 165 | kfree(cp); |
6ee73861 | 166 | |
562af10c | 167 | nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */ |
6ee73861 BS |
168 | nv_wr32(dev, 0x400320, 4); |
169 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); | |
170 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0); | |
171 | return 0; | |
172 | } | |
173 | ||
174 | int | |
175 | nv50_graph_init(struct drm_device *dev) | |
176 | { | |
177 | int ret; | |
178 | ||
179 | NV_DEBUG(dev, "\n"); | |
180 | ||
181 | nv50_graph_init_reset(dev); | |
182 | nv50_graph_init_regs__nv(dev); | |
562af10c | 183 | nv50_graph_init_zcull(dev); |
6ee73861 BS |
184 | |
185 | ret = nv50_graph_init_ctxctl(dev); | |
186 | if (ret) | |
187 | return ret; | |
188 | ||
b8c157d3 BS |
189 | ret = nv50_graph_register(dev); |
190 | if (ret) | |
191 | return ret; | |
192 | nv50_graph_init_intr(dev); | |
6ee73861 BS |
193 | return 0; |
194 | } | |
195 | ||
196 | void | |
197 | nv50_graph_takedown(struct drm_device *dev) | |
198 | { | |
199 | NV_DEBUG(dev, "\n"); | |
274fec93 BS |
200 | nv_wr32(dev, 0x40013c, 0x00000000); |
201 | nouveau_irq_unregister(dev, 12); | |
6ee73861 BS |
202 | } |
203 | ||
204 | void | |
205 | nv50_graph_fifo_access(struct drm_device *dev, bool enabled) | |
206 | { | |
207 | const uint32_t mask = 0x00010001; | |
208 | ||
209 | if (enabled) | |
210 | nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask); | |
211 | else | |
212 | nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask); | |
213 | } | |
214 | ||
215 | struct nouveau_channel * | |
216 | nv50_graph_channel(struct drm_device *dev) | |
217 | { | |
218 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
219 | uint32_t inst; | |
220 | int i; | |
221 | ||
a51a3bf5 MM |
222 | /* Be sure we're not in the middle of a context switch or bad things |
223 | * will happen, such as unloading the wrong pgraph context. | |
224 | */ | |
4b5c152a | 225 | if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) |
a51a3bf5 MM |
226 | NV_ERROR(dev, "Ctxprog is still running\n"); |
227 | ||
6ee73861 BS |
228 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); |
229 | if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) | |
230 | return NULL; | |
231 | inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12; | |
232 | ||
233 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
cff5c133 | 234 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; |
6ee73861 | 235 | |
a8eaebc6 | 236 | if (chan && chan->ramin && chan->ramin->vinst == inst) |
6ee73861 BS |
237 | return chan; |
238 | } | |
239 | ||
240 | return NULL; | |
241 | } | |
242 | ||
243 | int | |
244 | nv50_graph_create_context(struct nouveau_channel *chan) | |
245 | { | |
246 | struct drm_device *dev = chan->dev; | |
247 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a8eaebc6 | 248 | struct nouveau_gpuobj *ramin = chan->ramin; |
d5f3c90d | 249 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
ec91db26 | 250 | struct nouveau_grctx ctx = {}; |
6ee73861 BS |
251 | int hdr, ret; |
252 | ||
253 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
254 | ||
3052be2c | 255 | ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0, |
a8eaebc6 BS |
256 | NVOBJ_FLAG_ZERO_ALLOC | |
257 | NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx); | |
6ee73861 BS |
258 | if (ret) |
259 | return ret; | |
6ee73861 | 260 | |
ac94a343 | 261 | hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; |
b3beb167 | 262 | nv_wo32(ramin, hdr + 0x00, 0x00190002); |
a8eaebc6 | 263 | nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst + |
b3beb167 | 264 | pgraph->grctx_size - 1); |
a8eaebc6 | 265 | nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst); |
b3beb167 BS |
266 | nv_wo32(ramin, hdr + 0x0c, 0); |
267 | nv_wo32(ramin, hdr + 0x10, 0); | |
268 | nv_wo32(ramin, hdr + 0x14, 0x00010000); | |
6ee73861 | 269 | |
ec91db26 BS |
270 | ctx.dev = chan->dev; |
271 | ctx.mode = NOUVEAU_GRCTX_VALS; | |
a8eaebc6 | 272 | ctx.data = chan->ramin_grctx; |
ec91db26 BS |
273 | nv50_grctx_init(&ctx); |
274 | ||
a8eaebc6 | 275 | nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12); |
6ee73861 | 276 | |
f56cb86f | 277 | dev_priv->engine.instmem.flush(dev); |
4c136142 | 278 | atomic_inc(&chan->vm->pgraph_refs); |
6ee73861 BS |
279 | return 0; |
280 | } | |
281 | ||
282 | void | |
283 | nv50_graph_destroy_context(struct nouveau_channel *chan) | |
284 | { | |
285 | struct drm_device *dev = chan->dev; | |
286 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3945e475 | 287 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
34311c73 | 288 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
ac94a343 | 289 | int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; |
3945e475 | 290 | unsigned long flags; |
6ee73861 BS |
291 | |
292 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
293 | ||
a8eaebc6 | 294 | if (!chan->ramin) |
6ee73861 BS |
295 | return; |
296 | ||
3945e475 | 297 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
34311c73 | 298 | pfifo->reassign(dev, false); |
3945e475 FJ |
299 | pgraph->fifo_access(dev, false); |
300 | ||
301 | if (pgraph->channel(dev) == chan) | |
302 | pgraph->unload_context(dev); | |
303 | ||
6ee73861 | 304 | for (i = hdr; i < hdr + 24; i += 4) |
a8eaebc6 | 305 | nv_wo32(chan->ramin, i, 0); |
f56cb86f | 306 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 307 | |
3945e475 | 308 | pgraph->fifo_access(dev, true); |
34311c73 | 309 | pfifo->reassign(dev, true); |
3945e475 FJ |
310 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
311 | ||
a8eaebc6 | 312 | nouveau_gpuobj_ref(NULL, &chan->ramin_grctx); |
4c136142 BS |
313 | |
314 | atomic_dec(&chan->vm->pgraph_refs); | |
6ee73861 BS |
315 | } |
316 | ||
317 | static int | |
318 | nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst) | |
319 | { | |
320 | uint32_t fifo = nv_rd32(dev, 0x400500); | |
321 | ||
322 | nv_wr32(dev, 0x400500, fifo & ~1); | |
323 | nv_wr32(dev, 0x400784, inst); | |
324 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40); | |
325 | nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11); | |
326 | nv_wr32(dev, 0x400040, 0xffffffff); | |
327 | (void)nv_rd32(dev, 0x400040); | |
328 | nv_wr32(dev, 0x400040, 0x00000000); | |
329 | nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1); | |
330 | ||
331 | if (nouveau_wait_for_idle(dev)) | |
332 | nv_wr32(dev, 0x40032c, inst | (1<<31)); | |
333 | nv_wr32(dev, 0x400500, fifo); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | int | |
339 | nv50_graph_load_context(struct nouveau_channel *chan) | |
340 | { | |
a8eaebc6 | 341 | uint32_t inst = chan->ramin->vinst >> 12; |
6ee73861 BS |
342 | |
343 | NV_DEBUG(chan->dev, "ch%d\n", chan->id); | |
344 | return nv50_graph_do_load_context(chan->dev, inst); | |
345 | } | |
346 | ||
347 | int | |
348 | nv50_graph_unload_context(struct drm_device *dev) | |
349 | { | |
a51a3bf5 | 350 | uint32_t inst; |
6ee73861 BS |
351 | |
352 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); | |
353 | if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) | |
354 | return 0; | |
355 | inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; | |
356 | ||
0a90dc51 | 357 | nouveau_wait_for_idle(dev); |
6ee73861 BS |
358 | nv_wr32(dev, 0x400784, inst); |
359 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); | |
360 | nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01); | |
361 | nouveau_wait_for_idle(dev); | |
6ee73861 BS |
362 | |
363 | nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst); | |
364 | return 0; | |
365 | } | |
366 | ||
274fec93 | 367 | static void |
6ee73861 BS |
368 | nv50_graph_context_switch(struct drm_device *dev) |
369 | { | |
370 | uint32_t inst; | |
371 | ||
372 | nv50_graph_unload_context(dev); | |
373 | ||
374 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT); | |
375 | inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE; | |
376 | nv50_graph_do_load_context(dev, inst); | |
377 | ||
378 | nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, | |
379 | NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH); | |
380 | } | |
381 | ||
382 | static int | |
b8c157d3 BS |
383 | nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, |
384 | u32 class, u32 mthd, u32 data) | |
6ee73861 | 385 | { |
a8eaebc6 | 386 | struct nouveau_gpuobj *gpuobj; |
6ee73861 | 387 | |
a8eaebc6 BS |
388 | gpuobj = nouveau_ramht_find(chan, data); |
389 | if (!gpuobj) | |
6ee73861 BS |
390 | return -ENOENT; |
391 | ||
a8eaebc6 | 392 | if (nouveau_notifier_offset(gpuobj, NULL)) |
6ee73861 BS |
393 | return -EINVAL; |
394 | ||
a8eaebc6 | 395 | chan->nvsw.vblsem = gpuobj; |
6ee73861 BS |
396 | chan->nvsw.vblsem_offset = ~0; |
397 | return 0; | |
398 | } | |
399 | ||
400 | static int | |
b8c157d3 BS |
401 | nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, |
402 | u32 class, u32 mthd, u32 data) | |
6ee73861 BS |
403 | { |
404 | if (nouveau_notifier_offset(chan->nvsw.vblsem, &data)) | |
405 | return -ERANGE; | |
406 | ||
407 | chan->nvsw.vblsem_offset = data >> 2; | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static int | |
b8c157d3 BS |
412 | nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, |
413 | u32 class, u32 mthd, u32 data) | |
6ee73861 BS |
414 | { |
415 | chan->nvsw.vblsem_rval = data; | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static int | |
b8c157d3 BS |
420 | nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, |
421 | u32 class, u32 mthd, u32 data) | |
6ee73861 BS |
422 | { |
423 | struct drm_device *dev = chan->dev; | |
424 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
425 | ||
426 | if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1) | |
427 | return -EINVAL; | |
428 | ||
042206c0 | 429 | drm_vblank_get(dev, data); |
1f6d2de2 FJ |
430 | |
431 | chan->nvsw.vblsem_head = data; | |
6ee73861 | 432 | list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting); |
1f6d2de2 | 433 | |
6ee73861 BS |
434 | return 0; |
435 | } | |
436 | ||
332b242f FJ |
437 | static int |
438 | nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan, | |
439 | u32 class, u32 mthd, u32 data) | |
440 | { | |
d7117e0d | 441 | nouveau_finish_page_flip(chan, NULL); |
332b242f FJ |
442 | return 0; |
443 | } | |
444 | ||
b8c157d3 BS |
445 | static int |
446 | nv50_graph_register(struct drm_device *dev) | |
447 | { | |
448 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
449 | ||
450 | if (dev_priv->engine.graph.registered) | |
451 | return 0; | |
452 | ||
453 | NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */ | |
454 | NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem); | |
455 | NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset); | |
456 | NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val); | |
457 | NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release); | |
332b242f | 458 | NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip); |
b8c157d3 BS |
459 | |
460 | NVOBJ_CLASS(dev, 0x0030, GR); /* null */ | |
461 | NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */ | |
462 | NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */ | |
b8c157d3 BS |
463 | |
464 | /* tesla */ | |
465 | if (dev_priv->chipset == 0x50) | |
466 | NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */ | |
467 | else | |
468 | if (dev_priv->chipset < 0xa0) | |
469 | NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */ | |
470 | else { | |
471 | switch (dev_priv->chipset) { | |
472 | case 0xa0: | |
473 | case 0xaa: | |
474 | case 0xac: | |
475 | NVOBJ_CLASS(dev, 0x8397, GR); | |
476 | break; | |
477 | case 0xa3: | |
478 | case 0xa5: | |
479 | case 0xa8: | |
480 | NVOBJ_CLASS(dev, 0x8597, GR); | |
481 | break; | |
482 | case 0xaf: | |
483 | NVOBJ_CLASS(dev, 0x8697, GR); | |
484 | break; | |
485 | } | |
486 | } | |
487 | ||
aa2c2e80 | 488 | /* compute */ |
a169f09b BS |
489 | NVOBJ_CLASS(dev, 0x50c0, GR); |
490 | if (dev_priv->chipset > 0xa0 && | |
491 | dev_priv->chipset != 0xaa && | |
492 | dev_priv->chipset != 0xac) | |
aa2c2e80 BS |
493 | NVOBJ_CLASS(dev, 0x85c0, GR); |
494 | ||
b8c157d3 BS |
495 | dev_priv->engine.graph.registered = true; |
496 | return 0; | |
497 | } | |
56ac7475 BS |
498 | |
499 | void | |
500 | nv50_graph_tlb_flush(struct drm_device *dev) | |
501 | { | |
a11c3198 | 502 | nv50_vm_flush_engine(dev, 0); |
56ac7475 BS |
503 | } |
504 | ||
505 | void | |
506 | nv86_graph_tlb_flush(struct drm_device *dev) | |
507 | { | |
508 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
509 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
510 | bool idle, timeout = false; | |
511 | unsigned long flags; | |
512 | u64 start; | |
513 | u32 tmp; | |
514 | ||
515 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | |
516 | nv_mask(dev, 0x400500, 0x00000001, 0x00000000); | |
517 | ||
518 | start = ptimer->read(dev); | |
519 | do { | |
520 | idle = true; | |
521 | ||
522 | for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) { | |
523 | if ((tmp & 7) == 1) | |
524 | idle = false; | |
525 | } | |
526 | ||
527 | for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) { | |
528 | if ((tmp & 7) == 1) | |
529 | idle = false; | |
530 | } | |
531 | ||
532 | for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) { | |
533 | if ((tmp & 7) == 1) | |
534 | idle = false; | |
535 | } | |
536 | } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000)); | |
537 | ||
538 | if (timeout) { | |
539 | NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: " | |
540 | "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
541 | nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380), | |
542 | nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388)); | |
543 | } | |
544 | ||
a11c3198 | 545 | nv50_vm_flush_engine(dev, 0); |
56ac7475 BS |
546 | |
547 | nv_mask(dev, 0x400500, 0x00000001, 0x00000001); | |
548 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
549 | } | |
274fec93 BS |
550 | |
551 | static struct nouveau_enum nv50_mp_exec_error_names[] = | |
552 | { | |
bb9b18a3 BS |
553 | { 3, "STACK_UNDERFLOW", NULL }, |
554 | { 4, "QUADON_ACTIVE", NULL }, | |
555 | { 8, "TIMEOUT", NULL }, | |
556 | { 0x10, "INVALID_OPCODE", NULL }, | |
557 | { 0x40, "BREAKPOINT", NULL }, | |
274fec93 BS |
558 | {} |
559 | }; | |
560 | ||
561 | static struct nouveau_bitfield nv50_graph_trap_m2mf[] = { | |
562 | { 0x00000001, "NOTIFY" }, | |
563 | { 0x00000002, "IN" }, | |
564 | { 0x00000004, "OUT" }, | |
565 | {} | |
566 | }; | |
567 | ||
568 | static struct nouveau_bitfield nv50_graph_trap_vfetch[] = { | |
569 | { 0x00000001, "FAULT" }, | |
570 | {} | |
571 | }; | |
572 | ||
573 | static struct nouveau_bitfield nv50_graph_trap_strmout[] = { | |
574 | { 0x00000001, "FAULT" }, | |
575 | {} | |
576 | }; | |
577 | ||
578 | static struct nouveau_bitfield nv50_graph_trap_ccache[] = { | |
579 | { 0x00000001, "FAULT" }, | |
580 | {} | |
581 | }; | |
582 | ||
583 | /* There must be a *lot* of these. Will take some time to gather them up. */ | |
6effe393 | 584 | struct nouveau_enum nv50_data_error_names[] = { |
bb9b18a3 BS |
585 | { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL }, |
586 | { 0x00000004, "INVALID_VALUE", NULL }, | |
587 | { 0x00000005, "INVALID_ENUM", NULL }, | |
588 | { 0x00000008, "INVALID_OBJECT", NULL }, | |
589 | { 0x00000009, "READ_ONLY_OBJECT", NULL }, | |
590 | { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, | |
591 | { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, | |
592 | { 0x0000000c, "INVALID_BITFIELD", NULL }, | |
593 | { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, | |
594 | { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, | |
595 | { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, | |
596 | { 0x00000010, "RT_DOUBLE_BIND", NULL }, | |
597 | { 0x00000011, "RT_TYPES_MISMATCH", NULL }, | |
598 | { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, | |
599 | { 0x00000015, "FP_TOO_FEW_REGS", NULL }, | |
600 | { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, | |
601 | { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, | |
602 | { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, | |
603 | { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, | |
604 | { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, | |
605 | { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, | |
606 | { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, | |
607 | { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, | |
608 | { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, | |
609 | { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, | |
610 | { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, | |
611 | { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, | |
612 | { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, | |
613 | { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, | |
614 | { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, | |
615 | { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, | |
616 | { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, | |
617 | { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, | |
618 | { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, | |
619 | { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, | |
620 | { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, | |
621 | { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, | |
622 | { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, | |
623 | { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, | |
624 | { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, | |
625 | { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, | |
274fec93 BS |
626 | {} |
627 | }; | |
628 | ||
629 | static struct nouveau_bitfield nv50_graph_intr[] = { | |
630 | { 0x00000001, "NOTIFY" }, | |
631 | { 0x00000002, "COMPUTE_QUERY" }, | |
632 | { 0x00000010, "ILLEGAL_MTHD" }, | |
633 | { 0x00000020, "ILLEGAL_CLASS" }, | |
634 | { 0x00000040, "DOUBLE_NOTIFY" }, | |
635 | { 0x00001000, "CONTEXT_SWITCH" }, | |
636 | { 0x00010000, "BUFFER_NOTIFY" }, | |
637 | { 0x00100000, "DATA_ERROR" }, | |
638 | { 0x00200000, "TRAP" }, | |
639 | { 0x01000000, "SINGLE_STEP" }, | |
640 | {} | |
641 | }; | |
642 | ||
643 | static void | |
644 | nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display) | |
645 | { | |
646 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
647 | uint32_t units = nv_rd32(dev, 0x1540); | |
648 | uint32_t addr, mp10, status, pc, oplow, ophigh; | |
649 | int i; | |
650 | int mps = 0; | |
651 | for (i = 0; i < 4; i++) { | |
652 | if (!(units & 1 << (i+24))) | |
653 | continue; | |
654 | if (dev_priv->chipset < 0xa0) | |
655 | addr = 0x408200 + (tpid << 12) + (i << 7); | |
656 | else | |
657 | addr = 0x408100 + (tpid << 11) + (i << 7); | |
658 | mp10 = nv_rd32(dev, addr + 0x10); | |
659 | status = nv_rd32(dev, addr + 0x14); | |
660 | if (!status) | |
661 | continue; | |
662 | if (display) { | |
663 | nv_rd32(dev, addr + 0x20); | |
664 | pc = nv_rd32(dev, addr + 0x24); | |
665 | oplow = nv_rd32(dev, addr + 0x70); | |
666 | ophigh= nv_rd32(dev, addr + 0x74); | |
667 | NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - " | |
668 | "TP %d MP %d: ", tpid, i); | |
669 | nouveau_enum_print(nv50_mp_exec_error_names, status); | |
670 | printk(" at %06x warp %d, opcode %08x %08x\n", | |
671 | pc&0xffffff, pc >> 24, | |
672 | oplow, ophigh); | |
673 | } | |
674 | nv_wr32(dev, addr + 0x10, mp10); | |
675 | nv_wr32(dev, addr + 0x14, 0); | |
676 | mps++; | |
677 | } | |
678 | if (!mps && display) | |
679 | NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: " | |
680 | "No MPs claiming errors?\n", tpid); | |
681 | } | |
682 | ||
683 | static void | |
684 | nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old, | |
685 | uint32_t ustatus_new, int display, const char *name) | |
686 | { | |
687 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
688 | int tps = 0; | |
689 | uint32_t units = nv_rd32(dev, 0x1540); | |
690 | int i, r; | |
691 | uint32_t ustatus_addr, ustatus; | |
692 | for (i = 0; i < 16; i++) { | |
693 | if (!(units & (1 << i))) | |
694 | continue; | |
695 | if (dev_priv->chipset < 0xa0) | |
696 | ustatus_addr = ustatus_old + (i << 12); | |
697 | else | |
698 | ustatus_addr = ustatus_new + (i << 11); | |
699 | ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff; | |
700 | if (!ustatus) | |
701 | continue; | |
702 | tps++; | |
703 | switch (type) { | |
704 | case 6: /* texture error... unknown for now */ | |
705 | nv50_fb_vm_trap(dev, display, name); | |
706 | if (display) { | |
707 | NV_ERROR(dev, "magic set %d:\n", i); | |
708 | for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) | |
709 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
710 | nv_rd32(dev, r)); | |
711 | } | |
712 | break; | |
713 | case 7: /* MP error */ | |
714 | if (ustatus & 0x00010000) { | |
715 | nv50_pgraph_mp_trap(dev, i, display); | |
716 | ustatus &= ~0x00010000; | |
717 | } | |
718 | break; | |
719 | case 8: /* TPDMA error */ | |
720 | { | |
721 | uint32_t e0c = nv_rd32(dev, ustatus_addr + 4); | |
722 | uint32_t e10 = nv_rd32(dev, ustatus_addr + 8); | |
723 | uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc); | |
724 | uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10); | |
725 | uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14); | |
726 | uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18); | |
727 | uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c); | |
728 | nv50_fb_vm_trap(dev, display, name); | |
729 | /* 2d engine destination */ | |
730 | if (ustatus & 0x00000010) { | |
731 | if (display) { | |
732 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n", | |
733 | i, e14, e10); | |
734 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
735 | i, e0c, e18, e1c, e20, e24); | |
736 | } | |
737 | ustatus &= ~0x00000010; | |
738 | } | |
739 | /* Render target */ | |
740 | if (ustatus & 0x00000040) { | |
741 | if (display) { | |
742 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n", | |
743 | i, e14, e10); | |
744 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
745 | i, e0c, e18, e1c, e20, e24); | |
746 | } | |
747 | ustatus &= ~0x00000040; | |
748 | } | |
749 | /* CUDA memory: l[], g[] or stack. */ | |
750 | if (ustatus & 0x00000080) { | |
751 | if (display) { | |
752 | if (e18 & 0x80000000) { | |
753 | /* g[] read fault? */ | |
754 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n", | |
755 | i, e14, e10 | ((e18 >> 24) & 0x1f)); | |
756 | e18 &= ~0x1f000000; | |
757 | } else if (e18 & 0xc) { | |
758 | /* g[] write fault? */ | |
759 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n", | |
760 | i, e14, e10 | ((e18 >> 7) & 0x1f)); | |
761 | e18 &= ~0x00000f80; | |
762 | } else { | |
763 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n", | |
764 | i, e14, e10); | |
765 | } | |
766 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
767 | i, e0c, e18, e1c, e20, e24); | |
768 | } | |
769 | ustatus &= ~0x00000080; | |
770 | } | |
771 | } | |
772 | break; | |
773 | } | |
774 | if (ustatus) { | |
775 | if (display) | |
776 | NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); | |
777 | } | |
778 | nv_wr32(dev, ustatus_addr, 0xc0000000); | |
779 | } | |
780 | ||
781 | if (!tps && display) | |
782 | NV_INFO(dev, "%s - No TPs claiming errors?\n", name); | |
783 | } | |
784 | ||
785 | static int | |
786 | nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid) | |
787 | { | |
788 | u32 status = nv_rd32(dev, 0x400108); | |
789 | u32 ustatus; | |
790 | ||
791 | if (!status && display) { | |
792 | NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n"); | |
793 | return 1; | |
794 | } | |
795 | ||
796 | /* DISPATCH: Relays commands to other units and handles NOTIFY, | |
797 | * COND, QUERY. If you get a trap from it, the command is still stuck | |
798 | * in DISPATCH and you need to do something about it. */ | |
799 | if (status & 0x001) { | |
800 | ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff; | |
801 | if (!ustatus && display) { | |
802 | NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n"); | |
803 | } | |
804 | ||
805 | nv_wr32(dev, 0x400500, 0x00000000); | |
806 | ||
807 | /* Known to be triggered by screwed up NOTIFY and COND... */ | |
808 | if (ustatus & 0x00000001) { | |
809 | u32 addr = nv_rd32(dev, 0x400808); | |
810 | u32 subc = (addr & 0x00070000) >> 16; | |
811 | u32 mthd = (addr & 0x00001ffc); | |
812 | u32 datal = nv_rd32(dev, 0x40080c); | |
813 | u32 datah = nv_rd32(dev, 0x400810); | |
814 | u32 class = nv_rd32(dev, 0x400814); | |
815 | u32 r848 = nv_rd32(dev, 0x400848); | |
816 | ||
817 | NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n"); | |
818 | if (display && (addr & 0x80000000)) { | |
819 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) " | |
820 | "subc %d class 0x%04x mthd 0x%04x " | |
821 | "data 0x%08x%08x " | |
822 | "400808 0x%08x 400848 0x%08x\n", | |
823 | chid, inst, subc, class, mthd, datah, | |
824 | datal, addr, r848); | |
825 | } else | |
826 | if (display) { | |
827 | NV_INFO(dev, "PGRAPH - no stuck command?\n"); | |
828 | } | |
829 | ||
830 | nv_wr32(dev, 0x400808, 0); | |
831 | nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3); | |
832 | nv_wr32(dev, 0x400848, 0); | |
833 | ustatus &= ~0x00000001; | |
834 | } | |
835 | ||
836 | if (ustatus & 0x00000002) { | |
837 | u32 addr = nv_rd32(dev, 0x40084c); | |
838 | u32 subc = (addr & 0x00070000) >> 16; | |
839 | u32 mthd = (addr & 0x00001ffc); | |
840 | u32 data = nv_rd32(dev, 0x40085c); | |
841 | u32 class = nv_rd32(dev, 0x400814); | |
842 | ||
843 | NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n"); | |
844 | if (display && (addr & 0x80000000)) { | |
845 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) " | |
846 | "subc %d class 0x%04x mthd 0x%04x " | |
847 | "data 0x%08x 40084c 0x%08x\n", | |
848 | chid, inst, subc, class, mthd, | |
849 | data, addr); | |
850 | } else | |
851 | if (display) { | |
852 | NV_INFO(dev, "PGRAPH - no stuck command?\n"); | |
853 | } | |
854 | ||
855 | nv_wr32(dev, 0x40084c, 0); | |
856 | ustatus &= ~0x00000002; | |
857 | } | |
858 | ||
859 | if (ustatus && display) { | |
860 | NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown " | |
861 | "0x%08x)\n", ustatus); | |
862 | } | |
863 | ||
864 | nv_wr32(dev, 0x400804, 0xc0000000); | |
865 | nv_wr32(dev, 0x400108, 0x001); | |
866 | status &= ~0x001; | |
867 | if (!status) | |
868 | return 0; | |
869 | } | |
870 | ||
871 | /* M2MF: Memory to memory copy engine. */ | |
872 | if (status & 0x002) { | |
873 | u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff; | |
874 | if (display) { | |
875 | NV_INFO(dev, "PGRAPH - TRAP_M2MF"); | |
876 | nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); | |
877 | printk("\n"); | |
878 | NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n", | |
879 | nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808), | |
880 | nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810)); | |
881 | ||
882 | } | |
883 | ||
884 | /* No sane way found yet -- just reset the bugger. */ | |
885 | nv_wr32(dev, 0x400040, 2); | |
886 | nv_wr32(dev, 0x400040, 0); | |
887 | nv_wr32(dev, 0x406800, 0xc0000000); | |
888 | nv_wr32(dev, 0x400108, 0x002); | |
889 | status &= ~0x002; | |
890 | } | |
891 | ||
892 | /* VFETCH: Fetches data from vertex buffers. */ | |
893 | if (status & 0x004) { | |
894 | u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff; | |
895 | if (display) { | |
896 | NV_INFO(dev, "PGRAPH - TRAP_VFETCH"); | |
897 | nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); | |
898 | printk("\n"); | |
899 | NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n", | |
900 | nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08), | |
901 | nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10)); | |
902 | } | |
903 | ||
904 | nv_wr32(dev, 0x400c04, 0xc0000000); | |
905 | nv_wr32(dev, 0x400108, 0x004); | |
906 | status &= ~0x004; | |
907 | } | |
908 | ||
909 | /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ | |
910 | if (status & 0x008) { | |
911 | ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff; | |
912 | if (display) { | |
913 | NV_INFO(dev, "PGRAPH - TRAP_STRMOUT"); | |
914 | nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); | |
915 | printk("\n"); | |
916 | NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n", | |
917 | nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808), | |
918 | nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810)); | |
919 | ||
920 | } | |
921 | ||
922 | /* No sane way found yet -- just reset the bugger. */ | |
923 | nv_wr32(dev, 0x400040, 0x80); | |
924 | nv_wr32(dev, 0x400040, 0); | |
925 | nv_wr32(dev, 0x401800, 0xc0000000); | |
926 | nv_wr32(dev, 0x400108, 0x008); | |
927 | status &= ~0x008; | |
928 | } | |
929 | ||
930 | /* CCACHE: Handles code and c[] caches and fills them. */ | |
931 | if (status & 0x010) { | |
932 | ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff; | |
933 | if (display) { | |
934 | NV_INFO(dev, "PGRAPH - TRAP_CCACHE"); | |
935 | nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); | |
936 | printk("\n"); | |
937 | NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x" | |
938 | " %08x %08x %08x\n", | |
4dcf905c MS |
939 | nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004), |
940 | nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c), | |
941 | nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014), | |
942 | nv_rd32(dev, 0x40501c)); | |
274fec93 BS |
943 | |
944 | } | |
945 | ||
946 | nv_wr32(dev, 0x405018, 0xc0000000); | |
947 | nv_wr32(dev, 0x400108, 0x010); | |
948 | status &= ~0x010; | |
949 | } | |
950 | ||
951 | /* Unknown, not seen yet... 0x402000 is the only trap status reg | |
952 | * remaining, so try to handle it anyway. Perhaps related to that | |
953 | * unknown DMA slot on tesla? */ | |
954 | if (status & 0x20) { | |
955 | ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff; | |
956 | if (display) | |
957 | NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus); | |
958 | nv_wr32(dev, 0x402000, 0xc0000000); | |
959 | /* no status modifiction on purpose */ | |
960 | } | |
961 | ||
962 | /* TEXTURE: CUDA texturing units */ | |
963 | if (status & 0x040) { | |
964 | nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display, | |
965 | "PGRAPH - TRAP_TEXTURE"); | |
966 | nv_wr32(dev, 0x400108, 0x040); | |
967 | status &= ~0x040; | |
968 | } | |
969 | ||
970 | /* MP: CUDA execution engines. */ | |
971 | if (status & 0x080) { | |
972 | nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display, | |
973 | "PGRAPH - TRAP_MP"); | |
974 | nv_wr32(dev, 0x400108, 0x080); | |
975 | status &= ~0x080; | |
976 | } | |
977 | ||
978 | /* TPDMA: Handles TP-initiated uncached memory accesses: | |
979 | * l[], g[], stack, 2d surfaces, render targets. */ | |
980 | if (status & 0x100) { | |
981 | nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display, | |
982 | "PGRAPH - TRAP_TPDMA"); | |
983 | nv_wr32(dev, 0x400108, 0x100); | |
984 | status &= ~0x100; | |
985 | } | |
986 | ||
987 | if (status) { | |
988 | if (display) | |
989 | NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status); | |
990 | nv_wr32(dev, 0x400108, status); | |
991 | } | |
992 | ||
993 | return 1; | |
994 | } | |
995 | ||
996 | static int | |
997 | nv50_graph_isr_chid(struct drm_device *dev, u64 inst) | |
998 | { | |
999 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1000 | struct nouveau_channel *chan; | |
1001 | unsigned long flags; | |
1002 | int i; | |
1003 | ||
1004 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
1005 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
1006 | chan = dev_priv->channels.ptr[i]; | |
1007 | if (!chan || !chan->ramin) | |
1008 | continue; | |
1009 | ||
1010 | if (inst == chan->ramin->vinst) | |
1011 | break; | |
1012 | } | |
1013 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
1014 | return i; | |
1015 | } | |
1016 | ||
1017 | static void | |
1018 | nv50_graph_isr(struct drm_device *dev) | |
1019 | { | |
1020 | u32 stat; | |
1021 | ||
1022 | while ((stat = nv_rd32(dev, 0x400100))) { | |
1023 | u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12; | |
1024 | u32 chid = nv50_graph_isr_chid(dev, inst); | |
1025 | u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR); | |
1026 | u32 subc = (addr & 0x00070000) >> 16; | |
1027 | u32 mthd = (addr & 0x00001ffc); | |
1028 | u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA); | |
1029 | u32 class = nv_rd32(dev, 0x400814); | |
1030 | u32 show = stat; | |
1031 | ||
1032 | if (stat & 0x00000010) { | |
1033 | if (!nouveau_gpuobj_mthd_call2(dev, chid, class, | |
1034 | mthd, data)) | |
1035 | show &= ~0x00000010; | |
1036 | } | |
1037 | ||
1038 | if (stat & 0x00001000) { | |
1039 | nv_wr32(dev, 0x400500, 0x00000000); | |
1040 | nv_wr32(dev, 0x400100, 0x00001000); | |
1041 | nv_mask(dev, 0x40013c, 0x00001000, 0x00000000); | |
1042 | nv50_graph_context_switch(dev); | |
1043 | stat &= ~0x00001000; | |
1044 | show &= ~0x00001000; | |
1045 | } | |
1046 | ||
1047 | show = (show && nouveau_ratelimit()) ? show : 0; | |
1048 | ||
1049 | if (show & 0x00100000) { | |
1050 | u32 ecode = nv_rd32(dev, 0x400110); | |
1051 | NV_INFO(dev, "PGRAPH - DATA_ERROR "); | |
1052 | nouveau_enum_print(nv50_data_error_names, ecode); | |
1053 | printk("\n"); | |
1054 | } | |
1055 | ||
1056 | if (stat & 0x00200000) { | |
1057 | if (!nv50_pgraph_trap_handler(dev, show, inst, chid)) | |
1058 | show &= ~0x00200000; | |
1059 | } | |
1060 | ||
1061 | nv_wr32(dev, 0x400100, stat); | |
1062 | nv_wr32(dev, 0x400500, 0x00010001); | |
1063 | ||
1064 | if (show) { | |
1065 | NV_INFO(dev, "PGRAPH -"); | |
1066 | nouveau_bitfield_print(nv50_graph_intr, show); | |
1067 | printk("\n"); | |
1068 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d " | |
1069 | "class 0x%04x mthd 0x%04x data 0x%08x\n", | |
1070 | chid, inst, subc, class, mthd, data); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | if (nv_rd32(dev, 0x400824) & (1 << 31)) | |
1075 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); | |
1076 | } |