[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nv50_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"

#include "nouveau_grctx.h"

#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)

static void
nv50_graph_init_reset(struct drm_device *dev)
{
	uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);

	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
}

static void
nv50_graph_init_intr(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
	nv_wr32(dev, 0x400138, 0xffffffff);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
}

static void
nv50_graph_init_regs__nv(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t units = nv_rd32(dev, 0x1540);
	int i;

	NV_DEBUG(dev, "\n");

	nv_wr32(dev, 0x400804, 0xc0000000);
	nv_wr32(dev, 0x406800, 0xc0000000);
	nv_wr32(dev, 0x400c04, 0xc0000000);
	nv_wr32(dev, 0x401800, 0xc0000000);
	nv_wr32(dev, 0x405018, 0xc0000000);
	nv_wr32(dev, 0x402000, 0xc0000000);

	for (i = 0; i < 16; i++) {
		if (units & 1 << i) {
			if (dev_priv->chipset < 0xa0) {
				nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
				nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
				nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
			} else {
				nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
				nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
				nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
			}
		}
	}

	nv_wr32(dev, 0x400108, 0xffffffff);

	nv_wr32(dev, 0x400824, 0x00004000);
	nv_wr32(dev, 0x400500, 0x00010001);
}

static void
nv50_graph_init_regs(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");

	nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
				(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
	nv_wr32(dev, 0x402ca8, 0x800);
}

static int
nv50_graph_init_ctxctl(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_grctx ctx = {};
	uint32_t *cp;
	int i;

	NV_DEBUG(dev, "\n");

	cp = kmalloc(512 * 4, GFP_KERNEL);
	if (!cp) {
		NV_ERROR(dev, "failed to allocate ctxprog\n");
		dev_priv->engine.graph.accel_blocked = true;
		return 0;
	}

	ctx.dev = dev;
	ctx.mode = NOUVEAU_GRCTX_PROG;
	ctx.data = cp;
	ctx.ctxprog_max = 512;
	if (!nv50_grctx_init(&ctx)) {
		dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
		for (i = 0; i < ctx.ctxprog_len; i++)
			nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
	} else {
		dev_priv->engine.graph.accel_blocked = true;
	}
	kfree(cp);

	nv_wr32(dev, 0x400320, 4);
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
	return 0;
}

int
nv50_graph_init(struct drm_device *dev)
{
	int ret;

	NV_DEBUG(dev, "\n");

	nv50_graph_init_reset(dev);
	nv50_graph_init_regs__nv(dev);
	nv50_graph_init_regs(dev);
	nv50_graph_init_intr(dev);

	ret = nv50_graph_init_ctxctl(dev);
	if (ret)
		return ret;

	return 0;
}

void
nv50_graph_takedown(struct drm_device *dev)
{
	NV_DEBUG(dev, "\n");
}

void
nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
{
	const uint32_t mask = 0x00010001;

	if (enabled)
		nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
	else
		nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
}

struct nouveau_channel *
nv50_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	/* Be sure we're not in the middle of a context switch or bad things
	 * will happen, such as unloading the wrong pgraph context.
	 */
	if (!nv_wait(0x400300, 0x00000001, 0x00000000))
		NV_ERROR(dev, "Ctxprog is still running\n");

	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->ramin && chan->ramin->instance == inst)
			return chan;
	}

	return NULL;
}

int
nv50_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
	struct nouveau_gpuobj *obj;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_grctx ctx = {};
	int hdr, ret;

	NV_DEBUG(dev, "ch%d\n", chan->id);

	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
				     0x1000, NVOBJ_FLAG_ZERO_ALLOC |
				     NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
	if (ret)
		return ret;
	obj = chan->ramin_grctx->gpuobj;

	hdr = IS_G80 ? 0x200 : 0x20;
	nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
	nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
					   pgraph->grctx_size - 1);
	nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
	nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
	nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
	nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);

	ctx.dev = chan->dev;
	ctx.mode = NOUVEAU_GRCTX_VALS;
	ctx.data = obj;
	nv50_grctx_init(&ctx);

	nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);

	dev_priv->engine.instmem.flush(dev);
	return 0;
}

void
nv50_graph_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i, hdr = IS_G80 ? 0x200 : 0x20;

	NV_DEBUG(dev, "ch%d\n", chan->id);

	if (!chan->ramin || !chan->ramin->gpuobj)
		return;

	for (i = hdr; i < hdr + 24; i += 4)
		nv_wo32(dev, chan->ramin->gpuobj, i/4, 0);
	dev_priv->engine.instmem.flush(dev);

	nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
}

static int
nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
{
	uint32_t fifo = nv_rd32(dev, 0x400500);

	nv_wr32(dev, 0x400500, fifo & ~1);
	nv_wr32(dev, 0x400784, inst);
	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
	nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
	nv_wr32(dev, 0x400040, 0xffffffff);
	(void)nv_rd32(dev, 0x400040);
	nv_wr32(dev, 0x400040, 0x00000000);
	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);

	if (nouveau_wait_for_idle(dev))
		nv_wr32(dev, 0x40032c, inst | (1<<31));
	nv_wr32(dev, 0x400500, fifo);

	return 0;
}

int
nv50_graph_load_context(struct nouveau_channel *chan)
{
	uint32_t inst = chan->ramin->instance >> 12;

	NV_DEBUG(chan->dev, "ch%d\n", chan->id);
	return nv50_graph_do_load_context(chan->dev, inst);
}

int
nv50_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;

	inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;

	nouveau_wait_for_idle(dev);
	nv_wr32(dev, 0x400784, inst);
	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
	nouveau_wait_for_idle(dev);

	nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
	return 0;
}

void
nv50_graph_context_switch(struct drm_device *dev)
{
	uint32_t inst;

	nv50_graph_unload_context(dev);

	inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
	inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
	nv50_graph_do_load_context(dev, inst);

	nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
		NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
}

static int
nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
			   int mthd, uint32_t data)
{
	struct nouveau_gpuobj_ref *ref = NULL;

	if (nouveau_gpuobj_ref_find(chan, data, &ref))
		return -ENOENT;

	if (nouveau_notifier_offset(ref->gpuobj, NULL))
		return -EINVAL;

	chan->nvsw.vblsem = ref->gpuobj;
	chan->nvsw.vblsem_offset = ~0;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
			      int mthd, uint32_t data)
{
	if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
		return -ERANGE;

	chan->nvsw.vblsem_offset = data >> 2;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
				   int mthd, uint32_t data)
{
	chan->nvsw.vblsem_rval = data;
	return 0;
}

static int
nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
			       int mthd, uint32_t data)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
		return -EINVAL;

	if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
		      NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
		nv_wr32(dev, NV50_PDISPLAY_INTR_1,
			NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
		nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
			NV50_PDISPLAY_INTR_EN) |
			NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
	}

	list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
	return 0;
}

static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
	{ 0x018c, nv50_graph_nvsw_dma_vblsem },
	{ 0x0400, nv50_graph_nvsw_vblsem_offset },
	{ 0x0404, nv50_graph_nvsw_vblsem_release_val },
	{ 0x0408, nv50_graph_nvsw_vblsem_release },
	{}
};

struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
	{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
	{ 0x0030, false, NULL }, /* null */
	{ 0x5039, false, NULL }, /* m2mf */
	{ 0x502d, false, NULL }, /* 2d */
	{ 0x50c0, false, NULL }, /* compute */
	{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
	{ 0x5097, false, NULL }, /* tesla (nv50) */
	{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
	{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
	{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
	{}
};
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
	30
d5f3c90d	31	#include "nouveau_grctx.h"
6ee73861 BS	32
	33	#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
	34
	35	static void
	36	nv50_graph_init_reset(struct drm_device *dev)
	37	{
	38	uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH \| (1 << 21);
	39
	40	NV_DEBUG(dev, "\n");
	41
	42	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
	43	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \| pmc_e);
	44	}
	45
	46	static void
	47	nv50_graph_init_intr(struct drm_device *dev)
	48	{
	49	NV_DEBUG(dev, "\n");
	50
	51	nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
	52	nv_wr32(dev, 0x400138, 0xffffffff);
	53	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
	54	}
	55
	56	static void
	57	nv50_graph_init_regs__nv(struct drm_device *dev)
	58	{
304424e1 MK	59	struct drm_nouveau_private *dev_priv = dev->dev_private;
	60	uint32_t units = nv_rd32(dev, 0x1540);
	61	int i;
	62
6ee73861 BS	63	NV_DEBUG(dev, "\n");
	64
	65	nv_wr32(dev, 0x400804, 0xc0000000);
	66	nv_wr32(dev, 0x406800, 0xc0000000);
	67	nv_wr32(dev, 0x400c04, 0xc0000000);
716abaa8	68	nv_wr32(dev, 0x401800, 0xc0000000);
6ee73861 BS	69	nv_wr32(dev, 0x405018, 0xc0000000);
	70	nv_wr32(dev, 0x402000, 0xc0000000);
	71
304424e1 MK	72	for (i = 0; i < 16; i++) {
	73	if (units & 1 << i) {
	74	if (dev_priv->chipset < 0xa0) {
	75	nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
	76	nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
	77	nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
	78	} else {
	79	nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
	80	nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
	81	nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
	82	}
	83	}
	84	}
	85
6ee73861 BS	86	nv_wr32(dev, 0x400108, 0xffffffff);
	87
	88	nv_wr32(dev, 0x400824, 0x00004000);
	89	nv_wr32(dev, 0x400500, 0x00010001);
	90	}
	91
	92	static void
	93	nv50_graph_init_regs(struct drm_device *dev)
	94	{
	95	NV_DEBUG(dev, "\n");
	96
	97	nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
	98	(1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
	99	nv_wr32(dev, 0x402ca8, 0x800);
	100	}
	101
	102	static int
	103	nv50_graph_init_ctxctl(struct drm_device *dev)
	104	{
054b93e4	105	struct drm_nouveau_private *dev_priv = dev->dev_private;
ec91db26 BS	106	struct nouveau_grctx ctx = {};
	107	uint32_t *cp;
	108	int i;
054b93e4	109
6ee73861 BS	110	NV_DEBUG(dev, "\n");
6ee73861 BS	111
ec91db26 BS	112	cp = kmalloc(512 * 4, GFP_KERNEL);
	113	if (!cp) {
	114	NV_ERROR(dev, "failed to allocate ctxprog\n");
	115	dev_priv->engine.graph.accel_blocked = true;
	116	return 0;
d5f3c90d	117	}
ec91db26 BS	118
	119	ctx.dev = dev;
	120	ctx.mode = NOUVEAU_GRCTX_PROG;
	121	ctx.data = cp;
	122	ctx.ctxprog_max = 512;
	123	if (!nv50_grctx_init(&ctx)) {
	124	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
	125
	126	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	127	for (i = 0; i < ctx.ctxprog_len; i++)
	128	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
	129	} else {
	130	dev_priv->engine.graph.accel_blocked = true;
d5f3c90d	131	}
ec91db26	132	kfree(cp);
6ee73861 BS	133
	134	nv_wr32(dev, 0x400320, 4);
	135	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
	136	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
	137	return 0;
	138	}
	139
	140	int
	141	nv50_graph_init(struct drm_device *dev)
	142	{
	143	int ret;
	144
	145	NV_DEBUG(dev, "\n");
	146
	147	nv50_graph_init_reset(dev);
	148	nv50_graph_init_regs__nv(dev);
	149	nv50_graph_init_regs(dev);
	150	nv50_graph_init_intr(dev);
	151
	152	ret = nv50_graph_init_ctxctl(dev);
	153	if (ret)
	154	return ret;
	155
	156	return 0;
	157	}
	158
	159	void
	160	nv50_graph_takedown(struct drm_device *dev)
	161	{
	162	NV_DEBUG(dev, "\n");
6ee73861 BS	163	}
	164
	165	void
	166	nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
	167	{
	168	const uint32_t mask = 0x00010001;
	169
	170	if (enabled)
	171	nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) \| mask);
	172	else
	173	nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
	174	}
	175
	176	struct nouveau_channel *
	177	nv50_graph_channel(struct drm_device *dev)
	178	{
	179	struct drm_nouveau_private *dev_priv = dev->dev_private;
	180	uint32_t inst;
	181	int i;
	182
a51a3bf5 MM	183	/* Be sure we're not in the middle of a context switch or bad things
	184	* will happen, such as unloading the wrong pgraph context.
	185	*/
	186	if (!nv_wait(0x400300, 0x00000001, 0x00000000))
	187	NV_ERROR(dev, "Ctxprog is still running\n");
	188
6ee73861 BS	189	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	190	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
	191	return NULL;
	192	inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
	193
	194	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	195	struct nouveau_channel *chan = dev_priv->fifos[i];
	196
	197	if (chan && chan->ramin && chan->ramin->instance == inst)
	198	return chan;
	199	}
	200
	201	return NULL;
	202	}
	203
	204	int
	205	nv50_graph_create_context(struct nouveau_channel *chan)
	206	{
	207	struct drm_device *dev = chan->dev;
	208	struct drm_nouveau_private *dev_priv = dev->dev_private;
	209	struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
6e86e041	210	struct nouveau_gpuobj *obj;
d5f3c90d	211	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
ec91db26	212	struct nouveau_grctx ctx = {};
6ee73861 BS	213	int hdr, ret;
	214
	215	NV_DEBUG(dev, "ch%d\n", chan->id);
	216
d5f3c90d MK	217	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
d5f3c90d MK	218	0x1000, NVOBJ_FLAG_ZERO_ALLOC \|
6ee73861 BS	219	NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
	220	if (ret)
	221	return ret;
6e86e041	222	obj = chan->ramin_grctx->gpuobj;
6ee73861 BS	223
6ee73861 BS	224	hdr = IS_G80 ? 0x200 : 0x20;
6ee73861 BS	225	nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002);
6ee73861 BS	226	nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
d5f3c90d	227	pgraph->grctx_size - 1);
6ee73861 BS	228	nv_wo32(dev, ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
	229	nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0);
	230	nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
	231	nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);
6ee73861	232
ec91db26 BS	233	ctx.dev = chan->dev;
	234	ctx.mode = NOUVEAU_GRCTX_VALS;
	235	ctx.data = obj;
	236	nv50_grctx_init(&ctx);
	237
6e86e041	238	nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
6ee73861	239
f56cb86f	240	dev_priv->engine.instmem.flush(dev);
6ee73861 BS	241	return 0;
	242	}
	243
	244	void
	245	nv50_graph_destroy_context(struct nouveau_channel *chan)
	246	{
	247	struct drm_device *dev = chan->dev;
	248	struct drm_nouveau_private *dev_priv = dev->dev_private;
	249	int i, hdr = IS_G80 ? 0x200 : 0x20;
	250
	251	NV_DEBUG(dev, "ch%d\n", chan->id);
	252
	253	if (!chan->ramin \|\| !chan->ramin->gpuobj)
	254	return;
	255
6ee73861 BS	256	for (i = hdr; i < hdr + 24; i += 4)
6ee73861 BS	257	nv_wo32(dev, chan->ramin->gpuobj, i/4, 0);
f56cb86f	258	dev_priv->engine.instmem.flush(dev);
6ee73861 BS	259
	260	nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
	261	}
	262
	263	static int
	264	nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
	265	{
	266	uint32_t fifo = nv_rd32(dev, 0x400500);
	267
	268	nv_wr32(dev, 0x400500, fifo & ~1);
	269	nv_wr32(dev, 0x400784, inst);
	270	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) \| 0x40);
	271	nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) \| 0x11);
	272	nv_wr32(dev, 0x400040, 0xffffffff);
	273	(void)nv_rd32(dev, 0x400040);
	274	nv_wr32(dev, 0x400040, 0x00000000);
	275	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) \| 1);
	276
	277	if (nouveau_wait_for_idle(dev))
	278	nv_wr32(dev, 0x40032c, inst \| (1<<31));
	279	nv_wr32(dev, 0x400500, fifo);
	280
	281	return 0;
	282	}
	283
	284	int
	285	nv50_graph_load_context(struct nouveau_channel *chan)
	286	{
	287	uint32_t inst = chan->ramin->instance >> 12;
	288
	289	NV_DEBUG(chan->dev, "ch%d\n", chan->id);
	290	return nv50_graph_do_load_context(chan->dev, inst);
	291	}
	292
	293	int
	294	nv50_graph_unload_context(struct drm_device *dev)
	295	{
a51a3bf5	296	uint32_t inst;
6ee73861 BS	297
	298	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
	299	if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
	300	return 0;
	301	inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
	302
0a90dc51	303	nouveau_wait_for_idle(dev);
6ee73861 BS	304	nv_wr32(dev, 0x400784, inst);
	305	nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) \| 0x20);
	306	nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) \| 0x01);
	307	nouveau_wait_for_idle(dev);
6ee73861 BS	308
	309	nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
	310	return 0;
	311	}
	312
	313	void
	314	nv50_graph_context_switch(struct drm_device *dev)
	315	{
	316	uint32_t inst;
	317
	318	nv50_graph_unload_context(dev);
	319
	320	inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
	321	inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
	322	nv50_graph_do_load_context(dev, inst);
	323
	324	nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
	325	NV40_PGRAPH_INTR_EN) \| NV_PGRAPH_INTR_CONTEXT_SWITCH);
	326	}
	327
	328	static int
	329	nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan, int grclass,
	330	int mthd, uint32_t data)
	331	{
	332	struct nouveau_gpuobj_ref *ref = NULL;
	333
	334	if (nouveau_gpuobj_ref_find(chan, data, &ref))
	335	return -ENOENT;
	336
	337	if (nouveau_notifier_offset(ref->gpuobj, NULL))
	338	return -EINVAL;
	339
	340	chan->nvsw.vblsem = ref->gpuobj;
	341	chan->nvsw.vblsem_offset = ~0;
	342	return 0;
	343	}
	344
	345	static int
	346	nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan, int grclass,
	347	int mthd, uint32_t data)
	348	{
	349	if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
	350	return -ERANGE;
	351
	352	chan->nvsw.vblsem_offset = data >> 2;
	353	return 0;
	354	}
	355
	356	static int
	357	nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan, int grclass,
	358	int mthd, uint32_t data)
	359	{
	360	chan->nvsw.vblsem_rval = data;
	361	return 0;
	362	}
	363
	364	static int
	365	nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan, int grclass,
	366	int mthd, uint32_t data)
	367	{
	368	struct drm_device *dev = chan->dev;
	369	struct drm_nouveau_private *dev_priv = dev->dev_private;
	370
	371	if (!chan->nvsw.vblsem \|\| chan->nvsw.vblsem_offset == ~0 \|\| data > 1)
372	return -EINVAL;
373
374	if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN) &
375	NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data))) {
376	nv_wr32(dev, NV50_PDISPLAY_INTR_1,
377	NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
378	nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
379	NV50_PDISPLAY_INTR_EN) \|
380	NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(data));
381	}
382
383	list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
384	return 0;
385	}
386
387	static struct nouveau_pgraph_object_method nv50_graph_nvsw_methods[] = {
388	{ 0x018c, nv50_graph_nvsw_dma_vblsem },
389	{ 0x0400, nv50_graph_nvsw_vblsem_offset },
390	{ 0x0404, nv50_graph_nvsw_vblsem_release_val },
391	{ 0x0408, nv50_graph_nvsw_vblsem_release },
392	{}
393	};
394
395	struct nouveau_pgraph_object_class nv50_graph_grclass[] = {
396	{ 0x506e, true, nv50_graph_nvsw_methods }, /* nvsw */
397	{ 0x0030, false, NULL }, /* null */
398	{ 0x5039, false, NULL }, /* m2mf */
399	{ 0x502d, false, NULL }, /* 2d */
400	{ 0x50c0, false, NULL }, /* compute */
d327dd4e	401	{ 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */
6ee73861	402	{ 0x5097, false, NULL }, /* tesla (nv50) */
d327dd4e MK	403	{ 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */
	404	{ 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */
	405	{ 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */
6ee73861 BS	406	{}
6ee73861 BS	407	};