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drm/nouveau: use static vidshift of 2 on volt 0x30 tables
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nv50_graph.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm.h"
29#include "nouveau_drv.h"
a8eaebc6 30#include "nouveau_ramht.h"
d5f3c90d 31#include "nouveau_grctx.h"
332b242f 32#include "nouveau_dma.h"
a11c3198 33#include "nouveau_vm.h"
332b242f 34#include "nv50_evo.h"
6ee73861 35
274fec93
BS		 36static int nv50_graph_register(struct drm_device *);
37static void nv50_graph_isr(struct drm_device *);
b8c157d3 38
6ee73861
BS		 39static void
40nv50_graph_init_reset(struct drm_device *dev)
41{
42 uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
43
44 NV_DEBUG(dev, "\n");
45
46 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
47 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
48}
49
50static void
51nv50_graph_init_intr(struct drm_device *dev)
52{
53 NV_DEBUG(dev, "\n");
54
274fec93 55 nouveau_irq_register(dev, 12, nv50_graph_isr);
6ee73861
BS		 56 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
57 nv_wr32(dev, 0x400138, 0xffffffff);
58 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
59}
60
61static void
62nv50_graph_init_regs__nv(struct drm_device *dev)
63{
304424e1
MK		 64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65 uint32_t units = nv_rd32(dev, 0x1540);
66 int i;
67
6ee73861
BS		 68 NV_DEBUG(dev, "\n");
69
70 nv_wr32(dev, 0x400804, 0xc0000000);
71 nv_wr32(dev, 0x406800, 0xc0000000);
72 nv_wr32(dev, 0x400c04, 0xc0000000);
716abaa8 73 nv_wr32(dev, 0x401800, 0xc0000000);
6ee73861
BS		 74 nv_wr32(dev, 0x405018, 0xc0000000);
75 nv_wr32(dev, 0x402000, 0xc0000000);
76
304424e1
MK		 77 for (i = 0; i < 16; i++) {
78 if (units & 1 << i) {
79 if (dev_priv->chipset < 0xa0) {
80 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
81 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
82 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
83 } else {
84 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
85 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
86 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
87 }
88 }
89 }
90
6ee73861
BS		 91 nv_wr32(dev, 0x400108, 0xffffffff);
92
93 nv_wr32(dev, 0x400824, 0x00004000);
94 nv_wr32(dev, 0x400500, 0x00010001);
95}
96
97static void
562af10c 98nv50_graph_init_zcull(struct drm_device *dev)
6ee73861 99{
562af10c
BS		 100 struct drm_nouveau_private *dev_priv = dev->dev_private;
101 int i;
102
6ee73861
BS		 103 NV_DEBUG(dev, "\n");
104
562af10c
BS		 105 switch (dev_priv->chipset & 0xf0) {
106 case 0x50:
107 case 0x80:
108 case 0x90:
109 nv_wr32(dev, 0x402ca8, 0x00000800);
110 break;
111 case 0xa0:
112 default:
113 nv_wr32(dev, 0x402cc0, 0x00000000);
114 if (dev_priv->chipset == 0xa0 ||
115 dev_priv->chipset == 0xaa ||
116 dev_priv->chipset == 0xac) {
117 nv_wr32(dev, 0x402ca8, 0x00000802);
118 } else {
119 nv_wr32(dev, 0x402cc0, 0x00000000);
120 nv_wr32(dev, 0x402ca8, 0x00000002);
121 }
122
123 break;
124 }
125
126 /* zero out zcull regions */
127 for (i = 0; i < 8; i++) {
128 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
129 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
130 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
131 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
132 }
6ee73861
BS		 133}
134
135static int
136nv50_graph_init_ctxctl(struct drm_device *dev)
137{
054b93e4 138 struct drm_nouveau_private *dev_priv = dev->dev_private;
ec91db26
BS		 139 struct nouveau_grctx ctx = {};
140 uint32_t *cp;
141 int i;
054b93e4 142
6ee73861
BS		 143 NV_DEBUG(dev, "\n");
144
ec91db26
BS		 145 cp = kmalloc(512 * 4, GFP_KERNEL);
146 if (!cp) {
147 NV_ERROR(dev, "failed to allocate ctxprog\n");
148 dev_priv->engine.graph.accel_blocked = true;
149 return 0;
d5f3c90d 150 }
ec91db26
BS		 151
152 ctx.dev = dev;
153 ctx.mode = NOUVEAU_GRCTX_PROG;
154 ctx.data = cp;
155 ctx.ctxprog_max = 512;
156 if (!nv50_grctx_init(&ctx)) {
157 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
158
159 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
160 for (i = 0; i < ctx.ctxprog_len; i++)
161 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
162 } else {
163 dev_priv->engine.graph.accel_blocked = true;
d5f3c90d 164 }
ec91db26 165 kfree(cp);
6ee73861 166
562af10c 167 nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
6ee73861
BS		 168 nv_wr32(dev, 0x400320, 4);
169 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
170 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
171 return 0;
172}
173
174int
175nv50_graph_init(struct drm_device *dev)
176{
177 int ret;
178
179 NV_DEBUG(dev, "\n");
180
181 nv50_graph_init_reset(dev);
182 nv50_graph_init_regs__nv(dev);
562af10c 183 nv50_graph_init_zcull(dev);
6ee73861
BS		 184
185 ret = nv50_graph_init_ctxctl(dev);
186 if (ret)
187 return ret;
188
b8c157d3
BS		 189 ret = nv50_graph_register(dev);
190 if (ret)
191 return ret;
192 nv50_graph_init_intr(dev);
6ee73861
BS		 193 return 0;
194}
195
196void
197nv50_graph_takedown(struct drm_device *dev)
198{
199 NV_DEBUG(dev, "\n");
274fec93
BS		 200 nv_wr32(dev, 0x40013c, 0x00000000);
201 nouveau_irq_unregister(dev, 12);
6ee73861
BS		 202}
203
204void
205nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
206{
207 const uint32_t mask = 0x00010001;
208
209 if (enabled)
210 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
211 else
212 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
213}
214
215struct nouveau_channel *
216nv50_graph_channel(struct drm_device *dev)
217{
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 uint32_t inst;
220 int i;
221
a51a3bf5
MM		 222 /* Be sure we're not in the middle of a context switch or bad things
223 * will happen, such as unloading the wrong pgraph context.
224 */
4b5c152a 225 if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
a51a3bf5
MM		 226 NV_ERROR(dev, "Ctxprog is still running\n");
227
6ee73861
BS		 228 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
229 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
230 return NULL;
231 inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
232
233 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133 234 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
6ee73861 235
a8eaebc6 236 if (chan && chan->ramin && chan->ramin->vinst == inst)
6ee73861
BS		 237 return chan;
238 }
239
240 return NULL;
241}
242
243int
244nv50_graph_create_context(struct nouveau_channel *chan)
245{
246 struct drm_device *dev = chan->dev;
247 struct drm_nouveau_private *dev_priv = dev->dev_private;
a8eaebc6 248 struct nouveau_gpuobj *ramin = chan->ramin;
d5f3c90d 249 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
ec91db26 250 struct nouveau_grctx ctx = {};
6ee73861
BS		 251 int hdr, ret;
252
253 NV_DEBUG(dev, "ch%d\n", chan->id);
254
3052be2c 255 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
a8eaebc6
BS		 256 NVOBJ_FLAG_ZERO_ALLOC |
257 NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
6ee73861
BS		 258 if (ret)
259 return ret;
6ee73861 260
ac94a343 261 hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
b3beb167 262 nv_wo32(ramin, hdr + 0x00, 0x00190002);
a8eaebc6 263 nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
b3beb167 264 pgraph->grctx_size - 1);
a8eaebc6 265 nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
b3beb167
BS		 266 nv_wo32(ramin, hdr + 0x0c, 0);
267 nv_wo32(ramin, hdr + 0x10, 0);
268 nv_wo32(ramin, hdr + 0x14, 0x00010000);
6ee73861 269
ec91db26
BS		 270 ctx.dev = chan->dev;
271 ctx.mode = NOUVEAU_GRCTX_VALS;
a8eaebc6 272 ctx.data = chan->ramin_grctx;
ec91db26
BS		 273 nv50_grctx_init(&ctx);
274
a8eaebc6 275 nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
6ee73861 276
f56cb86f 277 dev_priv->engine.instmem.flush(dev);
4c136142 278 atomic_inc(&chan->vm->pgraph_refs);
6ee73861
BS		 279 return 0;
280}
281
282void
283nv50_graph_destroy_context(struct nouveau_channel *chan)
284{
285 struct drm_device *dev = chan->dev;
286 struct drm_nouveau_private *dev_priv = dev->dev_private;
3945e475 287 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
34311c73 288 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
ac94a343 289 int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
3945e475 290 unsigned long flags;
6ee73861
BS		 291
292 NV_DEBUG(dev, "ch%d\n", chan->id);
293
a8eaebc6 294 if (!chan->ramin)
6ee73861
BS		 295 return;
296
3945e475 297 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
34311c73 298 pfifo->reassign(dev, false);
3945e475
FJ		 299 pgraph->fifo_access(dev, false);
300
301 if (pgraph->channel(dev) == chan)
302 pgraph->unload_context(dev);
303
6ee73861 304 for (i = hdr; i < hdr + 24; i += 4)
a8eaebc6 305 nv_wo32(chan->ramin, i, 0);
f56cb86f 306 dev_priv->engine.instmem.flush(dev);
6ee73861 307
3945e475 308 pgraph->fifo_access(dev, true);
34311c73 309 pfifo->reassign(dev, true);
3945e475
FJ		 310 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
311
a8eaebc6 312 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
4c136142
BS		 313
314 atomic_dec(&chan->vm->pgraph_refs);
6ee73861
BS		 315}
316
317static int
318nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
319{
320 uint32_t fifo = nv_rd32(dev, 0x400500);
321
322 nv_wr32(dev, 0x400500, fifo & ~1);
323 nv_wr32(dev, 0x400784, inst);
324 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
325 nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
326 nv_wr32(dev, 0x400040, 0xffffffff);
327 (void)nv_rd32(dev, 0x400040);
328 nv_wr32(dev, 0x400040, 0x00000000);
329 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
330
331 if (nouveau_wait_for_idle(dev))
332 nv_wr32(dev, 0x40032c, inst | (1<<31));
333 nv_wr32(dev, 0x400500, fifo);
334
335 return 0;
336}
337
338int
339nv50_graph_load_context(struct nouveau_channel *chan)
340{
a8eaebc6 341 uint32_t inst = chan->ramin->vinst >> 12;
6ee73861
BS		 342
343 NV_DEBUG(chan->dev, "ch%d\n", chan->id);
344 return nv50_graph_do_load_context(chan->dev, inst);
345}
346
347int
348nv50_graph_unload_context(struct drm_device *dev)
349{
a51a3bf5 350 uint32_t inst;
6ee73861
BS		 351
352 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
353 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
354 return 0;
355 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
356
0a90dc51 357 nouveau_wait_for_idle(dev);
6ee73861
BS		 358 nv_wr32(dev, 0x400784, inst);
359 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
360 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
361 nouveau_wait_for_idle(dev);
6ee73861
BS		 362
363 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
364 return 0;
365}
366
274fec93 367static void
6ee73861
BS		 368nv50_graph_context_switch(struct drm_device *dev)
369{
370 uint32_t inst;
371
372 nv50_graph_unload_context(dev);
373
374 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
375 inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
376 nv50_graph_do_load_context(dev, inst);
377
378 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
379 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
380}
381
382static int
b8c157d3
BS		 383nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
384 u32 class, u32 mthd, u32 data)
6ee73861 385{
a8eaebc6 386 struct nouveau_gpuobj *gpuobj;
6ee73861 387
a8eaebc6
BS		 388 gpuobj = nouveau_ramht_find(chan, data);
389 if (!gpuobj)
6ee73861
BS		 390 return -ENOENT;
391
a8eaebc6 392 if (nouveau_notifier_offset(gpuobj, NULL))
6ee73861
BS		 393 return -EINVAL;
394
a8eaebc6 395 chan->nvsw.vblsem = gpuobj;
6ee73861
BS		 396 chan->nvsw.vblsem_offset = ~0;
397 return 0;
398}
399
400static int
b8c157d3
BS		 401nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
402 u32 class, u32 mthd, u32 data)
6ee73861
BS		 403{
404 if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
405 return -ERANGE;
406
407 chan->nvsw.vblsem_offset = data >> 2;
408 return 0;
409}
410
411static int
b8c157d3
BS		 412nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
413 u32 class, u32 mthd, u32 data)
6ee73861
BS		 414{
415 chan->nvsw.vblsem_rval = data;
416 return 0;
417}
418
419static int
b8c157d3
BS		 420nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
421 u32 class, u32 mthd, u32 data)
6ee73861
BS		 422{
423 struct drm_device *dev = chan->dev;
424 struct drm_nouveau_private *dev_priv = dev->dev_private;
425
426 if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
427 return -EINVAL;
428
042206c0 429 drm_vblank_get(dev, data);
1f6d2de2
FJ		 430
431 chan->nvsw.vblsem_head = data;
6ee73861 432 list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
1f6d2de2 433
6ee73861
BS		 434 return 0;
435}
436
332b242f
FJ		 437static int
438nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
439 u32 class, u32 mthd, u32 data)
440{
d7117e0d 441 nouveau_finish_page_flip(chan, NULL);
332b242f
FJ		 442 return 0;
443}
444
b8c157d3
BS		 445static int
446nv50_graph_register(struct drm_device *dev)
447{
448 struct drm_nouveau_private *dev_priv = dev->dev_private;
449
450 if (dev_priv->engine.graph.registered)
451 return 0;
452
453 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
454 NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
455 NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
456 NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
457 NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
332b242f 458 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
b8c157d3
BS		 459
460 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
461 NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
462 NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
b8c157d3
BS		 463
464 /* tesla */
465 if (dev_priv->chipset == 0x50)
466 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
467 else
468 if (dev_priv->chipset < 0xa0)
469 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
470 else {
471 switch (dev_priv->chipset) {
472 case 0xa0:
473 case 0xaa:
474 case 0xac:
475 NVOBJ_CLASS(dev, 0x8397, GR);
476 break;
477 case 0xa3:
478 case 0xa5:
479 case 0xa8:
480 NVOBJ_CLASS(dev, 0x8597, GR);
481 break;
482 case 0xaf:
483 NVOBJ_CLASS(dev, 0x8697, GR);
484 break;
485 }
486 }
487
aa2c2e80 488 /* compute */
a169f09b
BS		 489 NVOBJ_CLASS(dev, 0x50c0, GR);
490 if (dev_priv->chipset > 0xa0 &&
491 dev_priv->chipset != 0xaa &&
492 dev_priv->chipset != 0xac)
aa2c2e80
BS		 493 NVOBJ_CLASS(dev, 0x85c0, GR);
494
b8c157d3
BS		 495 dev_priv->engine.graph.registered = true;
496 return 0;
497}
56ac7475
BS		 498
499void
500nv50_graph_tlb_flush(struct drm_device *dev)
501{
a11c3198 502 nv50_vm_flush_engine(dev, 0);
56ac7475
BS		 503}
504
505void
2b4cebe4 506nv84_graph_tlb_flush(struct drm_device *dev)
56ac7475
BS		 507{
508 struct drm_nouveau_private *dev_priv = dev->dev_private;
509 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
510 bool idle, timeout = false;
511 unsigned long flags;
512 u64 start;
513 u32 tmp;
514
515 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
516 nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
517
518 start = ptimer->read(dev);
519 do {
520 idle = true;
521
522 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
523 if ((tmp & 7) == 1)
524 idle = false;
525 }
526
527 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
528 if ((tmp & 7) == 1)
529 idle = false;
530 }
531
532 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
533 if ((tmp & 7) == 1)
534 idle = false;
535 }
536 } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
537
538 if (timeout) {
539 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
540 "0x%08x 0x%08x 0x%08x 0x%08x\n",
541 nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
542 nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
543 }
544
a11c3198 545 nv50_vm_flush_engine(dev, 0);
56ac7475
BS		 546
547 nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
548 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
549}
274fec93 550
f9ec8f6c 551static struct nouveau_enum nv50_mp_exec_error_names[] = {
bb9b18a3
BS		 552 { 3, "STACK_UNDERFLOW", NULL },
553 { 4, "QUADON_ACTIVE", NULL },
554 { 8, "TIMEOUT", NULL },
555 { 0x10, "INVALID_OPCODE", NULL },
556 { 0x40, "BREAKPOINT", NULL },
274fec93
BS		 557 {}
558};
559
560static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
561 { 0x00000001, "NOTIFY" },
562 { 0x00000002, "IN" },
563 { 0x00000004, "OUT" },
564 {}
565};
566
567static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
568 { 0x00000001, "FAULT" },
569 {}
570};
571
572static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
573 { 0x00000001, "FAULT" },
574 {}
575};
576
577static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
578 { 0x00000001, "FAULT" },
579 {}
580};
581
582/* There must be a *lot* of these. Will take some time to gather them up. */
6effe393 583struct nouveau_enum nv50_data_error_names[] = {
bb9b18a3
BS		 584 { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
585 { 0x00000004, "INVALID_VALUE", NULL },
586 { 0x00000005, "INVALID_ENUM", NULL },
587 { 0x00000008, "INVALID_OBJECT", NULL },
588 { 0x00000009, "READ_ONLY_OBJECT", NULL },
589 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
590 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
591 { 0x0000000c, "INVALID_BITFIELD", NULL },
592 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
593 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
594 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
595 { 0x00000010, "RT_DOUBLE_BIND", NULL },
596 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
597 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
598 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
599 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
600 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
601 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
602 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
603 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
604 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
605 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
606 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
607 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
608 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
609 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
610 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
611 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
612 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
613 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
614 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
615 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
616 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
617 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
618 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
619 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
620 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
621 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
622 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
623 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
624 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
274fec93
BS		 625 {}
626};
627
628static struct nouveau_bitfield nv50_graph_intr[] = {
629 { 0x00000001, "NOTIFY" },
630 { 0x00000002, "COMPUTE_QUERY" },
631 { 0x00000010, "ILLEGAL_MTHD" },
632 { 0x00000020, "ILLEGAL_CLASS" },
633 { 0x00000040, "DOUBLE_NOTIFY" },
634 { 0x00001000, "CONTEXT_SWITCH" },
635 { 0x00010000, "BUFFER_NOTIFY" },
636 { 0x00100000, "DATA_ERROR" },
637 { 0x00200000, "TRAP" },
638 { 0x01000000, "SINGLE_STEP" },
639 {}
640};
641
642static void
643nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
644{
645 struct drm_nouveau_private *dev_priv = dev->dev_private;
646 uint32_t units = nv_rd32(dev, 0x1540);
647 uint32_t addr, mp10, status, pc, oplow, ophigh;
648 int i;
649 int mps = 0;
650 for (i = 0; i < 4; i++) {
651 if (!(units & 1 << (i+24)))
652 continue;
653 if (dev_priv->chipset < 0xa0)
654 addr = 0x408200 + (tpid << 12) + (i << 7);
655 else
656 addr = 0x408100 + (tpid << 11) + (i << 7);
657 mp10 = nv_rd32(dev, addr + 0x10);
658 status = nv_rd32(dev, addr + 0x14);
659 if (!status)
660 continue;
661 if (display) {
662 nv_rd32(dev, addr + 0x20);
663 pc = nv_rd32(dev, addr + 0x24);
664 oplow = nv_rd32(dev, addr + 0x70);
0b89a072 665 ophigh = nv_rd32(dev, addr + 0x74);
274fec93
BS		 666 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
667 "TP %d MP %d: ", tpid, i);
668 nouveau_enum_print(nv50_mp_exec_error_names, status);
669 printk(" at %06x warp %d, opcode %08x %08x\n",
670 pc&0xffffff, pc >> 24,
671 oplow, ophigh);
672 }
673 nv_wr32(dev, addr + 0x10, mp10);
674 nv_wr32(dev, addr + 0x14, 0);
675 mps++;
676 }
677 if (!mps && display)
678 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
679 "No MPs claiming errors?\n", tpid);
680}
681
682static void
683nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
684 uint32_t ustatus_new, int display, const char *name)
685{
686 struct drm_nouveau_private *dev_priv = dev->dev_private;
687 int tps = 0;
688 uint32_t units = nv_rd32(dev, 0x1540);
689 int i, r;
690 uint32_t ustatus_addr, ustatus;
691 for (i = 0; i < 16; i++) {
692 if (!(units & (1 << i)))
693 continue;
694 if (dev_priv->chipset < 0xa0)
695 ustatus_addr = ustatus_old + (i << 12);
696 else
697 ustatus_addr = ustatus_new + (i << 11);
698 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
699 if (!ustatus)
700 continue;
701 tps++;
702 switch (type) {
703 case 6: /* texture error... unknown for now */
274fec93
BS		 704 if (display) {
705 NV_ERROR(dev, "magic set %d:\n", i);
706 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
707 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
708 nv_rd32(dev, r));
709 }
710 break;
711 case 7: /* MP error */
712 if (ustatus & 0x00010000) {
713 nv50_pgraph_mp_trap(dev, i, display);
714 ustatus &= ~0x00010000;
715 }
716 break;
717 case 8: /* TPDMA error */
718 {
719 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
720 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
721 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
722 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
723 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
724 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
725 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
274fec93
BS		 726 /* 2d engine destination */
727 if (ustatus & 0x00000010) {
728 if (display) {
729 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
730 i, e14, e10);
731 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
732 i, e0c, e18, e1c, e20, e24);
733 }
734 ustatus &= ~0x00000010;
735 }
736 /* Render target */
737 if (ustatus & 0x00000040) {
738 if (display) {
739 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
740 i, e14, e10);
741 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
742 i, e0c, e18, e1c, e20, e24);
743 }
744 ustatus &= ~0x00000040;
745 }
746 /* CUDA memory: l[], g[] or stack. */
747 if (ustatus & 0x00000080) {
748 if (display) {
749 if (e18 & 0x80000000) {
750 /* g[] read fault? */
751 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
752 i, e14, e10 | ((e18 >> 24) & 0x1f));
753 e18 &= ~0x1f000000;
754 } else if (e18 & 0xc) {
755 /* g[] write fault? */
756 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
757 i, e14, e10 | ((e18 >> 7) & 0x1f));
758 e18 &= ~0x00000f80;
759 } else {
760 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
761 i, e14, e10);
762 }
763 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
764 i, e0c, e18, e1c, e20, e24);
765 }
766 ustatus &= ~0x00000080;
767 }
768 }
769 break;
770 }
771 if (ustatus) {
772 if (display)
773 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
774 }
775 nv_wr32(dev, ustatus_addr, 0xc0000000);
776 }
777
778 if (!tps && display)
779 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
780}
781
782static int
783nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
784{
785 u32 status = nv_rd32(dev, 0x400108);
786 u32 ustatus;
787
788 if (!status && display) {
789 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
790 return 1;
791 }
792
793 /* DISPATCH: Relays commands to other units and handles NOTIFY,
794 * COND, QUERY. If you get a trap from it, the command is still stuck
795 * in DISPATCH and you need to do something about it. */
796 if (status & 0x001) {
797 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
798 if (!ustatus && display) {
799 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
800 }
801
802 nv_wr32(dev, 0x400500, 0x00000000);
803
804 /* Known to be triggered by screwed up NOTIFY and COND... */
805 if (ustatus & 0x00000001) {
806 u32 addr = nv_rd32(dev, 0x400808);
807 u32 subc = (addr & 0x00070000) >> 16;
808 u32 mthd = (addr & 0x00001ffc);
809 u32 datal = nv_rd32(dev, 0x40080c);
810 u32 datah = nv_rd32(dev, 0x400810);
811 u32 class = nv_rd32(dev, 0x400814);
812 u32 r848 = nv_rd32(dev, 0x400848);
813
814 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
815 if (display && (addr & 0x80000000)) {
816 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
817 "subc %d class 0x%04x mthd 0x%04x "
818 "data 0x%08x%08x "
819 "400808 0x%08x 400848 0x%08x\n",
820 chid, inst, subc, class, mthd, datah,
821 datal, addr, r848);
822 } else
823 if (display) {
824 NV_INFO(dev, "PGRAPH - no stuck command?\n");
825 }
826
827 nv_wr32(dev, 0x400808, 0);
828 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
829 nv_wr32(dev, 0x400848, 0);
830 ustatus &= ~0x00000001;
831 }
832
833 if (ustatus & 0x00000002) {
834 u32 addr = nv_rd32(dev, 0x40084c);
835 u32 subc = (addr & 0x00070000) >> 16;
836 u32 mthd = (addr & 0x00001ffc);
837 u32 data = nv_rd32(dev, 0x40085c);
838 u32 class = nv_rd32(dev, 0x400814);
839
840 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
841 if (display && (addr & 0x80000000)) {
842 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
843 "subc %d class 0x%04x mthd 0x%04x "
844 "data 0x%08x 40084c 0x%08x\n",
845 chid, inst, subc, class, mthd,
846 data, addr);
847 } else
848 if (display) {
849 NV_INFO(dev, "PGRAPH - no stuck command?\n");
850 }
851
852 nv_wr32(dev, 0x40084c, 0);
853 ustatus &= ~0x00000002;
854 }
855
856 if (ustatus && display) {
857 NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
858 "0x%08x)\n", ustatus);
859 }
860
861 nv_wr32(dev, 0x400804, 0xc0000000);
862 nv_wr32(dev, 0x400108, 0x001);
863 status &= ~0x001;
864 if (!status)
865 return 0;
866 }
867
868 /* M2MF: Memory to memory copy engine. */
869 if (status & 0x002) {
870 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
871 if (display) {
872 NV_INFO(dev, "PGRAPH - TRAP_M2MF");
873 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
874 printk("\n");
875 NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
876 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
877 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
878
879 }
880
881 /* No sane way found yet -- just reset the bugger. */
882 nv_wr32(dev, 0x400040, 2);
883 nv_wr32(dev, 0x400040, 0);
884 nv_wr32(dev, 0x406800, 0xc0000000);
885 nv_wr32(dev, 0x400108, 0x002);
886 status &= ~0x002;
887 }
888
889 /* VFETCH: Fetches data from vertex buffers. */
890 if (status & 0x004) {
891 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
892 if (display) {
893 NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
894 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
895 printk("\n");
896 NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
897 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
898 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
899 }
900
901 nv_wr32(dev, 0x400c04, 0xc0000000);
902 nv_wr32(dev, 0x400108, 0x004);
903 status &= ~0x004;
904 }
905
906 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
907 if (status & 0x008) {
908 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
909 if (display) {
910 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
911 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
912 printk("\n");
913 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
914 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
915 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
916
917 }
918
919 /* No sane way found yet -- just reset the bugger. */
920 nv_wr32(dev, 0x400040, 0x80);
921 nv_wr32(dev, 0x400040, 0);
922 nv_wr32(dev, 0x401800, 0xc0000000);
923 nv_wr32(dev, 0x400108, 0x008);
924 status &= ~0x008;
925 }
926
927 /* CCACHE: Handles code and c[] caches and fills them. */
928 if (status & 0x010) {
929 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
930 if (display) {
931 NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
932 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
933 printk("\n");
934 NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
935 " %08x %08x %08x\n",
4dcf905c
MS		 936 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
937 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
938 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
939 nv_rd32(dev, 0x40501c));
274fec93
BS		 940
941 }
942
943 nv_wr32(dev, 0x405018, 0xc0000000);
944 nv_wr32(dev, 0x400108, 0x010);
945 status &= ~0x010;
946 }
947
948 /* Unknown, not seen yet... 0x402000 is the only trap status reg
949 * remaining, so try to handle it anyway. Perhaps related to that
950 * unknown DMA slot on tesla? */
951 if (status & 0x20) {
952 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
953 if (display)
954 NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
955 nv_wr32(dev, 0x402000, 0xc0000000);
956 /* no status modifiction on purpose */
957 }
958
959 /* TEXTURE: CUDA texturing units */
960 if (status & 0x040) {
961 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
962 "PGRAPH - TRAP_TEXTURE");
963 nv_wr32(dev, 0x400108, 0x040);
964 status &= ~0x040;
965 }
966
967 /* MP: CUDA execution engines. */
968 if (status & 0x080) {
969 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
970 "PGRAPH - TRAP_MP");
971 nv_wr32(dev, 0x400108, 0x080);
972 status &= ~0x080;
973 }
974
975 /* TPDMA: Handles TP-initiated uncached memory accesses:
976 * l[], g[], stack, 2d surfaces, render targets. */
977 if (status & 0x100) {
978 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
979 "PGRAPH - TRAP_TPDMA");
980 nv_wr32(dev, 0x400108, 0x100);
981 status &= ~0x100;
982 }
983
984 if (status) {
985 if (display)
986 NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
987 nv_wr32(dev, 0x400108, status);
988 }
989
990 return 1;
991}
992
993static int
994nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
995{
996 struct drm_nouveau_private *dev_priv = dev->dev_private;
997 struct nouveau_channel *chan;
998 unsigned long flags;
999 int i;
1000
1001 spin_lock_irqsave(&dev_priv->channels.lock, flags);
1002 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
1003 chan = dev_priv->channels.ptr[i];
1004 if (!chan || !chan->ramin)
1005 continue;
1006
1007 if (inst == chan->ramin->vinst)
1008 break;
1009 }
1010 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
1011 return i;
1012}
1013
1014static void
1015nv50_graph_isr(struct drm_device *dev)
1016{
1017 u32 stat;
1018
1019 while ((stat = nv_rd32(dev, 0x400100))) {
1020 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
1021 u32 chid = nv50_graph_isr_chid(dev, inst);
1022 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1023 u32 subc = (addr & 0x00070000) >> 16;
1024 u32 mthd = (addr & 0x00001ffc);
1025 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1026 u32 class = nv_rd32(dev, 0x400814);
1027 u32 show = stat;
1028
1029 if (stat & 0x00000010) {
1030 if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
1031 mthd, data))
1032 show &= ~0x00000010;
1033 }
1034
1035 if (stat & 0x00001000) {
1036 nv_wr32(dev, 0x400500, 0x00000000);
1037 nv_wr32(dev, 0x400100, 0x00001000);
1038 nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
1039 nv50_graph_context_switch(dev);
1040 stat &= ~0x00001000;
1041 show &= ~0x00001000;
1042 }
1043
1044 show = (show && nouveau_ratelimit()) ? show : 0;
1045
1046 if (show & 0x00100000) {
1047 u32 ecode = nv_rd32(dev, 0x400110);
1048 NV_INFO(dev, "PGRAPH - DATA_ERROR ");
1049 nouveau_enum_print(nv50_data_error_names, ecode);
1050 printk("\n");
1051 }
1052
1053 if (stat & 0x00200000) {
1054 if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1055 show &= ~0x00200000;
1056 }
1057
1058 nv_wr32(dev, 0x400100, stat);
1059 nv_wr32(dev, 0x400500, 0x00010001);
1060
1061 if (show) {
1062 NV_INFO(dev, "PGRAPH -");
1063 nouveau_bitfield_print(nv50_graph_intr, show);
1064 printk("\n");
1065 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1066 "class 0x%04x mthd 0x%04x data 0x%08x\n",
1067 chid, inst, subc, class, mthd, data);
6fdb383e 1068 nv50_fb_vm_trap(dev, 1);
274fec93
BS		 1069 }
1070 }
1071
1072 if (nv_rd32(dev, 0x400824) & (1 << 31))
1073 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1074}
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