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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2007 Ben Skeggs. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm.h" | |
29 | #include "nouveau_drv.h" | |
a8eaebc6 | 30 | #include "nouveau_ramht.h" |
332b242f | 31 | #include "nouveau_dma.h" |
a11c3198 | 32 | #include "nouveau_vm.h" |
332b242f | 33 | #include "nv50_evo.h" |
6ee73861 | 34 | |
2703c21a BS |
35 | struct nv50_graph_engine { |
36 | struct nouveau_exec_engine base; | |
37 | u32 ctxprog[512]; | |
38 | u32 ctxprog_size; | |
39 | u32 grctx_size; | |
40 | }; | |
41 | ||
42 | static void | |
43 | nv50_graph_fifo_access(struct drm_device *dev, bool enabled) | |
44 | { | |
45 | const uint32_t mask = 0x00010001; | |
46 | ||
47 | if (enabled) | |
48 | nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask); | |
49 | else | |
50 | nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask); | |
51 | } | |
52 | ||
53 | static struct nouveau_channel * | |
54 | nv50_graph_channel(struct drm_device *dev) | |
55 | { | |
56 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
57 | uint32_t inst; | |
58 | int i; | |
59 | ||
60 | /* Be sure we're not in the middle of a context switch or bad things | |
61 | * will happen, such as unloading the wrong pgraph context. | |
62 | */ | |
63 | if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) | |
64 | NV_ERROR(dev, "Ctxprog is still running\n"); | |
65 | ||
66 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); | |
67 | if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) | |
68 | return NULL; | |
69 | inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12; | |
70 | ||
71 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
72 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; | |
73 | ||
74 | if (chan && chan->ramin && chan->ramin->vinst == inst) | |
75 | return chan; | |
76 | } | |
77 | ||
78 | return NULL; | |
79 | } | |
80 | ||
81 | static int | |
82 | nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst) | |
83 | { | |
84 | uint32_t fifo = nv_rd32(dev, 0x400500); | |
85 | ||
86 | nv_wr32(dev, 0x400500, fifo & ~1); | |
87 | nv_wr32(dev, 0x400784, inst); | |
88 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40); | |
89 | nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11); | |
90 | nv_wr32(dev, 0x400040, 0xffffffff); | |
91 | (void)nv_rd32(dev, 0x400040); | |
92 | nv_wr32(dev, 0x400040, 0x00000000); | |
93 | nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1); | |
94 | ||
95 | if (nouveau_wait_for_idle(dev)) | |
96 | nv_wr32(dev, 0x40032c, inst | (1<<31)); | |
97 | nv_wr32(dev, 0x400500, fifo); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | static int | |
103 | nv50_graph_unload_context(struct drm_device *dev) | |
104 | { | |
105 | uint32_t inst; | |
106 | ||
107 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); | |
108 | if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) | |
109 | return 0; | |
110 | inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; | |
111 | ||
112 | nouveau_wait_for_idle(dev); | |
113 | nv_wr32(dev, 0x400784, inst); | |
114 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); | |
115 | nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01); | |
116 | nouveau_wait_for_idle(dev); | |
117 | ||
118 | nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst); | |
119 | return 0; | |
120 | } | |
b8c157d3 | 121 | |
6d6538a0 BS |
122 | static int |
123 | nv50_graph_init(struct drm_device *dev, int engine) | |
6ee73861 | 124 | { |
304424e1 | 125 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
6d6538a0 BS |
126 | struct nv50_graph_engine *pgraph = nv_engine(dev, engine); |
127 | u32 units = nv_rd32(dev, 0x001540); | |
304424e1 MK |
128 | int i; |
129 | ||
6ee73861 BS |
130 | NV_DEBUG(dev, "\n"); |
131 | ||
6d6538a0 | 132 | /* master reset */ |
dce411cd BS |
133 | nv_mask(dev, 0x000200, 0x00201000, 0x00000000); |
134 | nv_mask(dev, 0x000200, 0x00201000, 0x00201000); | |
6d6538a0 BS |
135 | nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */ |
136 | ||
137 | /* reset/enable traps and interrupts */ | |
6ee73861 BS |
138 | nv_wr32(dev, 0x400804, 0xc0000000); |
139 | nv_wr32(dev, 0x406800, 0xc0000000); | |
140 | nv_wr32(dev, 0x400c04, 0xc0000000); | |
716abaa8 | 141 | nv_wr32(dev, 0x401800, 0xc0000000); |
6ee73861 BS |
142 | nv_wr32(dev, 0x405018, 0xc0000000); |
143 | nv_wr32(dev, 0x402000, 0xc0000000); | |
304424e1 | 144 | for (i = 0; i < 16; i++) { |
6d6538a0 BS |
145 | if (!(units & (1 << i))) |
146 | continue; | |
147 | ||
148 | if (dev_priv->chipset < 0xa0) { | |
149 | nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000); | |
150 | nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000); | |
151 | nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000); | |
152 | } else { | |
153 | nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000); | |
154 | nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000); | |
155 | nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000); | |
304424e1 MK |
156 | } |
157 | } | |
158 | ||
6ee73861 | 159 | nv_wr32(dev, 0x400108, 0xffffffff); |
6d6538a0 BS |
160 | nv_wr32(dev, 0x400138, 0xffffffff); |
161 | nv_wr32(dev, 0x400100, 0xffffffff); | |
162 | nv_wr32(dev, 0x40013c, 0xffffffff); | |
6ee73861 | 163 | nv_wr32(dev, 0x400500, 0x00010001); |
6ee73861 | 164 | |
6d6538a0 BS |
165 | /* upload context program, initialise ctxctl defaults */ |
166 | nv_wr32(dev, 0x400324, 0x00000000); | |
167 | for (i = 0; i < pgraph->ctxprog_size; i++) | |
168 | nv_wr32(dev, 0x400328, pgraph->ctxprog[i]); | |
169 | nv_wr32(dev, 0x400824, 0x00000000); | |
170 | nv_wr32(dev, 0x400828, 0x00000000); | |
171 | nv_wr32(dev, 0x40082c, 0x00000000); | |
172 | nv_wr32(dev, 0x400830, 0x00000000); | |
173 | nv_wr32(dev, 0x400724, 0x00000000); | |
174 | nv_wr32(dev, 0x40032c, 0x00000000); | |
175 | nv_wr32(dev, 0x400320, 4); /* CTXCTL_CMD = NEWCTXDMA */ | |
176 | ||
177 | /* some unknown zcull magic */ | |
562af10c BS |
178 | switch (dev_priv->chipset & 0xf0) { |
179 | case 0x50: | |
180 | case 0x80: | |
181 | case 0x90: | |
182 | nv_wr32(dev, 0x402ca8, 0x00000800); | |
183 | break; | |
184 | case 0xa0: | |
185 | default: | |
186 | nv_wr32(dev, 0x402cc0, 0x00000000); | |
187 | if (dev_priv->chipset == 0xa0 || | |
188 | dev_priv->chipset == 0xaa || | |
189 | dev_priv->chipset == 0xac) { | |
190 | nv_wr32(dev, 0x402ca8, 0x00000802); | |
191 | } else { | |
192 | nv_wr32(dev, 0x402cc0, 0x00000000); | |
193 | nv_wr32(dev, 0x402ca8, 0x00000002); | |
194 | } | |
195 | ||
196 | break; | |
197 | } | |
198 | ||
199 | /* zero out zcull regions */ | |
200 | for (i = 0; i < 8; i++) { | |
201 | nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000); | |
202 | nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000); | |
203 | nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000); | |
204 | nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000); | |
205 | } | |
6ee73861 BS |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
2703c21a | 210 | static int |
6c320fef | 211 | nv50_graph_fini(struct drm_device *dev, int engine, bool suspend) |
6ee73861 | 212 | { |
274fec93 | 213 | nv_wr32(dev, 0x40013c, 0x00000000); |
2703c21a | 214 | return 0; |
6ee73861 BS |
215 | } |
216 | ||
2703c21a BS |
217 | static int |
218 | nv50_graph_context_new(struct nouveau_channel *chan, int engine) | |
6ee73861 BS |
219 | { |
220 | struct drm_device *dev = chan->dev; | |
221 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a8eaebc6 | 222 | struct nouveau_gpuobj *ramin = chan->ramin; |
2703c21a BS |
223 | struct nouveau_gpuobj *grctx = NULL; |
224 | struct nv50_graph_engine *pgraph = nv_engine(dev, engine); | |
6ee73861 BS |
225 | int hdr, ret; |
226 | ||
227 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
228 | ||
2703c21a | 229 | ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0, |
a8eaebc6 | 230 | NVOBJ_FLAG_ZERO_ALLOC | |
2703c21a | 231 | NVOBJ_FLAG_ZERO_FREE, &grctx); |
6ee73861 BS |
232 | if (ret) |
233 | return ret; | |
6ee73861 | 234 | |
ac94a343 | 235 | hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; |
b3beb167 | 236 | nv_wo32(ramin, hdr + 0x00, 0x00190002); |
2703c21a BS |
237 | nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1); |
238 | nv_wo32(ramin, hdr + 0x08, grctx->vinst); | |
b3beb167 BS |
239 | nv_wo32(ramin, hdr + 0x0c, 0); |
240 | nv_wo32(ramin, hdr + 0x10, 0); | |
241 | nv_wo32(ramin, hdr + 0x14, 0x00010000); | |
6ee73861 | 242 | |
d58086de | 243 | nv50_grctx_fill(dev, grctx); |
2703c21a | 244 | nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12); |
6ee73861 | 245 | |
f56cb86f | 246 | dev_priv->engine.instmem.flush(dev); |
2703c21a BS |
247 | |
248 | atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]); | |
249 | chan->engctx[NVOBJ_ENGINE_GR] = grctx; | |
6ee73861 BS |
250 | return 0; |
251 | } | |
252 | ||
2703c21a BS |
253 | static void |
254 | nv50_graph_context_del(struct nouveau_channel *chan, int engine) | |
6ee73861 | 255 | { |
2703c21a | 256 | struct nouveau_gpuobj *grctx = chan->engctx[engine]; |
6ee73861 BS |
257 | struct drm_device *dev = chan->dev; |
258 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
ac94a343 | 259 | int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20; |
3945e475 | 260 | unsigned long flags; |
6ee73861 BS |
261 | |
262 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
263 | ||
a8eaebc6 | 264 | if (!chan->ramin) |
6ee73861 BS |
265 | return; |
266 | ||
3945e475 | 267 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
67b342ef | 268 | nv_wr32(dev, NV03_PFIFO_CACHES, 0); |
2703c21a | 269 | nv50_graph_fifo_access(dev, false); |
3945e475 | 270 | |
2703c21a BS |
271 | if (nv50_graph_channel(dev) == chan) |
272 | nv50_graph_unload_context(dev); | |
3945e475 | 273 | |
6ee73861 | 274 | for (i = hdr; i < hdr + 24; i += 4) |
a8eaebc6 | 275 | nv_wo32(chan->ramin, i, 0); |
f56cb86f | 276 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 277 | |
2703c21a | 278 | nv50_graph_fifo_access(dev, true); |
67b342ef | 279 | nv_wr32(dev, NV03_PFIFO_CACHES, 1); |
3945e475 FJ |
280 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
281 | ||
2703c21a | 282 | nouveau_gpuobj_ref(NULL, &grctx); |
4c136142 | 283 | |
2703c21a BS |
284 | atomic_dec(&chan->vm->engref[engine]); |
285 | chan->engctx[engine] = NULL; | |
6ee73861 BS |
286 | } |
287 | ||
288 | static int | |
2703c21a BS |
289 | nv50_graph_object_new(struct nouveau_channel *chan, int engine, |
290 | u32 handle, u16 class) | |
4ea52f89 BS |
291 | { |
292 | struct drm_device *dev = chan->dev; | |
293 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
294 | struct nouveau_gpuobj *obj = NULL; | |
295 | int ret; | |
296 | ||
297 | ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj); | |
298 | if (ret) | |
299 | return ret; | |
300 | obj->engine = 1; | |
301 | obj->class = class; | |
302 | ||
303 | nv_wo32(obj, 0x00, class); | |
304 | nv_wo32(obj, 0x04, 0x00000000); | |
305 | nv_wo32(obj, 0x08, 0x00000000); | |
306 | nv_wo32(obj, 0x0c, 0x00000000); | |
307 | dev_priv->engine.instmem.flush(dev); | |
308 | ||
309 | ret = nouveau_ramht_insert(chan, handle, obj); | |
310 | nouveau_gpuobj_ref(NULL, &obj); | |
311 | return ret; | |
312 | } | |
313 | ||
274fec93 | 314 | static void |
6ee73861 BS |
315 | nv50_graph_context_switch(struct drm_device *dev) |
316 | { | |
317 | uint32_t inst; | |
318 | ||
319 | nv50_graph_unload_context(dev); | |
320 | ||
321 | inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT); | |
322 | inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE; | |
323 | nv50_graph_do_load_context(dev, inst); | |
324 | ||
325 | nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, | |
326 | NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH); | |
327 | } | |
328 | ||
2703c21a BS |
329 | static void |
330 | nv50_graph_tlb_flush(struct drm_device *dev, int engine) | |
56ac7475 | 331 | { |
a11c3198 | 332 | nv50_vm_flush_engine(dev, 0); |
56ac7475 BS |
333 | } |
334 | ||
2703c21a BS |
335 | static void |
336 | nv84_graph_tlb_flush(struct drm_device *dev, int engine) | |
56ac7475 BS |
337 | { |
338 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
339 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
340 | bool idle, timeout = false; | |
341 | unsigned long flags; | |
342 | u64 start; | |
343 | u32 tmp; | |
344 | ||
345 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | |
346 | nv_mask(dev, 0x400500, 0x00000001, 0x00000000); | |
347 | ||
348 | start = ptimer->read(dev); | |
349 | do { | |
350 | idle = true; | |
351 | ||
352 | for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) { | |
353 | if ((tmp & 7) == 1) | |
354 | idle = false; | |
355 | } | |
356 | ||
357 | for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) { | |
358 | if ((tmp & 7) == 1) | |
359 | idle = false; | |
360 | } | |
361 | ||
362 | for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) { | |
363 | if ((tmp & 7) == 1) | |
364 | idle = false; | |
365 | } | |
366 | } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000)); | |
367 | ||
368 | if (timeout) { | |
369 | NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: " | |
370 | "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
371 | nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380), | |
372 | nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388)); | |
373 | } | |
374 | ||
a11c3198 | 375 | nv50_vm_flush_engine(dev, 0); |
56ac7475 BS |
376 | |
377 | nv_mask(dev, 0x400500, 0x00000001, 0x00000001); | |
378 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
379 | } | |
274fec93 | 380 | |
f9ec8f6c | 381 | static struct nouveau_enum nv50_mp_exec_error_names[] = { |
bb9b18a3 BS |
382 | { 3, "STACK_UNDERFLOW", NULL }, |
383 | { 4, "QUADON_ACTIVE", NULL }, | |
384 | { 8, "TIMEOUT", NULL }, | |
385 | { 0x10, "INVALID_OPCODE", NULL }, | |
386 | { 0x40, "BREAKPOINT", NULL }, | |
274fec93 BS |
387 | {} |
388 | }; | |
389 | ||
390 | static struct nouveau_bitfield nv50_graph_trap_m2mf[] = { | |
391 | { 0x00000001, "NOTIFY" }, | |
392 | { 0x00000002, "IN" }, | |
393 | { 0x00000004, "OUT" }, | |
394 | {} | |
395 | }; | |
396 | ||
397 | static struct nouveau_bitfield nv50_graph_trap_vfetch[] = { | |
398 | { 0x00000001, "FAULT" }, | |
399 | {} | |
400 | }; | |
401 | ||
402 | static struct nouveau_bitfield nv50_graph_trap_strmout[] = { | |
403 | { 0x00000001, "FAULT" }, | |
404 | {} | |
405 | }; | |
406 | ||
407 | static struct nouveau_bitfield nv50_graph_trap_ccache[] = { | |
408 | { 0x00000001, "FAULT" }, | |
409 | {} | |
410 | }; | |
411 | ||
412 | /* There must be a *lot* of these. Will take some time to gather them up. */ | |
6effe393 | 413 | struct nouveau_enum nv50_data_error_names[] = { |
bb9b18a3 BS |
414 | { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL }, |
415 | { 0x00000004, "INVALID_VALUE", NULL }, | |
416 | { 0x00000005, "INVALID_ENUM", NULL }, | |
417 | { 0x00000008, "INVALID_OBJECT", NULL }, | |
418 | { 0x00000009, "READ_ONLY_OBJECT", NULL }, | |
419 | { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, | |
420 | { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, | |
421 | { 0x0000000c, "INVALID_BITFIELD", NULL }, | |
422 | { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, | |
423 | { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, | |
424 | { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, | |
425 | { 0x00000010, "RT_DOUBLE_BIND", NULL }, | |
426 | { 0x00000011, "RT_TYPES_MISMATCH", NULL }, | |
427 | { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, | |
428 | { 0x00000015, "FP_TOO_FEW_REGS", NULL }, | |
429 | { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, | |
430 | { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, | |
431 | { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, | |
432 | { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, | |
433 | { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, | |
434 | { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, | |
435 | { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, | |
436 | { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, | |
437 | { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, | |
438 | { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, | |
439 | { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, | |
440 | { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, | |
441 | { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, | |
442 | { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, | |
443 | { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, | |
444 | { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, | |
445 | { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, | |
446 | { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, | |
447 | { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, | |
448 | { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, | |
449 | { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, | |
450 | { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, | |
451 | { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, | |
452 | { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, | |
453 | { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, | |
454 | { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, | |
274fec93 BS |
455 | {} |
456 | }; | |
457 | ||
458 | static struct nouveau_bitfield nv50_graph_intr[] = { | |
459 | { 0x00000001, "NOTIFY" }, | |
460 | { 0x00000002, "COMPUTE_QUERY" }, | |
461 | { 0x00000010, "ILLEGAL_MTHD" }, | |
462 | { 0x00000020, "ILLEGAL_CLASS" }, | |
463 | { 0x00000040, "DOUBLE_NOTIFY" }, | |
464 | { 0x00001000, "CONTEXT_SWITCH" }, | |
465 | { 0x00010000, "BUFFER_NOTIFY" }, | |
466 | { 0x00100000, "DATA_ERROR" }, | |
467 | { 0x00200000, "TRAP" }, | |
468 | { 0x01000000, "SINGLE_STEP" }, | |
469 | {} | |
470 | }; | |
471 | ||
472 | static void | |
473 | nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display) | |
474 | { | |
475 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
476 | uint32_t units = nv_rd32(dev, 0x1540); | |
477 | uint32_t addr, mp10, status, pc, oplow, ophigh; | |
478 | int i; | |
479 | int mps = 0; | |
480 | for (i = 0; i < 4; i++) { | |
481 | if (!(units & 1 << (i+24))) | |
482 | continue; | |
483 | if (dev_priv->chipset < 0xa0) | |
484 | addr = 0x408200 + (tpid << 12) + (i << 7); | |
485 | else | |
486 | addr = 0x408100 + (tpid << 11) + (i << 7); | |
487 | mp10 = nv_rd32(dev, addr + 0x10); | |
488 | status = nv_rd32(dev, addr + 0x14); | |
489 | if (!status) | |
490 | continue; | |
491 | if (display) { | |
492 | nv_rd32(dev, addr + 0x20); | |
493 | pc = nv_rd32(dev, addr + 0x24); | |
494 | oplow = nv_rd32(dev, addr + 0x70); | |
0b89a072 | 495 | ophigh = nv_rd32(dev, addr + 0x74); |
274fec93 BS |
496 | NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - " |
497 | "TP %d MP %d: ", tpid, i); | |
498 | nouveau_enum_print(nv50_mp_exec_error_names, status); | |
499 | printk(" at %06x warp %d, opcode %08x %08x\n", | |
500 | pc&0xffffff, pc >> 24, | |
501 | oplow, ophigh); | |
502 | } | |
503 | nv_wr32(dev, addr + 0x10, mp10); | |
504 | nv_wr32(dev, addr + 0x14, 0); | |
505 | mps++; | |
506 | } | |
507 | if (!mps && display) | |
508 | NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: " | |
509 | "No MPs claiming errors?\n", tpid); | |
510 | } | |
511 | ||
512 | static void | |
513 | nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old, | |
514 | uint32_t ustatus_new, int display, const char *name) | |
515 | { | |
516 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
517 | int tps = 0; | |
518 | uint32_t units = nv_rd32(dev, 0x1540); | |
519 | int i, r; | |
520 | uint32_t ustatus_addr, ustatus; | |
521 | for (i = 0; i < 16; i++) { | |
522 | if (!(units & (1 << i))) | |
523 | continue; | |
524 | if (dev_priv->chipset < 0xa0) | |
525 | ustatus_addr = ustatus_old + (i << 12); | |
526 | else | |
527 | ustatus_addr = ustatus_new + (i << 11); | |
528 | ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff; | |
529 | if (!ustatus) | |
530 | continue; | |
531 | tps++; | |
532 | switch (type) { | |
533 | case 6: /* texture error... unknown for now */ | |
274fec93 BS |
534 | if (display) { |
535 | NV_ERROR(dev, "magic set %d:\n", i); | |
536 | for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) | |
537 | NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, | |
538 | nv_rd32(dev, r)); | |
539 | } | |
540 | break; | |
541 | case 7: /* MP error */ | |
c983e6f6 | 542 | if (ustatus & 0x04030000) { |
274fec93 | 543 | nv50_pgraph_mp_trap(dev, i, display); |
c983e6f6 | 544 | ustatus &= ~0x04030000; |
274fec93 BS |
545 | } |
546 | break; | |
547 | case 8: /* TPDMA error */ | |
548 | { | |
549 | uint32_t e0c = nv_rd32(dev, ustatus_addr + 4); | |
550 | uint32_t e10 = nv_rd32(dev, ustatus_addr + 8); | |
551 | uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc); | |
552 | uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10); | |
553 | uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14); | |
554 | uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18); | |
555 | uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c); | |
274fec93 BS |
556 | /* 2d engine destination */ |
557 | if (ustatus & 0x00000010) { | |
558 | if (display) { | |
559 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n", | |
560 | i, e14, e10); | |
561 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
562 | i, e0c, e18, e1c, e20, e24); | |
563 | } | |
564 | ustatus &= ~0x00000010; | |
565 | } | |
566 | /* Render target */ | |
567 | if (ustatus & 0x00000040) { | |
568 | if (display) { | |
569 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n", | |
570 | i, e14, e10); | |
571 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
572 | i, e0c, e18, e1c, e20, e24); | |
573 | } | |
574 | ustatus &= ~0x00000040; | |
575 | } | |
576 | /* CUDA memory: l[], g[] or stack. */ | |
577 | if (ustatus & 0x00000080) { | |
578 | if (display) { | |
579 | if (e18 & 0x80000000) { | |
580 | /* g[] read fault? */ | |
581 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n", | |
582 | i, e14, e10 | ((e18 >> 24) & 0x1f)); | |
583 | e18 &= ~0x1f000000; | |
584 | } else if (e18 & 0xc) { | |
585 | /* g[] write fault? */ | |
586 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n", | |
587 | i, e14, e10 | ((e18 >> 7) & 0x1f)); | |
588 | e18 &= ~0x00000f80; | |
589 | } else { | |
590 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n", | |
591 | i, e14, e10); | |
592 | } | |
593 | NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | |
594 | i, e0c, e18, e1c, e20, e24); | |
595 | } | |
596 | ustatus &= ~0x00000080; | |
597 | } | |
598 | } | |
599 | break; | |
600 | } | |
601 | if (ustatus) { | |
602 | if (display) | |
603 | NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); | |
604 | } | |
605 | nv_wr32(dev, ustatus_addr, 0xc0000000); | |
606 | } | |
607 | ||
608 | if (!tps && display) | |
609 | NV_INFO(dev, "%s - No TPs claiming errors?\n", name); | |
610 | } | |
611 | ||
612 | static int | |
613 | nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid) | |
614 | { | |
615 | u32 status = nv_rd32(dev, 0x400108); | |
616 | u32 ustatus; | |
617 | ||
618 | if (!status && display) { | |
619 | NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n"); | |
620 | return 1; | |
621 | } | |
622 | ||
623 | /* DISPATCH: Relays commands to other units and handles NOTIFY, | |
624 | * COND, QUERY. If you get a trap from it, the command is still stuck | |
625 | * in DISPATCH and you need to do something about it. */ | |
626 | if (status & 0x001) { | |
627 | ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff; | |
628 | if (!ustatus && display) { | |
629 | NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n"); | |
630 | } | |
631 | ||
632 | nv_wr32(dev, 0x400500, 0x00000000); | |
633 | ||
634 | /* Known to be triggered by screwed up NOTIFY and COND... */ | |
635 | if (ustatus & 0x00000001) { | |
636 | u32 addr = nv_rd32(dev, 0x400808); | |
637 | u32 subc = (addr & 0x00070000) >> 16; | |
638 | u32 mthd = (addr & 0x00001ffc); | |
639 | u32 datal = nv_rd32(dev, 0x40080c); | |
640 | u32 datah = nv_rd32(dev, 0x400810); | |
641 | u32 class = nv_rd32(dev, 0x400814); | |
642 | u32 r848 = nv_rd32(dev, 0x400848); | |
643 | ||
644 | NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n"); | |
645 | if (display && (addr & 0x80000000)) { | |
646 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) " | |
647 | "subc %d class 0x%04x mthd 0x%04x " | |
648 | "data 0x%08x%08x " | |
649 | "400808 0x%08x 400848 0x%08x\n", | |
650 | chid, inst, subc, class, mthd, datah, | |
651 | datal, addr, r848); | |
652 | } else | |
653 | if (display) { | |
654 | NV_INFO(dev, "PGRAPH - no stuck command?\n"); | |
655 | } | |
656 | ||
657 | nv_wr32(dev, 0x400808, 0); | |
658 | nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3); | |
659 | nv_wr32(dev, 0x400848, 0); | |
660 | ustatus &= ~0x00000001; | |
661 | } | |
662 | ||
663 | if (ustatus & 0x00000002) { | |
664 | u32 addr = nv_rd32(dev, 0x40084c); | |
665 | u32 subc = (addr & 0x00070000) >> 16; | |
666 | u32 mthd = (addr & 0x00001ffc); | |
667 | u32 data = nv_rd32(dev, 0x40085c); | |
668 | u32 class = nv_rd32(dev, 0x400814); | |
669 | ||
670 | NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n"); | |
671 | if (display && (addr & 0x80000000)) { | |
672 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) " | |
673 | "subc %d class 0x%04x mthd 0x%04x " | |
674 | "data 0x%08x 40084c 0x%08x\n", | |
675 | chid, inst, subc, class, mthd, | |
676 | data, addr); | |
677 | } else | |
678 | if (display) { | |
679 | NV_INFO(dev, "PGRAPH - no stuck command?\n"); | |
680 | } | |
681 | ||
682 | nv_wr32(dev, 0x40084c, 0); | |
683 | ustatus &= ~0x00000002; | |
684 | } | |
685 | ||
686 | if (ustatus && display) { | |
687 | NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown " | |
688 | "0x%08x)\n", ustatus); | |
689 | } | |
690 | ||
691 | nv_wr32(dev, 0x400804, 0xc0000000); | |
692 | nv_wr32(dev, 0x400108, 0x001); | |
693 | status &= ~0x001; | |
694 | if (!status) | |
695 | return 0; | |
696 | } | |
697 | ||
698 | /* M2MF: Memory to memory copy engine. */ | |
699 | if (status & 0x002) { | |
700 | u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff; | |
701 | if (display) { | |
702 | NV_INFO(dev, "PGRAPH - TRAP_M2MF"); | |
703 | nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); | |
704 | printk("\n"); | |
705 | NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n", | |
706 | nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808), | |
707 | nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810)); | |
708 | ||
709 | } | |
710 | ||
711 | /* No sane way found yet -- just reset the bugger. */ | |
712 | nv_wr32(dev, 0x400040, 2); | |
713 | nv_wr32(dev, 0x400040, 0); | |
714 | nv_wr32(dev, 0x406800, 0xc0000000); | |
715 | nv_wr32(dev, 0x400108, 0x002); | |
716 | status &= ~0x002; | |
717 | } | |
718 | ||
719 | /* VFETCH: Fetches data from vertex buffers. */ | |
720 | if (status & 0x004) { | |
721 | u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff; | |
722 | if (display) { | |
723 | NV_INFO(dev, "PGRAPH - TRAP_VFETCH"); | |
724 | nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); | |
725 | printk("\n"); | |
726 | NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n", | |
727 | nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08), | |
728 | nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10)); | |
729 | } | |
730 | ||
731 | nv_wr32(dev, 0x400c04, 0xc0000000); | |
732 | nv_wr32(dev, 0x400108, 0x004); | |
733 | status &= ~0x004; | |
734 | } | |
735 | ||
736 | /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ | |
737 | if (status & 0x008) { | |
738 | ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff; | |
739 | if (display) { | |
740 | NV_INFO(dev, "PGRAPH - TRAP_STRMOUT"); | |
741 | nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); | |
742 | printk("\n"); | |
743 | NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n", | |
744 | nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808), | |
745 | nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810)); | |
746 | ||
747 | } | |
748 | ||
749 | /* No sane way found yet -- just reset the bugger. */ | |
750 | nv_wr32(dev, 0x400040, 0x80); | |
751 | nv_wr32(dev, 0x400040, 0); | |
752 | nv_wr32(dev, 0x401800, 0xc0000000); | |
753 | nv_wr32(dev, 0x400108, 0x008); | |
754 | status &= ~0x008; | |
755 | } | |
756 | ||
757 | /* CCACHE: Handles code and c[] caches and fills them. */ | |
758 | if (status & 0x010) { | |
759 | ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff; | |
760 | if (display) { | |
761 | NV_INFO(dev, "PGRAPH - TRAP_CCACHE"); | |
762 | nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); | |
763 | printk("\n"); | |
764 | NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x" | |
765 | " %08x %08x %08x\n", | |
4dcf905c MS |
766 | nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004), |
767 | nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c), | |
768 | nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014), | |
769 | nv_rd32(dev, 0x40501c)); | |
274fec93 BS |
770 | |
771 | } | |
772 | ||
773 | nv_wr32(dev, 0x405018, 0xc0000000); | |
774 | nv_wr32(dev, 0x400108, 0x010); | |
775 | status &= ~0x010; | |
776 | } | |
777 | ||
778 | /* Unknown, not seen yet... 0x402000 is the only trap status reg | |
779 | * remaining, so try to handle it anyway. Perhaps related to that | |
780 | * unknown DMA slot on tesla? */ | |
781 | if (status & 0x20) { | |
782 | ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff; | |
783 | if (display) | |
784 | NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus); | |
785 | nv_wr32(dev, 0x402000, 0xc0000000); | |
786 | /* no status modifiction on purpose */ | |
787 | } | |
788 | ||
789 | /* TEXTURE: CUDA texturing units */ | |
790 | if (status & 0x040) { | |
791 | nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display, | |
792 | "PGRAPH - TRAP_TEXTURE"); | |
793 | nv_wr32(dev, 0x400108, 0x040); | |
794 | status &= ~0x040; | |
795 | } | |
796 | ||
797 | /* MP: CUDA execution engines. */ | |
798 | if (status & 0x080) { | |
799 | nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display, | |
800 | "PGRAPH - TRAP_MP"); | |
801 | nv_wr32(dev, 0x400108, 0x080); | |
802 | status &= ~0x080; | |
803 | } | |
804 | ||
805 | /* TPDMA: Handles TP-initiated uncached memory accesses: | |
806 | * l[], g[], stack, 2d surfaces, render targets. */ | |
807 | if (status & 0x100) { | |
808 | nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display, | |
809 | "PGRAPH - TRAP_TPDMA"); | |
810 | nv_wr32(dev, 0x400108, 0x100); | |
811 | status &= ~0x100; | |
812 | } | |
813 | ||
814 | if (status) { | |
815 | if (display) | |
816 | NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status); | |
817 | nv_wr32(dev, 0x400108, status); | |
818 | } | |
819 | ||
820 | return 1; | |
821 | } | |
822 | ||
7ff5441e | 823 | int |
274fec93 BS |
824 | nv50_graph_isr_chid(struct drm_device *dev, u64 inst) |
825 | { | |
826 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
827 | struct nouveau_channel *chan; | |
828 | unsigned long flags; | |
829 | int i; | |
830 | ||
831 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
832 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
833 | chan = dev_priv->channels.ptr[i]; | |
834 | if (!chan || !chan->ramin) | |
835 | continue; | |
836 | ||
837 | if (inst == chan->ramin->vinst) | |
838 | break; | |
839 | } | |
840 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
841 | return i; | |
842 | } | |
843 | ||
844 | static void | |
845 | nv50_graph_isr(struct drm_device *dev) | |
846 | { | |
847 | u32 stat; | |
848 | ||
849 | while ((stat = nv_rd32(dev, 0x400100))) { | |
850 | u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12; | |
851 | u32 chid = nv50_graph_isr_chid(dev, inst); | |
852 | u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR); | |
853 | u32 subc = (addr & 0x00070000) >> 16; | |
854 | u32 mthd = (addr & 0x00001ffc); | |
855 | u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA); | |
856 | u32 class = nv_rd32(dev, 0x400814); | |
857 | u32 show = stat; | |
858 | ||
859 | if (stat & 0x00000010) { | |
860 | if (!nouveau_gpuobj_mthd_call2(dev, chid, class, | |
861 | mthd, data)) | |
862 | show &= ~0x00000010; | |
863 | } | |
864 | ||
865 | if (stat & 0x00001000) { | |
866 | nv_wr32(dev, 0x400500, 0x00000000); | |
867 | nv_wr32(dev, 0x400100, 0x00001000); | |
868 | nv_mask(dev, 0x40013c, 0x00001000, 0x00000000); | |
869 | nv50_graph_context_switch(dev); | |
870 | stat &= ~0x00001000; | |
871 | show &= ~0x00001000; | |
872 | } | |
873 | ||
874 | show = (show && nouveau_ratelimit()) ? show : 0; | |
875 | ||
876 | if (show & 0x00100000) { | |
877 | u32 ecode = nv_rd32(dev, 0x400110); | |
878 | NV_INFO(dev, "PGRAPH - DATA_ERROR "); | |
879 | nouveau_enum_print(nv50_data_error_names, ecode); | |
880 | printk("\n"); | |
881 | } | |
882 | ||
883 | if (stat & 0x00200000) { | |
884 | if (!nv50_pgraph_trap_handler(dev, show, inst, chid)) | |
885 | show &= ~0x00200000; | |
886 | } | |
887 | ||
888 | nv_wr32(dev, 0x400100, stat); | |
889 | nv_wr32(dev, 0x400500, 0x00010001); | |
890 | ||
891 | if (show) { | |
892 | NV_INFO(dev, "PGRAPH -"); | |
893 | nouveau_bitfield_print(nv50_graph_intr, show); | |
894 | printk("\n"); | |
895 | NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d " | |
896 | "class 0x%04x mthd 0x%04x data 0x%08x\n", | |
897 | chid, inst, subc, class, mthd, data); | |
6fdb383e | 898 | nv50_fb_vm_trap(dev, 1); |
274fec93 BS |
899 | } |
900 | } | |
901 | ||
902 | if (nv_rd32(dev, 0x400824) & (1 << 31)) | |
903 | nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); | |
904 | } | |
2703c21a BS |
905 | |
906 | static void | |
907 | nv50_graph_destroy(struct drm_device *dev, int engine) | |
908 | { | |
909 | struct nv50_graph_engine *pgraph = nv_engine(dev, engine); | |
910 | ||
911 | NVOBJ_ENGINE_DEL(dev, GR); | |
912 | ||
913 | nouveau_irq_unregister(dev, 12); | |
914 | kfree(pgraph); | |
915 | } | |
916 | ||
917 | int | |
918 | nv50_graph_create(struct drm_device *dev) | |
919 | { | |
920 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
921 | struct nv50_graph_engine *pgraph; | |
2703c21a BS |
922 | int ret; |
923 | ||
924 | pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL); | |
925 | if (!pgraph) | |
926 | return -ENOMEM; | |
927 | ||
d58086de BS |
928 | ret = nv50_grctx_init(dev, pgraph->ctxprog, ARRAY_SIZE(pgraph->ctxprog), |
929 | &pgraph->ctxprog_size, | |
930 | &pgraph->grctx_size); | |
2703c21a BS |
931 | if (ret) { |
932 | NV_ERROR(dev, "PGRAPH: ctxprog build failed\n"); | |
2703c21a BS |
933 | kfree(pgraph); |
934 | return 0; | |
935 | } | |
936 | ||
2703c21a BS |
937 | pgraph->base.destroy = nv50_graph_destroy; |
938 | pgraph->base.init = nv50_graph_init; | |
939 | pgraph->base.fini = nv50_graph_fini; | |
940 | pgraph->base.context_new = nv50_graph_context_new; | |
941 | pgraph->base.context_del = nv50_graph_context_del; | |
942 | pgraph->base.object_new = nv50_graph_object_new; | |
943 | if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac) | |
944 | pgraph->base.tlb_flush = nv50_graph_tlb_flush; | |
945 | else | |
946 | pgraph->base.tlb_flush = nv84_graph_tlb_flush; | |
947 | ||
948 | nouveau_irq_register(dev, 12, nv50_graph_isr); | |
949 | ||
2703c21a BS |
950 | NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base); |
951 | NVOBJ_CLASS(dev, 0x0030, GR); /* null */ | |
952 | NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */ | |
953 | NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */ | |
954 | ||
955 | /* tesla */ | |
956 | if (dev_priv->chipset == 0x50) | |
957 | NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */ | |
958 | else | |
959 | if (dev_priv->chipset < 0xa0) | |
960 | NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */ | |
961 | else { | |
962 | switch (dev_priv->chipset) { | |
963 | case 0xa0: | |
964 | case 0xaa: | |
965 | case 0xac: | |
966 | NVOBJ_CLASS(dev, 0x8397, GR); | |
967 | break; | |
968 | case 0xa3: | |
969 | case 0xa5: | |
970 | case 0xa8: | |
971 | NVOBJ_CLASS(dev, 0x8597, GR); | |
972 | break; | |
973 | case 0xaf: | |
974 | NVOBJ_CLASS(dev, 0x8697, GR); | |
975 | break; | |
976 | } | |
977 | } | |
978 | ||
979 | /* compute */ | |
980 | NVOBJ_CLASS(dev, 0x50c0, GR); | |
981 | if (dev_priv->chipset > 0xa0 && | |
982 | dev_priv->chipset != 0xaa && | |
983 | dev_priv->chipset != 0xac) | |
984 | NVOBJ_CLASS(dev, 0x85c0, GR); | |
985 | ||
986 | return 0; | |
987 | } |