[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nv84_crypt.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_util.h"
#include "nouveau_vm.h"
#include "nouveau_ramht.h"

static void nv84_crypt_isr(struct drm_device *);

int
nv84_crypt_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *ramin = chan->ramin;
	int ret;

	NV_DEBUG(dev, "ch%d\n", chan->id);

	ret = nouveau_gpuobj_new(dev, chan, 256, 0,
				 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
				 &chan->crypt_ctx);
	if (ret)
		return ret;

	nv_wo32(ramin, 0xa0, 0x00190000);
	nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
	nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
	nv_wo32(ramin, 0xac, 0);
	nv_wo32(ramin, 0xb0, 0);
	nv_wo32(ramin, 0xb4, 0);

	dev_priv->engine.instmem.flush(dev);
	atomic_inc(&chan->vm->pcrypt_refs);
	return 0;
}

void
nv84_crypt_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	u32 inst;

	if (!chan->crypt_ctx)
		return;

	inst  = (chan->ramin->vinst >> 12);
	inst |= 0x80000000;

	/* mark context as invalid if still on the hardware, not
	 * doing this causes issues the next time PCRYPT is used,
	 * unsurprisingly :)
	 */
	nv_wr32(dev, 0x10200c, 0x00000000);
	if (nv_rd32(dev, 0x102188) == inst)
		nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
	if (nv_rd32(dev, 0x10218c) == inst)
		nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
	nv_wr32(dev, 0x10200c, 0x00000010);

	nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
	atomic_dec(&chan->vm->pcrypt_refs);
}

int
nv84_crypt_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	if (ret)
		return ret;
	obj->engine = 5;
	obj->class  = class;

	nv_wo32(obj, 0x00, class);
	dev_priv->engine.instmem.flush(dev);

	ret = nouveau_ramht_insert(chan, handle, obj);
	nouveau_gpuobj_ref(NULL, &obj);
	return ret;
}

void
nv84_crypt_tlb_flush(struct drm_device *dev)
{
	nv50_vm_flush_engine(dev, 0x0a);
}

int
nv84_crypt_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;

	if (!pcrypt->registered) {
		NVOBJ_CLASS(dev, 0x74c1, CRYPT);
		pcrypt->registered = true;
	}

	nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
	nv_mask(dev, 0x000200, 0x00004000, 0x00004000);

	nouveau_irq_register(dev, 14, nv84_crypt_isr);
	nv_wr32(dev, 0x102130, 0xffffffff);
	nv_wr32(dev, 0x102140, 0xffffffbf);

	nv_wr32(dev, 0x10200c, 0x00000010);
	return 0;
}

void
nv84_crypt_fini(struct drm_device *dev)
{
	nv_wr32(dev, 0x102140, 0x00000000);
	nouveau_irq_unregister(dev, 14);
}

static void
nv84_crypt_isr(struct drm_device *dev)
{
	u32 stat = nv_rd32(dev, 0x102130);
	u32 mthd = nv_rd32(dev, 0x102190);
	u32 data = nv_rd32(dev, 0x102194);
	u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
	int show = nouveau_ratelimit();

	if (show) {
		NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			     stat, mthd, data, inst);
	}

	nv_wr32(dev, 0x102130, stat);
	nv_wr32(dev, 0x10200c, 0x10);

	nv50_fb_vm_trap(dev, show);
}
Commit	Line	Data
bd2e597d BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
d7facf9d	27	#include "nouveau_util.h"
a11c3198	28	#include "nouveau_vm.h"
4ea52f89	29	#include "nouveau_ramht.h"
d7facf9d BS	30
d7facf9d BS	31	static void nv84_crypt_isr(struct drm_device *);
bd2e597d BS	32
	33	int
	34	nv84_crypt_create_context(struct nouveau_channel *chan)
	35	{
	36	struct drm_device *dev = chan->dev;
	37	struct drm_nouveau_private *dev_priv = dev->dev_private;
	38	struct nouveau_gpuobj *ramin = chan->ramin;
	39	int ret;
	40
	41	NV_DEBUG(dev, "ch%d\n", chan->id);
	42
3052be2c	43	ret = nouveau_gpuobj_new(dev, chan, 256, 0,
bd2e597d BS	44	NVOBJ_FLAG_ZERO_ALLOC \| NVOBJ_FLAG_ZERO_FREE,
	45	&chan->crypt_ctx);
	46	if (ret)
	47	return ret;
	48
	49	nv_wo32(ramin, 0xa0, 0x00190000);
	50	nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
	51	nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
	52	nv_wo32(ramin, 0xac, 0);
	53	nv_wo32(ramin, 0xb0, 0);
	54	nv_wo32(ramin, 0xb4, 0);
	55
	56	dev_priv->engine.instmem.flush(dev);
4c136142	57	atomic_inc(&chan->vm->pcrypt_refs);
bd2e597d BS	58	return 0;
	59	}
	60
	61	void
	62	nv84_crypt_destroy_context(struct nouveau_channel *chan)
	63	{
	64	struct drm_device *dev = chan->dev;
	65	u32 inst;
	66
2cb3d3b6	67	if (!chan->crypt_ctx)
bd2e597d BS	68	return;
	69
	70	inst = (chan->ramin->vinst >> 12);
	71	inst \|= 0x80000000;
	72
	73	/* mark context as invalid if still on the hardware, not
	74	* doing this causes issues the next time PCRYPT is used,
	75	* unsurprisingly :)
	76	*/
	77	nv_wr32(dev, 0x10200c, 0x00000000);
	78	if (nv_rd32(dev, 0x102188) == inst)
	79	nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
	80	if (nv_rd32(dev, 0x10218c) == inst)
	81	nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
	82	nv_wr32(dev, 0x10200c, 0x00000010);
	83
	84	nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
4c136142	85	atomic_dec(&chan->vm->pcrypt_refs);
bd2e597d BS	86	}
bd2e597d BS	87
4ea52f89 BS	88	int
	89	nv84_crypt_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
	90	{
	91	struct drm_device *dev = chan->dev;
	92	struct drm_nouveau_private *dev_priv = dev->dev_private;
	93	struct nouveau_gpuobj *obj = NULL;
	94	int ret;
	95
	96	ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	97	if (ret)
	98	return ret;
	99	obj->engine = 5;
	100	obj->class = class;
	101
	102	nv_wo32(obj, 0x00, class);
	103	dev_priv->engine.instmem.flush(dev);
	104
	105	ret = nouveau_ramht_insert(chan, handle, obj);
	106	nouveau_gpuobj_ref(NULL, &obj);
	107	return ret;
	108	}
	109
bd2e597d BS	110	void
	111	nv84_crypt_tlb_flush(struct drm_device *dev)
	112	{
a11c3198	113	nv50_vm_flush_engine(dev, 0x0a);
bd2e597d BS	114	}
	115
	116	int
	117	nv84_crypt_init(struct drm_device *dev)
	118	{
	119	struct drm_nouveau_private *dev_priv = dev->dev_private;
	120	struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
	121
	122	if (!pcrypt->registered) {
	123	NVOBJ_CLASS(dev, 0x74c1, CRYPT);
	124	pcrypt->registered = true;
	125	}
	126
	127	nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
	128	nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
d7facf9d BS	129
d7facf9d BS	130	nouveau_irq_register(dev, 14, nv84_crypt_isr);
bd2e597d BS	131	nv_wr32(dev, 0x102130, 0xffffffff);
bd2e597d BS	132	nv_wr32(dev, 0x102140, 0xffffffbf);
d7facf9d	133
bd2e597d BS	134	nv_wr32(dev, 0x10200c, 0x00000010);
	135	return 0;
	136	}
	137
	138	void
	139	nv84_crypt_fini(struct drm_device *dev)
	140	{
	141	nv_wr32(dev, 0x102140, 0x00000000);
d7facf9d BS	142	nouveau_irq_unregister(dev, 14);
	143	}
	144
	145	static void
	146	nv84_crypt_isr(struct drm_device *dev)
	147	{
	148	u32 stat = nv_rd32(dev, 0x102130);
	149	u32 mthd = nv_rd32(dev, 0x102190);
	150	u32 data = nv_rd32(dev, 0x102194);
	151	u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
	152	int show = nouveau_ratelimit();
	153
	154	if (show) {
	155	NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
	156	stat, mthd, data, inst);
	157	}
	158
	159	nv_wr32(dev, 0x102130, stat);
	160	nv_wr32(dev, 0x10200c, 0x10);
	161
6fdb383e	162	nv50_fb_vm_trap(dev, show);
bd2e597d	163	}