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1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #include "nouveau_drv.h" | |
d7facf9d | 27 | #include "nouveau_util.h" |
a11c3198 | 28 | #include "nouveau_vm.h" |
4ea52f89 | 29 | #include "nouveau_ramht.h" |
d7facf9d | 30 | |
6dfdd7a6 BS |
31 | struct nv84_crypt_engine { |
32 | struct nouveau_exec_engine base; | |
33 | }; | |
bd2e597d | 34 | |
6dfdd7a6 BS |
35 | static int |
36 | nv84_crypt_context_new(struct nouveau_channel *chan, int engine) | |
bd2e597d BS |
37 | { |
38 | struct drm_device *dev = chan->dev; | |
39 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
40 | struct nouveau_gpuobj *ramin = chan->ramin; | |
6dfdd7a6 | 41 | struct nouveau_gpuobj *ctx; |
bd2e597d BS |
42 | int ret; |
43 | ||
44 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
45 | ||
6dfdd7a6 BS |
46 | ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC | |
47 | NVOBJ_FLAG_ZERO_FREE, &ctx); | |
bd2e597d BS |
48 | if (ret) |
49 | return ret; | |
50 | ||
51 | nv_wo32(ramin, 0xa0, 0x00190000); | |
6dfdd7a6 BS |
52 | nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1); |
53 | nv_wo32(ramin, 0xa8, ctx->vinst); | |
bd2e597d BS |
54 | nv_wo32(ramin, 0xac, 0); |
55 | nv_wo32(ramin, 0xb0, 0); | |
56 | nv_wo32(ramin, 0xb4, 0); | |
bd2e597d | 57 | dev_priv->engine.instmem.flush(dev); |
6dfdd7a6 BS |
58 | |
59 | atomic_inc(&chan->vm->engref[engine]); | |
60 | chan->engctx[engine] = ctx; | |
bd2e597d BS |
61 | return 0; |
62 | } | |
63 | ||
6dfdd7a6 BS |
64 | static void |
65 | nv84_crypt_context_del(struct nouveau_channel *chan, int engine) | |
bd2e597d | 66 | { |
6dfdd7a6 | 67 | struct nouveau_gpuobj *ctx = chan->engctx[engine]; |
bd2e597d BS |
68 | struct drm_device *dev = chan->dev; |
69 | u32 inst; | |
70 | ||
bd2e597d BS |
71 | inst = (chan->ramin->vinst >> 12); |
72 | inst |= 0x80000000; | |
73 | ||
74 | /* mark context as invalid if still on the hardware, not | |
75 | * doing this causes issues the next time PCRYPT is used, | |
76 | * unsurprisingly :) | |
77 | */ | |
78 | nv_wr32(dev, 0x10200c, 0x00000000); | |
79 | if (nv_rd32(dev, 0x102188) == inst) | |
80 | nv_mask(dev, 0x102188, 0x80000000, 0x00000000); | |
81 | if (nv_rd32(dev, 0x10218c) == inst) | |
82 | nv_mask(dev, 0x10218c, 0x80000000, 0x00000000); | |
83 | nv_wr32(dev, 0x10200c, 0x00000010); | |
84 | ||
6dfdd7a6 BS |
85 | nouveau_gpuobj_ref(NULL, &ctx); |
86 | ||
87 | atomic_dec(&chan->vm->engref[engine]); | |
88 | chan->engctx[engine] = NULL; | |
bd2e597d BS |
89 | } |
90 | ||
6dfdd7a6 BS |
91 | static int |
92 | nv84_crypt_object_new(struct nouveau_channel *chan, int engine, | |
93 | u32 handle, u16 class) | |
4ea52f89 BS |
94 | { |
95 | struct drm_device *dev = chan->dev; | |
96 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
97 | struct nouveau_gpuobj *obj = NULL; | |
98 | int ret; | |
99 | ||
100 | ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj); | |
101 | if (ret) | |
102 | return ret; | |
103 | obj->engine = 5; | |
104 | obj->class = class; | |
105 | ||
106 | nv_wo32(obj, 0x00, class); | |
107 | dev_priv->engine.instmem.flush(dev); | |
108 | ||
109 | ret = nouveau_ramht_insert(chan, handle, obj); | |
110 | nouveau_gpuobj_ref(NULL, &obj); | |
111 | return ret; | |
112 | } | |
113 | ||
6dfdd7a6 BS |
114 | static void |
115 | nv84_crypt_tlb_flush(struct drm_device *dev, int engine) | |
bd2e597d | 116 | { |
a11c3198 | 117 | nv50_vm_flush_engine(dev, 0x0a); |
bd2e597d BS |
118 | } |
119 | ||
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120 | static void |
121 | nv84_crypt_isr(struct drm_device *dev) | |
bd2e597d | 122 | { |
6dfdd7a6 BS |
123 | u32 stat = nv_rd32(dev, 0x102130); |
124 | u32 mthd = nv_rd32(dev, 0x102190); | |
125 | u32 data = nv_rd32(dev, 0x102194); | |
126 | u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff; | |
127 | int show = nouveau_ratelimit(); | |
bd2e597d | 128 | |
6dfdd7a6 BS |
129 | if (show) { |
130 | NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
131 | stat, mthd, data, inst); | |
bd2e597d BS |
132 | } |
133 | ||
6dfdd7a6 BS |
134 | nv_wr32(dev, 0x102130, stat); |
135 | nv_wr32(dev, 0x10200c, 0x10); | |
136 | ||
137 | nv50_fb_vm_trap(dev, show); | |
138 | } | |
139 | ||
140 | static int | |
141 | nv84_crypt_fini(struct drm_device *dev, int engine) | |
142 | { | |
143 | nv_wr32(dev, 0x102140, 0x00000000); | |
144 | return 0; | |
145 | } | |
146 | ||
147 | static int | |
148 | nv84_crypt_init(struct drm_device *dev, int engine) | |
149 | { | |
bd2e597d BS |
150 | nv_mask(dev, 0x000200, 0x00004000, 0x00000000); |
151 | nv_mask(dev, 0x000200, 0x00004000, 0x00004000); | |
d7facf9d | 152 | |
bd2e597d BS |
153 | nv_wr32(dev, 0x102130, 0xffffffff); |
154 | nv_wr32(dev, 0x102140, 0xffffffbf); | |
d7facf9d | 155 | |
bd2e597d BS |
156 | nv_wr32(dev, 0x10200c, 0x00000010); |
157 | return 0; | |
158 | } | |
159 | ||
6dfdd7a6 BS |
160 | static void |
161 | nv84_crypt_destroy(struct drm_device *dev, int engine) | |
bd2e597d | 162 | { |
6dfdd7a6 BS |
163 | struct nv84_crypt_engine *pcrypt = nv_engine(dev, engine); |
164 | ||
165 | NVOBJ_ENGINE_DEL(dev, CRYPT); | |
166 | ||
d7facf9d | 167 | nouveau_irq_unregister(dev, 14); |
6dfdd7a6 | 168 | kfree(pcrypt); |
d7facf9d BS |
169 | } |
170 | ||
6dfdd7a6 BS |
171 | int |
172 | nv84_crypt_create(struct drm_device *dev) | |
d7facf9d | 173 | { |
6dfdd7a6 | 174 | struct nv84_crypt_engine *pcrypt; |
d7facf9d | 175 | |
6dfdd7a6 BS |
176 | pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL); |
177 | if (!pcrypt) | |
178 | return -ENOMEM; | |
d7facf9d | 179 | |
6dfdd7a6 BS |
180 | pcrypt->base.destroy = nv84_crypt_destroy; |
181 | pcrypt->base.init = nv84_crypt_init; | |
182 | pcrypt->base.fini = nv84_crypt_fini; | |
183 | pcrypt->base.context_new = nv84_crypt_context_new; | |
184 | pcrypt->base.context_del = nv84_crypt_context_del; | |
185 | pcrypt->base.object_new = nv84_crypt_object_new; | |
186 | pcrypt->base.tlb_flush = nv84_crypt_tlb_flush; | |
d7facf9d | 187 | |
6dfdd7a6 BS |
188 | nouveau_irq_register(dev, 14, nv84_crypt_isr); |
189 | ||
190 | NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base); | |
191 | NVOBJ_CLASS (dev, 0x74c1, CRYPT); | |
192 | return 0; | |
bd2e597d | 193 | } |