[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nv84_fence.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/object.h>
#include <core/client.h>
#include <core/class.h>

#include <engine/fifo.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fence.h"

#include "nv50_display.h"

u64
nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
{
	struct nv84_fence_chan *fctx = chan->fence;
	return fctx->dispc_vma[crtc].offset;
}

static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	int ret = RING_SPACE(chan, 8);
	if (ret == 0) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
		OUT_RING  (chan, chan->vram);
		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
		OUT_RING  (chan, upper_32_bits(virtual));
		OUT_RING  (chan, lower_32_bits(virtual));
		OUT_RING  (chan, sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
		OUT_RING  (chan, 0x00000000);
		FIRE_RING (chan);
	}
	return ret;
}

static int
nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
	int ret = RING_SPACE(chan, 7);
	if (ret == 0) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
		OUT_RING  (chan, chan->vram);
		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(virtual));
		OUT_RING  (chan, lower_32_bits(virtual));
		OUT_RING  (chan, sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
		FIRE_RING (chan);
	}
	return ret;
}

static int
nv84_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
	struct nv84_fence_chan *fctx = chan->fence;
	struct nouveau_fifo_chan *fifo = (void *)chan->object;
	u64 addr = fifo->chid * 16;

	if (fence->sysmem)
		addr += fctx->vma_gart.offset;
	else
		addr += fctx->vma.offset;

	return fctx->base.emit32(chan, addr, fence->sequence);
}

static int
nv84_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nv84_fence_chan *fctx = chan->fence;
	struct nouveau_fifo_chan *fifo = (void *)prev->object;
	u64 addr = fifo->chid * 16;

	if (fence->sysmem)
		addr += fctx->vma_gart.offset;
	else
		addr += fctx->vma.offset;

	return fctx->base.sync32(chan, addr, fence->sequence);
}

static u32
nv84_fence_read(struct nouveau_channel *chan)
{
	struct nouveau_fifo_chan *fifo = (void *)chan->object;
	struct nv84_fence_priv *priv = chan->drm->fence;
	return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
}

static void
nv84_fence_context_del(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->drm->dev;
	struct nv84_fence_priv *priv = chan->drm->fence;
	struct nv84_fence_chan *fctx = chan->fence;
	int i;

	for (i = 0; i < dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
		nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
	}

	nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
	nouveau_bo_vma_del(priv->bo, &fctx->vma);
	nouveau_fence_context_del(&fctx->base);
	chan->fence = NULL;
	kfree(fctx);
}

int
nv84_fence_context_new(struct nouveau_channel *chan)
{
	struct nouveau_fifo_chan *fifo = (void *)chan->object;
	struct nouveau_client *client = nouveau_client(fifo);
	struct nv84_fence_priv *priv = chan->drm->fence;
	struct nv84_fence_chan *fctx;
	int ret, i;

	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);
	fctx->base.emit = nv84_fence_emit;
	fctx->base.sync = nv84_fence_sync;
	fctx->base.read = nv84_fence_read;
	fctx->base.emit32 = nv84_fence_emit32;
	fctx->base.sync32 = nv84_fence_sync32;

	ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
	if (ret == 0) {
		ret = nouveau_bo_vma_add(priv->bo_gart, client->vm,
					&fctx->vma_gart);
	}

	/* map display semaphore buffers into channel's vm */
	for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
		ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
	}

	nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);

	if (ret)
		nv84_fence_context_del(chan);
	return ret;
}

static bool
nv84_fence_suspend(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
	struct nv84_fence_priv *priv = drm->fence;
	int i;

	priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
	if (priv->suspend) {
		for (i = 0; i <= pfifo->max; i++)
			priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
	}

	return priv->suspend != NULL;
}

static void
nv84_fence_resume(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
	struct nv84_fence_priv *priv = drm->fence;
	int i;

	if (priv->suspend) {
		for (i = 0; i <= pfifo->max; i++)
			nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
		vfree(priv->suspend);
		priv->suspend = NULL;
	}
}

static void
nv84_fence_destroy(struct nouveau_drm *drm)
{
	struct nv84_fence_priv *priv = drm->fence;
	nouveau_bo_unmap(priv->bo_gart);
	if (priv->bo_gart)
		nouveau_bo_unpin(priv->bo_gart);
	nouveau_bo_ref(NULL, &priv->bo_gart);
	nouveau_bo_unmap(priv->bo);
	if (priv->bo)
		nouveau_bo_unpin(priv->bo);
	nouveau_bo_ref(NULL, &priv->bo);
	drm->fence = NULL;
	kfree(priv);
}

int
nv84_fence_create(struct nouveau_drm *drm)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
	struct nv84_fence_priv *priv;
	int ret;

	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.dtor = nv84_fence_destroy;
	priv->base.suspend = nv84_fence_suspend;
	priv->base.resume = nv84_fence_resume;
	priv->base.context_new = nv84_fence_context_new;
	priv->base.context_del = nv84_fence_context_del;

	init_waitqueue_head(&priv->base.waiting);
	priv->base.uevent = true;

	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
			     TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
		if (ret == 0) {
			ret = nouveau_bo_map(priv->bo);
			if (ret)
				nouveau_bo_unpin(priv->bo);
		}
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo);
	}

	if (ret == 0)
		ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
				     TTM_PL_FLAG_TT, 0, 0, NULL,
				     &priv->bo_gart);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
		if (ret == 0) {
			ret = nouveau_bo_map(priv->bo_gart);
			if (ret)
				nouveau_bo_unpin(priv->bo_gart);
		}
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo_gart);
	}

	if (ret)
		nv84_fence_destroy(drm);
	return ret;
}
Commit	Line	Data
5e120f6e BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
ebb945a9	25	#include <core/object.h>
a34caf78	26	#include <core/client.h>
ebb945a9 BS	27	#include <core/class.h>
ebb945a9 BS	28
02a841d4	29	#include <engine/fifo.h>
ebb945a9 BS	30
	31	#include "nouveau_drm.h"
	32	#include "nouveau_dma.h"
5e120f6e BS	33	#include "nouveau_fence.h"
5e120f6e BS	34
77145f1c BS	35	#include "nv50_display.h"
77145f1c BS	36
a34caf78 BS	37	u64
	38	nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
	39	{
	40	struct nv84_fence_chan *fctx = chan->fence;
	41	return fctx->dispc_vma[crtc].offset;
	42	}
5e120f6e BS	43
5e120f6e BS	44	static int
bba9852f	45	nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e	46	{
bba9852f	47	int ret = RING_SPACE(chan, 8);
5e120f6e BS	48	if (ret == 0) {
5e120f6e BS	49	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
a34caf78	50	OUT_RING (chan, chan->vram);
e18c080f	51	BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
bba9852f BS	52	OUT_RING (chan, upper_32_bits(virtual));
	53	OUT_RING (chan, lower_32_bits(virtual));
	54	OUT_RING (chan, sequence);
5e120f6e	55	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
e18c080f	56	OUT_RING (chan, 0x00000000);
5e120f6e BS	57	FIRE_RING (chan);
	58	}
	59	return ret;
	60	}
	61
	62	static int
bba9852f	63	nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
5e120f6e	64	{
bba9852f	65	int ret = RING_SPACE(chan, 7);
5e120f6e BS	66	if (ret == 0) {
5e120f6e BS	67	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
a34caf78	68	OUT_RING (chan, chan->vram);
5e120f6e	69	BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
bba9852f BS	70	OUT_RING (chan, upper_32_bits(virtual));
	71	OUT_RING (chan, lower_32_bits(virtual));
	72	OUT_RING (chan, sequence);
5e120f6e BS	73	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
	74	FIRE_RING (chan);
	75	}
	76	return ret;
	77	}
	78
264ce192	79	static int
bba9852f BS	80	nv84_fence_emit(struct nouveau_fence *fence)
	81	{
	82	struct nouveau_channel *chan = fence->channel;
bba9852f BS	83	struct nv84_fence_chan *fctx = chan->fence;
bba9852f BS	84	struct nouveau_fifo_chan fifo = (void )chan->object;
264ce192 BS	85	u64 addr = fifo->chid * 16;
	86
	87	if (fence->sysmem)
	88	addr += fctx->vma_gart.offset;
	89	else
	90	addr += fctx->vma.offset;
	91
827520ce	92	return fctx->base.emit32(chan, addr, fence->sequence);
bba9852f BS	93	}
bba9852f BS	94
264ce192	95	static int
bba9852f BS	96	nv84_fence_sync(struct nouveau_fence *fence,
	97	struct nouveau_channel prev, struct nouveau_channel chan)
	98	{
bba9852f BS	99	struct nv84_fence_chan *fctx = chan->fence;
bba9852f BS	100	struct nouveau_fifo_chan fifo = (void )prev->object;
264ce192 BS	101	u64 addr = fifo->chid * 16;
	102
	103	if (fence->sysmem)
	104	addr += fctx->vma_gart.offset;
	105	else
	106	addr += fctx->vma.offset;
	107
827520ce	108	return fctx->base.sync32(chan, addr, fence->sequence);
bba9852f BS	109	}
bba9852f BS	110
264ce192	111	static u32
5e120f6e BS	112	nv84_fence_read(struct nouveau_channel *chan)
5e120f6e BS	113	{
ebb945a9 BS	114	struct nouveau_fifo_chan fifo = (void )chan->object;
ebb945a9 BS	115	struct nv84_fence_priv *priv = chan->drm->fence;
a34caf78	116	return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
5e120f6e BS	117	}
5e120f6e BS	118
264ce192	119	static void
e193b1d4	120	nv84_fence_context_del(struct nouveau_channel *chan)
5e120f6e	121	{
a34caf78 BS	122	struct drm_device *dev = chan->drm->dev;
a34caf78 BS	123	struct nv84_fence_priv *priv = chan->drm->fence;
e193b1d4	124	struct nv84_fence_chan *fctx = chan->fence;
a34caf78 BS	125	int i;
	126
	127	for (i = 0; i < dev->mode_config.num_crtc; i++) {
	128	struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
	129	nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
	130	}
	131
264ce192	132	nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
a34caf78	133	nouveau_bo_vma_del(priv->bo, &fctx->vma);
5e120f6e	134	nouveau_fence_context_del(&fctx->base);
e193b1d4	135	chan->fence = NULL;
5e120f6e BS	136	kfree(fctx);
	137	}
	138
a34caf78	139	int
e193b1d4	140	nv84_fence_context_new(struct nouveau_channel *chan)
5e120f6e	141	{
ebb945a9	142	struct nouveau_fifo_chan fifo = (void )chan->object;
a34caf78	143	struct nouveau_client *client = nouveau_client(fifo);
ebb945a9	144	struct nv84_fence_priv *priv = chan->drm->fence;
5e120f6e	145	struct nv84_fence_chan *fctx;
f589be88	146	int ret, i;
5e120f6e	147
e193b1d4	148	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
5e120f6e BS	149	if (!fctx)
	150	return -ENOMEM;
	151
	152	nouveau_fence_context_new(&fctx->base);
827520ce BS	153	fctx->base.emit = nv84_fence_emit;
	154	fctx->base.sync = nv84_fence_sync;
	155	fctx->base.read = nv84_fence_read;
	156	fctx->base.emit32 = nv84_fence_emit32;
	157	fctx->base.sync32 = nv84_fence_sync32;
5e120f6e	158
a34caf78	159	ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
264ce192 BS	160	if (ret == 0) {
	161	ret = nouveau_bo_vma_add(priv->bo_gart, client->vm,
	162	&fctx->vma_gart);
	163	}
ebb945a9	164
a34caf78 BS	165	/* map display semaphore buffers into channel's vm */
	166	for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
	167	struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
	168	ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
f589be88 BS	169	}
f589be88 BS	170
a34caf78	171	nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);
264ce192 BS	172
	173	if (ret)
	174	nv84_fence_context_del(chan);
5e120f6e BS	175	return ret;
	176	}
	177
264ce192	178	static bool
a34caf78 BS	179	nv84_fence_suspend(struct nouveau_drm *drm)
	180	{
	181	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
	182	struct nv84_fence_priv *priv = drm->fence;
	183	int i;
	184
	185	priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
	186	if (priv->suspend) {
	187	for (i = 0; i <= pfifo->max; i++)
	188	priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
	189	}
	190
	191	return priv->suspend != NULL;
	192	}
	193
264ce192	194	static void
a34caf78 BS	195	nv84_fence_resume(struct nouveau_drm *drm)
	196	{
	197	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
	198	struct nv84_fence_priv *priv = drm->fence;
	199	int i;
	200
	201	if (priv->suspend) {
	202	for (i = 0; i <= pfifo->max; i++)
	203	nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
	204	vfree(priv->suspend);
	205	priv->suspend = NULL;
	206	}
	207	}
	208
264ce192	209	static void
ebb945a9	210	nv84_fence_destroy(struct nouveau_drm *drm)
5e120f6e	211	{
ebb945a9	212	struct nv84_fence_priv *priv = drm->fence;
264ce192 BS	213	nouveau_bo_unmap(priv->bo_gart);
	214	if (priv->bo_gart)
	215	nouveau_bo_unpin(priv->bo_gart);
	216	nouveau_bo_ref(NULL, &priv->bo_gart);
a34caf78 BS	217	nouveau_bo_unmap(priv->bo);
	218	if (priv->bo)
	219	nouveau_bo_unpin(priv->bo);
	220	nouveau_bo_ref(NULL, &priv->bo);
ebb945a9	221	drm->fence = NULL;
5e120f6e BS	222	kfree(priv);
	223	}
	224
	225	int
ebb945a9	226	nv84_fence_create(struct nouveau_drm *drm)
5e120f6e	227	{
ebb945a9	228	struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
5e120f6e BS	229	struct nv84_fence_priv *priv;
	230	int ret;
	231
ebb945a9	232	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
5e120f6e BS	233	if (!priv)
	234	return -ENOMEM;
	235
e193b1d4	236	priv->base.dtor = nv84_fence_destroy;
a34caf78 BS	237	priv->base.suspend = nv84_fence_suspend;
a34caf78 BS	238	priv->base.resume = nv84_fence_resume;
e193b1d4 BS	239	priv->base.context_new = nv84_fence_context_new;
e193b1d4 BS	240	priv->base.context_del = nv84_fence_context_del;
5e120f6e	241
e18c080f BS	242	init_waitqueue_head(&priv->base.waiting);
	243	priv->base.uevent = true;
	244
a34caf78 BS	245	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
	246	TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
	247	if (ret == 0) {
	248	ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
	249	if (ret == 0) {
	250	ret = nouveau_bo_map(priv->bo);
	251	if (ret)
	252	nouveau_bo_unpin(priv->bo);
	253	}
	254	if (ret)
	255	nouveau_bo_ref(NULL, &priv->bo);
	256	}
	257
264ce192 BS	258	if (ret == 0)
	259	ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
	260	TTM_PL_FLAG_TT, 0, 0, NULL,
	261	&priv->bo_gart);
	262	if (ret == 0) {
	263	ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
	264	if (ret == 0) {
	265	ret = nouveau_bo_map(priv->bo_gart);
	266	if (ret)
	267	nouveau_bo_unpin(priv->bo_gart);
	268	}
	269	if (ret)
	270	nouveau_bo_ref(NULL, &priv->bo_gart);
	271	}
	272
5e120f6e	273	if (ret)
ebb945a9	274	nv84_fence_destroy(drm);
5e120f6e BS	275	return ret;
5e120f6e BS	276	}