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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
4dc28134 | 25 | #include "nouveau_drv.h" |
ebb945a9 | 26 | #include "nouveau_dma.h" |
5e120f6e BS |
27 | #include "nouveau_fence.h" |
28 | ||
77145f1c BS |
29 | #include "nv50_display.h" |
30 | ||
a34caf78 BS |
31 | u64 |
32 | nv84_fence_crtc(struct nouveau_channel *chan, int crtc) | |
33 | { | |
34 | struct nv84_fence_chan *fctx = chan->fence; | |
35 | return fctx->dispc_vma[crtc].offset; | |
36 | } | |
5e120f6e BS |
37 | |
38 | static int | |
bba9852f | 39 | nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) |
5e120f6e | 40 | { |
bba9852f | 41 | int ret = RING_SPACE(chan, 8); |
5e120f6e BS |
42 | if (ret == 0) { |
43 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
0ad72863 | 44 | OUT_RING (chan, chan->vram.handle); |
e18c080f | 45 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); |
bba9852f BS |
46 | OUT_RING (chan, upper_32_bits(virtual)); |
47 | OUT_RING (chan, lower_32_bits(virtual)); | |
48 | OUT_RING (chan, sequence); | |
5e120f6e | 49 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); |
e18c080f | 50 | OUT_RING (chan, 0x00000000); |
5e120f6e BS |
51 | FIRE_RING (chan); |
52 | } | |
53 | return ret; | |
54 | } | |
55 | ||
56 | static int | |
bba9852f | 57 | nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) |
5e120f6e | 58 | { |
bba9852f | 59 | int ret = RING_SPACE(chan, 7); |
5e120f6e BS |
60 | if (ret == 0) { |
61 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
0ad72863 | 62 | OUT_RING (chan, chan->vram.handle); |
5e120f6e | 63 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
bba9852f BS |
64 | OUT_RING (chan, upper_32_bits(virtual)); |
65 | OUT_RING (chan, lower_32_bits(virtual)); | |
66 | OUT_RING (chan, sequence); | |
5e120f6e BS |
67 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); |
68 | FIRE_RING (chan); | |
69 | } | |
70 | return ret; | |
71 | } | |
72 | ||
264ce192 | 73 | static int |
bba9852f BS |
74 | nv84_fence_emit(struct nouveau_fence *fence) |
75 | { | |
76 | struct nouveau_channel *chan = fence->channel; | |
bba9852f | 77 | struct nv84_fence_chan *fctx = chan->fence; |
bbf8906b | 78 | u64 addr = chan->chid * 16; |
264ce192 BS |
79 | |
80 | if (fence->sysmem) | |
81 | addr += fctx->vma_gart.offset; | |
82 | else | |
83 | addr += fctx->vma.offset; | |
84 | ||
29ba89b2 | 85 | return fctx->base.emit32(chan, addr, fence->base.seqno); |
bba9852f BS |
86 | } |
87 | ||
264ce192 | 88 | static int |
bba9852f BS |
89 | nv84_fence_sync(struct nouveau_fence *fence, |
90 | struct nouveau_channel *prev, struct nouveau_channel *chan) | |
91 | { | |
bba9852f | 92 | struct nv84_fence_chan *fctx = chan->fence; |
bbf8906b | 93 | u64 addr = prev->chid * 16; |
264ce192 BS |
94 | |
95 | if (fence->sysmem) | |
96 | addr += fctx->vma_gart.offset; | |
97 | else | |
98 | addr += fctx->vma.offset; | |
99 | ||
29ba89b2 | 100 | return fctx->base.sync32(chan, addr, fence->base.seqno); |
bba9852f BS |
101 | } |
102 | ||
264ce192 | 103 | static u32 |
5e120f6e BS |
104 | nv84_fence_read(struct nouveau_channel *chan) |
105 | { | |
ebb945a9 | 106 | struct nv84_fence_priv *priv = chan->drm->fence; |
bbf8906b | 107 | return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); |
5e120f6e BS |
108 | } |
109 | ||
264ce192 | 110 | static void |
e193b1d4 | 111 | nv84_fence_context_del(struct nouveau_channel *chan) |
5e120f6e | 112 | { |
a34caf78 BS |
113 | struct drm_device *dev = chan->drm->dev; |
114 | struct nv84_fence_priv *priv = chan->drm->fence; | |
e193b1d4 | 115 | struct nv84_fence_chan *fctx = chan->fence; |
a34caf78 BS |
116 | int i; |
117 | ||
118 | for (i = 0; i < dev->mode_config.num_crtc; i++) { | |
119 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); | |
120 | nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); | |
121 | } | |
122 | ||
1dadba87 | 123 | nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); |
264ce192 | 124 | nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); |
a34caf78 | 125 | nouveau_bo_vma_del(priv->bo, &fctx->vma); |
5e120f6e | 126 | nouveau_fence_context_del(&fctx->base); |
e193b1d4 | 127 | chan->fence = NULL; |
15a996bb | 128 | nouveau_fence_context_free(&fctx->base); |
5e120f6e BS |
129 | } |
130 | ||
a34caf78 | 131 | int |
e193b1d4 | 132 | nv84_fence_context_new(struct nouveau_channel *chan) |
5e120f6e | 133 | { |
a01ca78c | 134 | struct nouveau_cli *cli = (void *)chan->user.client; |
ebb945a9 | 135 | struct nv84_fence_priv *priv = chan->drm->fence; |
5e120f6e | 136 | struct nv84_fence_chan *fctx; |
f589be88 | 137 | int ret, i; |
5e120f6e | 138 | |
e193b1d4 | 139 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); |
5e120f6e BS |
140 | if (!fctx) |
141 | return -ENOMEM; | |
142 | ||
29ba89b2 | 143 | nouveau_fence_context_new(chan, &fctx->base); |
827520ce BS |
144 | fctx->base.emit = nv84_fence_emit; |
145 | fctx->base.sync = nv84_fence_sync; | |
146 | fctx->base.read = nv84_fence_read; | |
147 | fctx->base.emit32 = nv84_fence_emit32; | |
148 | fctx->base.sync32 = nv84_fence_sync32; | |
29ba89b2 | 149 | fctx->base.sequence = nv84_fence_read(chan); |
5e120f6e | 150 | |
3ee6f5b5 | 151 | ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma); |
264ce192 | 152 | if (ret == 0) { |
3ee6f5b5 | 153 | ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm, |
264ce192 BS |
154 | &fctx->vma_gart); |
155 | } | |
ebb945a9 | 156 | |
a34caf78 BS |
157 | /* map display semaphore buffers into channel's vm */ |
158 | for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { | |
159 | struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i); | |
3ee6f5b5 | 160 | ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); |
f589be88 BS |
161 | } |
162 | ||
264ce192 BS |
163 | if (ret) |
164 | nv84_fence_context_del(chan); | |
5e120f6e BS |
165 | return ret; |
166 | } | |
167 | ||
264ce192 | 168 | static bool |
a34caf78 BS |
169 | nv84_fence_suspend(struct nouveau_drm *drm) |
170 | { | |
a34caf78 BS |
171 | struct nv84_fence_priv *priv = drm->fence; |
172 | int i; | |
173 | ||
29ba89b2 | 174 | priv->suspend = vmalloc(priv->base.contexts * sizeof(u32)); |
a34caf78 | 175 | if (priv->suspend) { |
29ba89b2 | 176 | for (i = 0; i < priv->base.contexts; i++) |
a34caf78 BS |
177 | priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4); |
178 | } | |
179 | ||
180 | return priv->suspend != NULL; | |
181 | } | |
182 | ||
264ce192 | 183 | static void |
a34caf78 BS |
184 | nv84_fence_resume(struct nouveau_drm *drm) |
185 | { | |
a34caf78 BS |
186 | struct nv84_fence_priv *priv = drm->fence; |
187 | int i; | |
188 | ||
189 | if (priv->suspend) { | |
29ba89b2 | 190 | for (i = 0; i < priv->base.contexts; i++) |
a34caf78 BS |
191 | nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]); |
192 | vfree(priv->suspend); | |
193 | priv->suspend = NULL; | |
194 | } | |
195 | } | |
196 | ||
264ce192 | 197 | static void |
ebb945a9 | 198 | nv84_fence_destroy(struct nouveau_drm *drm) |
5e120f6e | 199 | { |
ebb945a9 | 200 | struct nv84_fence_priv *priv = drm->fence; |
264ce192 BS |
201 | nouveau_bo_unmap(priv->bo_gart); |
202 | if (priv->bo_gart) | |
203 | nouveau_bo_unpin(priv->bo_gart); | |
204 | nouveau_bo_ref(NULL, &priv->bo_gart); | |
a34caf78 BS |
205 | nouveau_bo_unmap(priv->bo); |
206 | if (priv->bo) | |
207 | nouveau_bo_unpin(priv->bo); | |
208 | nouveau_bo_ref(NULL, &priv->bo); | |
ebb945a9 | 209 | drm->fence = NULL; |
5e120f6e BS |
210 | kfree(priv); |
211 | } | |
212 | ||
213 | int | |
ebb945a9 | 214 | nv84_fence_create(struct nouveau_drm *drm) |
5e120f6e | 215 | { |
6189f1b0 | 216 | struct nvkm_fifo *fifo = nvxx_fifo(&drm->device); |
5e120f6e | 217 | struct nv84_fence_priv *priv; |
eaecf032 | 218 | u32 domain; |
5e120f6e BS |
219 | int ret; |
220 | ||
ebb945a9 | 221 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
5e120f6e BS |
222 | if (!priv) |
223 | return -ENOMEM; | |
224 | ||
e193b1d4 | 225 | priv->base.dtor = nv84_fence_destroy; |
a34caf78 BS |
226 | priv->base.suspend = nv84_fence_suspend; |
227 | priv->base.resume = nv84_fence_resume; | |
e193b1d4 BS |
228 | priv->base.context_new = nv84_fence_context_new; |
229 | priv->base.context_del = nv84_fence_context_del; | |
5e120f6e | 230 | |
8f0649b5 | 231 | priv->base.contexts = fifo->nr; |
f54d1867 | 232 | priv->base.context_base = dma_fence_context_alloc(priv->base.contexts); |
e18c080f BS |
233 | priv->base.uevent = true; |
234 | ||
eaecf032 AC |
235 | /* Use VRAM if there is any ; otherwise fallback to system memory */ |
236 | domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : | |
237 | /* | |
238 | * fences created in sysmem must be non-cached or we | |
239 | * will lose CPU/GPU coherency! | |
240 | */ | |
241 | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; | |
242 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, | |
243 | 0, NULL, NULL, &priv->bo); | |
a34caf78 | 244 | if (ret == 0) { |
eaecf032 | 245 | ret = nouveau_bo_pin(priv->bo, domain, false); |
a34caf78 BS |
246 | if (ret == 0) { |
247 | ret = nouveau_bo_map(priv->bo); | |
248 | if (ret) | |
249 | nouveau_bo_unpin(priv->bo); | |
250 | } | |
251 | if (ret) | |
252 | nouveau_bo_ref(NULL, &priv->bo); | |
253 | } | |
254 | ||
264ce192 | 255 | if (ret == 0) |
29ba89b2 | 256 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, |
a81349a7 AC |
257 | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0, |
258 | 0, NULL, NULL, &priv->bo_gart); | |
264ce192 | 259 | if (ret == 0) { |
ad76b3f7 | 260 | ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false); |
264ce192 BS |
261 | if (ret == 0) { |
262 | ret = nouveau_bo_map(priv->bo_gart); | |
263 | if (ret) | |
264 | nouveau_bo_unpin(priv->bo_gart); | |
265 | } | |
266 | if (ret) | |
267 | nouveau_bo_ref(NULL, &priv->bo_gart); | |
268 | } | |
269 | ||
5e120f6e | 270 | if (ret) |
ebb945a9 | 271 | nv84_fence_destroy(drm); |
5e120f6e BS |
272 | return ret; |
273 | } |