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1 | /* |
2 | * Copyright 2011 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <linux/firmware.h> | |
26 | #include "drmP.h" | |
27 | #include "nouveau_drv.h" | |
28 | #include "nouveau_util.h" | |
29 | #include "nouveau_vm.h" | |
30 | #include "nouveau_ramht.h" | |
31 | #include "nva3_copy.fuc.h" | |
32 | ||
33 | struct nva3_copy_engine { | |
34 | struct nouveau_exec_engine base; | |
35 | }; | |
36 | ||
37 | static int | |
38 | nva3_copy_context_new(struct nouveau_channel *chan, int engine) | |
39 | { | |
40 | struct drm_device *dev = chan->dev; | |
41 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
42 | struct nouveau_gpuobj *ramin = chan->ramin; | |
43 | struct nouveau_gpuobj *ctx = NULL; | |
44 | int ret; | |
45 | ||
46 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
47 | ||
48 | ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC | | |
49 | NVOBJ_FLAG_ZERO_FREE, &ctx); | |
50 | if (ret) | |
51 | return ret; | |
52 | ||
53 | nv_wo32(ramin, 0xc0, 0x00190000); | |
54 | nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1); | |
55 | nv_wo32(ramin, 0xc8, ctx->vinst); | |
56 | nv_wo32(ramin, 0xcc, 0x00000000); | |
57 | nv_wo32(ramin, 0xd0, 0x00000000); | |
58 | nv_wo32(ramin, 0xd4, 0x00000000); | |
59 | dev_priv->engine.instmem.flush(dev); | |
60 | ||
61 | atomic_inc(&chan->vm->engref[engine]); | |
62 | chan->engctx[engine] = ctx; | |
63 | return 0; | |
64 | } | |
65 | ||
66 | static int | |
67 | nva3_copy_object_new(struct nouveau_channel *chan, int engine, | |
68 | u32 handle, u16 class) | |
69 | { | |
70 | struct nouveau_gpuobj *ctx = chan->engctx[engine]; | |
71 | ||
72 | /* fuc engine doesn't need an object, our ramht code does.. */ | |
73 | ctx->engine = 3; | |
74 | ctx->class = class; | |
75 | return nouveau_ramht_insert(chan, handle, ctx); | |
76 | } | |
77 | ||
78 | static void | |
79 | nva3_copy_context_del(struct nouveau_channel *chan, int engine) | |
80 | { | |
81 | struct nouveau_gpuobj *ctx = chan->engctx[engine]; | |
5511d490 | 82 | int i; |
7ff5441e | 83 | |
5511d490 BS |
84 | for (i = 0xc0; i <= 0xd4; i += 4) |
85 | nv_wo32(chan->ramin, i, 0x00000000); | |
7ff5441e BS |
86 | |
87 | atomic_dec(&chan->vm->engref[engine]); | |
5511d490 | 88 | nouveau_gpuobj_ref(NULL, &ctx); |
7ff5441e BS |
89 | chan->engctx[engine] = ctx; |
90 | } | |
91 | ||
92 | static void | |
93 | nva3_copy_tlb_flush(struct drm_device *dev, int engine) | |
94 | { | |
95 | nv50_vm_flush_engine(dev, 0x0d); | |
96 | } | |
97 | ||
98 | static int | |
99 | nva3_copy_init(struct drm_device *dev, int engine) | |
100 | { | |
101 | int i; | |
102 | ||
103 | nv_mask(dev, 0x000200, 0x00002000, 0x00000000); | |
104 | nv_mask(dev, 0x000200, 0x00002000, 0x00002000); | |
105 | nv_wr32(dev, 0x104014, 0xffffffff); /* disable all interrupts */ | |
106 | ||
107 | /* upload ucode */ | |
108 | nv_wr32(dev, 0x1041c0, 0x01000000); | |
109 | for (i = 0; i < sizeof(nva3_pcopy_data) / 4; i++) | |
110 | nv_wr32(dev, 0x1041c4, nva3_pcopy_data[i]); | |
111 | ||
112 | nv_wr32(dev, 0x104180, 0x01000000); | |
113 | for (i = 0; i < sizeof(nva3_pcopy_code) / 4; i++) { | |
114 | if ((i & 0x3f) == 0) | |
115 | nv_wr32(dev, 0x104188, i >> 6); | |
116 | nv_wr32(dev, 0x104184, nva3_pcopy_code[i]); | |
117 | } | |
118 | ||
119 | /* start it running */ | |
120 | nv_wr32(dev, 0x10410c, 0x00000000); | |
121 | nv_wr32(dev, 0x104104, 0x00000000); /* ENTRY */ | |
122 | nv_wr32(dev, 0x104100, 0x00000002); /* TRIGGER */ | |
123 | return 0; | |
124 | } | |
125 | ||
126 | static int | |
6c320fef | 127 | nva3_copy_fini(struct drm_device *dev, int engine, bool suspend) |
7ff5441e BS |
128 | { |
129 | nv_mask(dev, 0x104048, 0x00000003, 0x00000000); | |
7ff5441e BS |
130 | nv_wr32(dev, 0x104014, 0xffffffff); |
131 | return 0; | |
132 | } | |
133 | ||
134 | static struct nouveau_enum nva3_copy_isr_error_name[] = { | |
135 | { 0x0001, "ILLEGAL_MTHD" }, | |
136 | { 0x0002, "INVALID_ENUM" }, | |
137 | { 0x0003, "INVALID_BITFIELD" }, | |
138 | {} | |
139 | }; | |
140 | ||
141 | static void | |
142 | nva3_copy_isr(struct drm_device *dev) | |
143 | { | |
144 | u32 dispatch = nv_rd32(dev, 0x10401c); | |
145 | u32 stat = nv_rd32(dev, 0x104008) & dispatch & ~(dispatch >> 16); | |
146 | u32 inst = nv_rd32(dev, 0x104050) & 0x3fffffff; | |
147 | u32 ssta = nv_rd32(dev, 0x104040) & 0x0000ffff; | |
148 | u32 addr = nv_rd32(dev, 0x104040) >> 16; | |
149 | u32 mthd = (addr & 0x07ff) << 2; | |
150 | u32 subc = (addr & 0x3800) >> 11; | |
151 | u32 data = nv_rd32(dev, 0x104044); | |
152 | int chid = nv50_graph_isr_chid(dev, inst); | |
153 | ||
154 | if (stat & 0x00000040) { | |
155 | NV_INFO(dev, "PCOPY: DISPATCH_ERROR ["); | |
156 | nouveau_enum_print(nva3_copy_isr_error_name, ssta); | |
157 | printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n", | |
158 | chid, inst, subc, mthd, data); | |
159 | nv_wr32(dev, 0x104004, 0x00000040); | |
160 | stat &= ~0x00000040; | |
161 | } | |
162 | ||
163 | if (stat) { | |
164 | NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat); | |
165 | nv_wr32(dev, 0x104004, stat); | |
166 | } | |
167 | nv50_fb_vm_trap(dev, 1); | |
168 | } | |
169 | ||
170 | static void | |
171 | nva3_copy_destroy(struct drm_device *dev, int engine) | |
172 | { | |
173 | struct nva3_copy_engine *pcopy = nv_engine(dev, engine); | |
174 | ||
175 | nouveau_irq_unregister(dev, 22); | |
176 | ||
177 | NVOBJ_ENGINE_DEL(dev, COPY0); | |
178 | kfree(pcopy); | |
179 | } | |
180 | ||
181 | int | |
182 | nva3_copy_create(struct drm_device *dev) | |
183 | { | |
184 | struct nva3_copy_engine *pcopy; | |
185 | ||
186 | pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL); | |
187 | if (!pcopy) | |
188 | return -ENOMEM; | |
189 | ||
190 | pcopy->base.destroy = nva3_copy_destroy; | |
191 | pcopy->base.init = nva3_copy_init; | |
192 | pcopy->base.fini = nva3_copy_fini; | |
193 | pcopy->base.context_new = nva3_copy_context_new; | |
194 | pcopy->base.context_del = nva3_copy_context_del; | |
195 | pcopy->base.object_new = nva3_copy_object_new; | |
196 | pcopy->base.tlb_flush = nva3_copy_tlb_flush; | |
197 | ||
198 | nouveau_irq_register(dev, 22, nva3_copy_isr); | |
199 | ||
200 | NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base); | |
201 | NVOBJ_CLASS(dev, 0x85b5, COPY0); | |
202 | return 0; | |
203 | } |