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drm/nouveau: port remainder of drm code, and rip out compat layer
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nvc0_fence.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
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25#include <core/object.h>
26#include <core/client.h>
27#include <core/class.h>
28
02a841d4 29#include <engine/fifo.h>
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30
31#include "nouveau_drm.h"
32#include "nouveau_dma.h"
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33#include "nouveau_fence.h"
34
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35#include "nv50_display.h"
36
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37struct nvc0_fence_priv {
38 struct nouveau_fence_priv base;
39 struct nouveau_bo *bo;
d6ba6d21 40 u32 *suspend;
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41};
42
43struct nvc0_fence_chan {
44 struct nouveau_fence_chan base;
45 struct nouveau_vma vma;
f589be88 46 struct nouveau_vma dispc_vma[4];
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47};
48
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49u64
50nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
51{
52 struct nvc0_fence_chan *fctx = chan->fence;
53 return fctx->dispc_vma[crtc].offset;
54}
55
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56static int
57nvc0_fence_emit(struct nouveau_fence *fence)
58{
59 struct nouveau_channel *chan = fence->channel;
e193b1d4 60 struct nvc0_fence_chan *fctx = chan->fence;
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61 struct nouveau_fifo_chan *fifo = (void *)chan->object;
62 u64 addr = fctx->vma.offset + fifo->chid * 16;
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63 int ret;
64
65 ret = RING_SPACE(chan, 5);
66 if (ret == 0) {
67 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
68 OUT_RING (chan, upper_32_bits(addr));
69 OUT_RING (chan, lower_32_bits(addr));
70 OUT_RING (chan, fence->sequence);
71 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
72 FIRE_RING (chan);
73 }
74
75 return ret;
76}
77
78static int
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79nvc0_fence_sync(struct nouveau_fence *fence,
80 struct nouveau_channel *prev, struct nouveau_channel *chan)
5e120f6e 81{
e193b1d4 82 struct nvc0_fence_chan *fctx = chan->fence;
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83 struct nouveau_fifo_chan *fifo = (void *)prev->object;
84 u64 addr = fctx->vma.offset + fifo->chid * 16;
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85 int ret;
86
87 ret = RING_SPACE(chan, 5);
88 if (ret == 0) {
89 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
90 OUT_RING (chan, upper_32_bits(addr));
91 OUT_RING (chan, lower_32_bits(addr));
92 OUT_RING (chan, fence->sequence);
93 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
94 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
95 FIRE_RING (chan);
96 }
97
98 return ret;
99}
100
101static u32
102nvc0_fence_read(struct nouveau_channel *chan)
103{
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104 struct nouveau_fifo_chan *fifo = (void *)chan->object;
105 struct nvc0_fence_priv *priv = chan->drm->fence;
106 return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
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107}
108
109static void
e193b1d4 110nvc0_fence_context_del(struct nouveau_channel *chan)
5e120f6e 111{
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112 struct drm_device *dev = chan->drm->dev;
113 struct nvc0_fence_priv *priv = chan->drm->fence;
e193b1d4 114 struct nvc0_fence_chan *fctx = chan->fence;
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115 int i;
116
ebb945a9 117 if (nv_device(chan->drm->device)->card_type >= NV_D0) {
f589be88 118 for (i = 0; i < dev->mode_config.num_crtc; i++) {
77145f1c 119 struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
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120 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
121 }
122 } else
ebb945a9 123 if (nv_device(chan->drm->device)->card_type >= NV_50) {
f589be88 124 for (i = 0; i < dev->mode_config.num_crtc; i++) {
77145f1c 125 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
ebb945a9 126 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
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127 }
128 }
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129
130 nouveau_bo_vma_del(priv->bo, &fctx->vma);
131 nouveau_fence_context_del(&fctx->base);
e193b1d4 132 chan->fence = NULL;
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133 kfree(fctx);
134}
135
136static int
e193b1d4 137nvc0_fence_context_new(struct nouveau_channel *chan)
5e120f6e 138{
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139 struct nouveau_fifo_chan *fifo = (void *)chan->object;
140 struct nouveau_client *client = nouveau_client(fifo);
141 struct nvc0_fence_priv *priv = chan->drm->fence;
5e120f6e 142 struct nvc0_fence_chan *fctx;
f589be88 143 int ret, i;
5e120f6e 144
e193b1d4 145 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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146 if (!fctx)
147 return -ENOMEM;
148
149 nouveau_fence_context_new(&fctx->base);
150
ebb945a9 151 ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
5e120f6e 152 if (ret)
e193b1d4 153 nvc0_fence_context_del(chan);
5e120f6e 154
f589be88 155 /* map display semaphore buffers into channel's vm */
ebb945a9 156 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
f589be88 157 struct nouveau_bo *bo;
ebb945a9 158 if (nv_device(chan->drm->device)->card_type >= NV_D0)
77145f1c 159 bo = nvd0_display_crtc_sema(chan->drm->dev, i);
f589be88 160 else
77145f1c 161 bo = nv50_display_crtc_sema(chan->drm->dev, i);
f589be88 162
ebb945a9 163 ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
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164 }
165
ebb945a9 166 nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);
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167 return ret;
168}
169
e193b1d4 170static bool
ebb945a9 171nvc0_fence_suspend(struct nouveau_drm *drm)
5e120f6e 172{
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173 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
174 struct nvc0_fence_priv *priv = drm->fence;
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175 int i;
176
ebb945a9 177 priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
e193b1d4 178 if (priv->suspend) {
ebb945a9 179 for (i = 0; i <= pfifo->max; i++)
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180 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
181 }
182
e193b1d4 183 return priv->suspend != NULL;
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184}
185
e193b1d4 186static void
ebb945a9 187nvc0_fence_resume(struct nouveau_drm *drm)
5e120f6e 188{
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189 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
190 struct nvc0_fence_priv *priv = drm->fence;
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191 int i;
192
193 if (priv->suspend) {
ebb945a9 194 for (i = 0; i <= pfifo->max; i++)
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195 nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
196 vfree(priv->suspend);
197 priv->suspend = NULL;
198 }
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199}
200
201static void
ebb945a9 202nvc0_fence_destroy(struct nouveau_drm *drm)
5e120f6e 203{
ebb945a9 204 struct nvc0_fence_priv *priv = drm->fence;
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205 nouveau_bo_unmap(priv->bo);
206 nouveau_bo_ref(NULL, &priv->bo);
ebb945a9 207 drm->fence = NULL;
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208 kfree(priv);
209}
210
211int
ebb945a9 212nvc0_fence_create(struct nouveau_drm *drm)
5e120f6e 213{
ebb945a9 214 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
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215 struct nvc0_fence_priv *priv;
216 int ret;
217
ebb945a9 218 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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219 if (!priv)
220 return -ENOMEM;
221
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222 priv->base.dtor = nvc0_fence_destroy;
223 priv->base.suspend = nvc0_fence_suspend;
224 priv->base.resume = nvc0_fence_resume;
225 priv->base.context_new = nvc0_fence_context_new;
226 priv->base.context_del = nvc0_fence_context_del;
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227 priv->base.emit = nvc0_fence_emit;
228 priv->base.sync = nvc0_fence_sync;
229 priv->base.read = nvc0_fence_read;
5e120f6e 230
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231 ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
232 TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
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233 if (ret == 0) {
234 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
235 if (ret == 0)
236 ret = nouveau_bo_map(priv->bo);
237 if (ret)
238 nouveau_bo_ref(NULL, &priv->bo);
239 }
240
241 if (ret)
ebb945a9 242 nvc0_fence_destroy(drm);
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243 return ret;
244}