[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nvc0_fence.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include <engine/fifo.h>
#include <core/ramht.h>
#include "nouveau_fence.h"
#include "nv50_display.h"

struct nvc0_fence_priv {
	struct nouveau_fence_priv base;
	struct nouveau_bo *bo;
	u32 *suspend;
};

struct nvc0_fence_chan {
	struct nouveau_fence_chan base;
	struct nouveau_vma vma;
	struct nouveau_vma dispc_vma[4];
};

u64
nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
{
	struct nvc0_fence_chan *fctx = chan->fence;
	return fctx->dispc_vma[crtc].offset;
}

static int
nvc0_fence_emit(struct nouveau_fence *fence)
{
	struct nouveau_channel *chan = fence->channel;
	struct nvc0_fence_chan *fctx = chan->fence;
	u64 addr = fctx->vma.offset + chan->id * 16;
	int ret;

	ret = RING_SPACE(chan, 5);
	if (ret == 0) {
		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(addr));
		OUT_RING  (chan, lower_32_bits(addr));
		OUT_RING  (chan, fence->sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
		FIRE_RING (chan);
	}

	return ret;
}

static int
nvc0_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nvc0_fence_chan *fctx = chan->fence;
	u64 addr = fctx->vma.offset + prev->id * 16;
	int ret;

	ret = RING_SPACE(chan, 5);
	if (ret == 0) {
		BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
		OUT_RING  (chan, upper_32_bits(addr));
		OUT_RING  (chan, lower_32_bits(addr));
		OUT_RING  (chan, fence->sequence);
		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
				 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
		FIRE_RING (chan);
	}

	return ret;
}

static u32
nvc0_fence_read(struct nouveau_channel *chan)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
}

static void
nvc0_fence_context_del(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	struct nvc0_fence_chan *fctx = chan->fence;
	int i;

	if (dev_priv->card_type >= NV_D0) {
		for (i = 0; i < dev->mode_config.num_crtc; i++) {
			struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
			nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
		}
	} else
	if (dev_priv->card_type >= NV_50) {
		struct nv50_display *disp = nv50_display(dev);
		for (i = 0; i < dev->mode_config.num_crtc; i++) {
			struct nv50_display_crtc *dispc = &disp->crtc[i];
			nouveau_bo_vma_del(dispc->sem.bo, &fctx->dispc_vma[i]);
		}
	}

	nouveau_bo_vma_del(priv->bo, &fctx->vma);
	nouveau_fence_context_del(&fctx->base);
	chan->fence = NULL;
	kfree(fctx);
}

static int
nvc0_fence_context_new(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	struct nvc0_fence_chan *fctx;
	int ret, i;

	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);

	ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
	if (ret)
		nvc0_fence_context_del(chan);

	/* map display semaphore buffers into channel's vm */
	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
		struct nouveau_bo *bo;
		if (dev_priv->card_type >= NV_D0)
			bo = nvd0_display_crtc_sema(dev, i);
		else
			bo = nv50_display(dev)->crtc[i].sem.bo;

		ret = nouveau_bo_vma_add(bo, chan->vm, &fctx->dispc_vma[i]);
	}

	nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
	return ret;
}

static bool
nvc0_fence_suspend(struct drm_device *dev)
{
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	int i;

	priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
	if (priv->suspend) {
		for (i = 0; i < pfifo->channels; i++)
			priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
	}

	return priv->suspend != NULL;
}

static void
nvc0_fence_resume(struct drm_device *dev)
{
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;
	int i;

	if (priv->suspend) {
		for (i = 0; i < pfifo->channels; i++)
			nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
		vfree(priv->suspend);
		priv->suspend = NULL;
	}
}

static void
nvc0_fence_destroy(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv = dev_priv->fence.func;

	nouveau_bo_unmap(priv->bo);
	nouveau_bo_ref(NULL, &priv->bo);
	dev_priv->fence.func = NULL;
	kfree(priv);
}

int
nvc0_fence_create(struct drm_device *dev)
{
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_fence_priv *priv;
	int ret;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.dtor = nvc0_fence_destroy;
	priv->base.suspend = nvc0_fence_suspend;
	priv->base.resume = nvc0_fence_resume;
	priv->base.context_new = nvc0_fence_context_new;
	priv->base.context_del = nvc0_fence_context_del;
	priv->base.emit = nvc0_fence_emit;
	priv->base.sync = nvc0_fence_sync;
	priv->base.read = nvc0_fence_read;
	dev_priv->fence.func = priv;

	ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
			     0, 0, NULL, &priv->bo);
	if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
		if (ret == 0)
			ret = nouveau_bo_map(priv->bo);
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo);
	}

	if (ret)
		nvc0_fence_destroy(dev);
	return ret;
}
Commit	Line	Data
5e120f6e BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
	27	#include "nouveau_dma.h"
02a841d4 BS	28	#include <engine/fifo.h>
02a841d4 BS	29	#include <core/ramht.h>
5e120f6e	30	#include "nouveau_fence.h"
f589be88	31	#include "nv50_display.h"
5e120f6e BS	32
	33	struct nvc0_fence_priv {
	34	struct nouveau_fence_priv base;
	35	struct nouveau_bo *bo;
d6ba6d21	36	u32 *suspend;
5e120f6e BS	37	};
	38
	39	struct nvc0_fence_chan {
	40	struct nouveau_fence_chan base;
	41	struct nouveau_vma vma;
f589be88	42	struct nouveau_vma dispc_vma[4];
5e120f6e BS	43	};
5e120f6e BS	44
f589be88 BS	45	u64
	46	nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
	47	{
	48	struct nvc0_fence_chan *fctx = chan->fence;
	49	return fctx->dispc_vma[crtc].offset;
	50	}
	51
5e120f6e BS	52	static int
	53	nvc0_fence_emit(struct nouveau_fence *fence)
	54	{
	55	struct nouveau_channel *chan = fence->channel;
e193b1d4	56	struct nvc0_fence_chan *fctx = chan->fence;
5e120f6e BS	57	u64 addr = fctx->vma.offset + chan->id * 16;
	58	int ret;
	59
	60	ret = RING_SPACE(chan, 5);
	61	if (ret == 0) {
	62	BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
	63	OUT_RING (chan, upper_32_bits(addr));
	64	OUT_RING (chan, lower_32_bits(addr));
	65	OUT_RING (chan, fence->sequence);
	66	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
	67	FIRE_RING (chan);
	68	}
	69
	70	return ret;
	71	}
	72
	73	static int
906c033e BS	74	nvc0_fence_sync(struct nouveau_fence *fence,
906c033e BS	75	struct nouveau_channel prev, struct nouveau_channel chan)
5e120f6e	76	{
e193b1d4	77	struct nvc0_fence_chan *fctx = chan->fence;
906c033e	78	u64 addr = fctx->vma.offset + prev->id * 16;
5e120f6e BS	79	int ret;
	80
	81	ret = RING_SPACE(chan, 5);
	82	if (ret == 0) {
	83	BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
	84	OUT_RING (chan, upper_32_bits(addr));
	85	OUT_RING (chan, lower_32_bits(addr));
	86	OUT_RING (chan, fence->sequence);
	87	OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL \|
	88	NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
	89	FIRE_RING (chan);
	90	}
	91
	92	return ret;
	93	}
	94
	95	static u32
	96	nvc0_fence_read(struct nouveau_channel *chan)
	97	{
e193b1d4 BS	98	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
e193b1d4 BS	99	struct nvc0_fence_priv *priv = dev_priv->fence.func;
5e120f6e BS	100	return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
	101	}
	102
	103	static void
e193b1d4	104	nvc0_fence_context_del(struct nouveau_channel *chan)
5e120f6e	105	{
f589be88 BS	106	struct drm_device *dev = chan->dev;
f589be88 BS	107	struct drm_nouveau_private *dev_priv = dev->dev_private;
e193b1d4 BS	108	struct nvc0_fence_priv *priv = dev_priv->fence.func;
e193b1d4 BS	109	struct nvc0_fence_chan *fctx = chan->fence;
f589be88 BS	110	int i;
	111
	112	if (dev_priv->card_type >= NV_D0) {
	113	for (i = 0; i < dev->mode_config.num_crtc; i++) {
	114	struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
	115	nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
	116	}
	117	} else
	118	if (dev_priv->card_type >= NV_50) {
	119	struct nv50_display *disp = nv50_display(dev);
	120	for (i = 0; i < dev->mode_config.num_crtc; i++) {
	121	struct nv50_display_crtc *dispc = &disp->crtc[i];
	122	nouveau_bo_vma_del(dispc->sem.bo, &fctx->dispc_vma[i]);
	123	}
	124	}
5e120f6e BS	125
	126	nouveau_bo_vma_del(priv->bo, &fctx->vma);
	127	nouveau_fence_context_del(&fctx->base);
e193b1d4	128	chan->fence = NULL;
5e120f6e BS	129	kfree(fctx);
	130	}
	131
	132	static int
e193b1d4	133	nvc0_fence_context_new(struct nouveau_channel *chan)
5e120f6e	134	{
f589be88 BS	135	struct drm_device *dev = chan->dev;
f589be88 BS	136	struct drm_nouveau_private *dev_priv = dev->dev_private;
e193b1d4	137	struct nvc0_fence_priv *priv = dev_priv->fence.func;
5e120f6e	138	struct nvc0_fence_chan *fctx;
f589be88	139	int ret, i;
5e120f6e	140
e193b1d4	141	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
5e120f6e BS	142	if (!fctx)
	143	return -ENOMEM;
	144
	145	nouveau_fence_context_new(&fctx->base);
	146
	147	ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
	148	if (ret)
e193b1d4	149	nvc0_fence_context_del(chan);
5e120f6e	150
f589be88 BS	151	/* map display semaphore buffers into channel's vm */
	152	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
	153	struct nouveau_bo *bo;
	154	if (dev_priv->card_type >= NV_D0)
	155	bo = nvd0_display_crtc_sema(dev, i);
	156	else
	157	bo = nv50_display(dev)->crtc[i].sem.bo;
	158
	159	ret = nouveau_bo_vma_add(bo, chan->vm, &fctx->dispc_vma[i]);
	160	}
	161
5e120f6e BS	162	nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
	163	return ret;
	164	}
	165
e193b1d4 BS	166	static bool
e193b1d4 BS	167	nvc0_fence_suspend(struct drm_device *dev)
5e120f6e	168	{
d6ba6d21	169	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
e193b1d4 BS	170	struct drm_nouveau_private *dev_priv = dev->dev_private;
e193b1d4 BS	171	struct nvc0_fence_priv *priv = dev_priv->fence.func;
d6ba6d21 BS	172	int i;
d6ba6d21 BS	173
e193b1d4 BS	174	priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
e193b1d4 BS	175	if (priv->suspend) {
d6ba6d21 BS	176	for (i = 0; i < pfifo->channels; i++)
	177	priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
	178	}
	179
e193b1d4	180	return priv->suspend != NULL;
5e120f6e BS	181	}
5e120f6e BS	182
e193b1d4 BS	183	static void
e193b1d4 BS	184	nvc0_fence_resume(struct drm_device *dev)
5e120f6e	185	{
d6ba6d21	186	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
e193b1d4 BS	187	struct drm_nouveau_private *dev_priv = dev->dev_private;
e193b1d4 BS	188	struct nvc0_fence_priv *priv = dev_priv->fence.func;
d6ba6d21 BS	189	int i;
	190
	191	if (priv->suspend) {
	192	for (i = 0; i < pfifo->channels; i++)
	193	nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
	194	vfree(priv->suspend);
	195	priv->suspend = NULL;
	196	}
5e120f6e BS	197	}
	198
	199	static void
e193b1d4	200	nvc0_fence_destroy(struct drm_device *dev)
5e120f6e BS	201	{
5e120f6e BS	202	struct drm_nouveau_private *dev_priv = dev->dev_private;
e193b1d4	203	struct nvc0_fence_priv *priv = dev_priv->fence.func;
5e120f6e BS	204
	205	nouveau_bo_unmap(priv->bo);
	206	nouveau_bo_ref(NULL, &priv->bo);
e193b1d4	207	dev_priv->fence.func = NULL;
5e120f6e BS	208	kfree(priv);
	209	}
	210
	211	int
	212	nvc0_fence_create(struct drm_device *dev)
	213	{
c420b2dc	214	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
5e120f6e	215	struct drm_nouveau_private *dev_priv = dev->dev_private;
5e120f6e BS	216	struct nvc0_fence_priv *priv;
	217	int ret;
	218
	219	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	220	if (!priv)
	221	return -ENOMEM;
	222
e193b1d4 BS	223	priv->base.dtor = nvc0_fence_destroy;
	224	priv->base.suspend = nvc0_fence_suspend;
	225	priv->base.resume = nvc0_fence_resume;
	226	priv->base.context_new = nvc0_fence_context_new;
	227	priv->base.context_del = nvc0_fence_context_del;
5e120f6e BS	228	priv->base.emit = nvc0_fence_emit;
	229	priv->base.sync = nvc0_fence_sync;
	230	priv->base.read = nvc0_fence_read;
e193b1d4	231	dev_priv->fence.func = priv;
5e120f6e BS	232
	233	ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
	234	0, 0, NULL, &priv->bo);
	235	if (ret == 0) {
	236	ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
	237	if (ret == 0)
	238	ret = nouveau_bo_map(priv->bo);
	239	if (ret)
	240	nouveau_bo_ref(NULL, &priv->bo);
	241	}
	242
	243	if (ret)
e193b1d4	244	nvc0_fence_destroy(dev);
5e120f6e BS	245	return ret;
5e120f6e BS	246	}