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4b223eef BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
966a5b7d BS |
25 | #include <linux/firmware.h> |
26 | ||
4b223eef BS |
27 | #include "drmP.h" |
28 | ||
29 | #include "nouveau_drv.h" | |
966a5b7d BS |
30 | #include "nouveau_mm.h" |
31 | #include "nvc0_graph.h" | |
32 | ||
33 | static void nvc0_graph_isr(struct drm_device *); | |
51f73d64 | 34 | static void nvc0_runk140_isr(struct drm_device *); |
966a5b7d | 35 | static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan); |
4b223eef BS |
36 | |
37 | void | |
38 | nvc0_graph_fifo_access(struct drm_device *dev, bool enabled) | |
39 | { | |
40 | } | |
41 | ||
42 | struct nouveau_channel * | |
43 | nvc0_graph_channel(struct drm_device *dev) | |
44 | { | |
45 | return NULL; | |
46 | } | |
47 | ||
966a5b7d BS |
48 | static int |
49 | nvc0_graph_construct_context(struct nouveau_channel *chan) | |
50 | { | |
51 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
52 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
53 | struct nvc0_graph_chan *grch = chan->pgraph_ctx; | |
54 | struct drm_device *dev = chan->dev; | |
55 | int ret, i; | |
56 | u32 *ctx; | |
57 | ||
58 | ctx = kmalloc(priv->grctx_size, GFP_KERNEL); | |
59 | if (!ctx) | |
60 | return -ENOMEM; | |
61 | ||
62 | nvc0_graph_load_context(chan); | |
63 | ||
64 | nv_wo32(grch->grctx, 0x1c, 1); | |
65 | nv_wo32(grch->grctx, 0x20, 0); | |
66 | nv_wo32(grch->grctx, 0x28, 0); | |
67 | nv_wo32(grch->grctx, 0x2c, 0); | |
68 | dev_priv->engine.instmem.flush(dev); | |
69 | ||
70 | ret = nvc0_grctx_generate(chan); | |
71 | if (ret) { | |
72 | kfree(ctx); | |
73 | return ret; | |
74 | } | |
75 | ||
76 | ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); | |
77 | if (ret) { | |
78 | kfree(ctx); | |
79 | return ret; | |
80 | } | |
81 | ||
82 | for (i = 0; i < priv->grctx_size; i += 4) | |
83 | ctx[i / 4] = nv_ro32(grch->grctx, i); | |
84 | ||
85 | priv->grctx_vals = ctx; | |
86 | return 0; | |
87 | } | |
88 | ||
89 | static int | |
90 | nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) | |
91 | { | |
92 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
93 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
94 | struct nvc0_graph_chan *grch = chan->pgraph_ctx; | |
95 | struct drm_device *dev = chan->dev; | |
96 | int i = 0, gpc, tp, ret; | |
97 | u32 magic; | |
98 | ||
99 | ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM, | |
100 | &grch->unk408004); | |
101 | if (ret) | |
102 | return ret; | |
103 | ||
104 | ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM, | |
105 | &grch->unk40800c); | |
106 | if (ret) | |
107 | return ret; | |
108 | ||
c906ca0f BS |
109 | ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, |
110 | NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER, | |
966a5b7d BS |
111 | &grch->unk418810); |
112 | if (ret) | |
113 | return ret; | |
114 | ||
115 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM, | |
116 | &grch->mmio); | |
117 | if (ret) | |
118 | return ret; | |
119 | ||
120 | ||
121 | nv_wo32(grch->mmio, i++ * 4, 0x00408004); | |
122 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8); | |
123 | nv_wo32(grch->mmio, i++ * 4, 0x00408008); | |
124 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); | |
125 | ||
126 | nv_wo32(grch->mmio, i++ * 4, 0x0040800c); | |
127 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8); | |
128 | nv_wo32(grch->mmio, i++ * 4, 0x00408010); | |
129 | nv_wo32(grch->mmio, i++ * 4, 0x80000000); | |
130 | ||
131 | nv_wo32(grch->mmio, i++ * 4, 0x00418810); | |
132 | nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12); | |
133 | nv_wo32(grch->mmio, i++ * 4, 0x00419848); | |
134 | nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12); | |
135 | ||
136 | nv_wo32(grch->mmio, i++ * 4, 0x00419004); | |
137 | nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8); | |
138 | nv_wo32(grch->mmio, i++ * 4, 0x00419008); | |
139 | nv_wo32(grch->mmio, i++ * 4, 0x00000000); | |
140 | ||
141 | nv_wo32(grch->mmio, i++ * 4, 0x00418808); | |
142 | nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8); | |
143 | nv_wo32(grch->mmio, i++ * 4, 0x0041880c); | |
144 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); | |
145 | ||
146 | magic = 0x02180000; | |
147 | nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
148 | nv_wo32(grch->mmio, i++ * 4, magic); | |
149 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
150 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) { | |
151 | u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800); | |
152 | nv_wo32(grch->mmio, i++ * 4, reg); | |
153 | nv_wo32(grch->mmio, i++ * 4, magic); | |
154 | } | |
155 | } | |
156 | ||
157 | grch->mmio_nr = i / 2; | |
158 | return 0; | |
159 | } | |
160 | ||
4b223eef BS |
161 | int |
162 | nvc0_graph_create_context(struct nouveau_channel *chan) | |
163 | { | |
966a5b7d BS |
164 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
165 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; | |
166 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
167 | struct nvc0_graph_priv *priv = pgraph->priv; | |
168 | struct nvc0_graph_chan *grch; | |
169 | struct drm_device *dev = chan->dev; | |
170 | struct nouveau_gpuobj *grctx; | |
171 | int ret, i; | |
172 | ||
173 | chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL); | |
174 | if (!chan->pgraph_ctx) | |
175 | return -ENOMEM; | |
176 | grch = chan->pgraph_ctx; | |
177 | ||
178 | ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256, | |
179 | NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC, | |
180 | &grch->grctx); | |
181 | if (ret) | |
182 | goto error; | |
183 | chan->ramin_grctx = grch->grctx; | |
184 | grctx = grch->grctx; | |
185 | ||
186 | ret = nvc0_graph_create_context_mmio_list(chan); | |
187 | if (ret) | |
188 | goto error; | |
189 | ||
190 | nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4); | |
191 | nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst)); | |
192 | pinstmem->flush(dev); | |
193 | ||
194 | if (!priv->grctx_vals) { | |
195 | ret = nvc0_graph_construct_context(chan); | |
196 | if (ret) | |
197 | goto error; | |
198 | } | |
199 | ||
200 | for (i = 0; i < priv->grctx_size; i += 4) | |
201 | nv_wo32(grctx, i, priv->grctx_vals[i / 4]); | |
202 | ||
71298e2f EV |
203 | nv_wo32(grctx, 0xf4, 0); |
204 | nv_wo32(grctx, 0xf8, 0); | |
205 | nv_wo32(grctx, 0x10, grch->mmio_nr); | |
206 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst)); | |
207 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst)); | |
208 | nv_wo32(grctx, 0x1c, 1); | |
209 | nv_wo32(grctx, 0x20, 0); | |
210 | nv_wo32(grctx, 0x28, 0); | |
211 | nv_wo32(grctx, 0x2c, 0); | |
966a5b7d | 212 | pinstmem->flush(dev); |
4b223eef | 213 | return 0; |
966a5b7d BS |
214 | |
215 | error: | |
216 | pgraph->destroy_context(chan); | |
217 | return ret; | |
4b223eef BS |
218 | } |
219 | ||
220 | void | |
221 | nvc0_graph_destroy_context(struct nouveau_channel *chan) | |
222 | { | |
966a5b7d BS |
223 | struct nvc0_graph_chan *grch; |
224 | ||
225 | grch = chan->pgraph_ctx; | |
226 | chan->pgraph_ctx = NULL; | |
227 | if (!grch) | |
228 | return; | |
229 | ||
230 | nouveau_gpuobj_ref(NULL, &grch->mmio); | |
231 | nouveau_gpuobj_ref(NULL, &grch->unk418810); | |
232 | nouveau_gpuobj_ref(NULL, &grch->unk40800c); | |
233 | nouveau_gpuobj_ref(NULL, &grch->unk408004); | |
234 | nouveau_gpuobj_ref(NULL, &grch->grctx); | |
235 | chan->ramin_grctx = NULL; | |
4b223eef BS |
236 | } |
237 | ||
238 | int | |
239 | nvc0_graph_load_context(struct nouveau_channel *chan) | |
240 | { | |
966a5b7d BS |
241 | struct drm_device *dev = chan->dev; |
242 | ||
243 | nv_wr32(dev, 0x409840, 0x00000030); | |
244 | nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12); | |
245 | nv_wr32(dev, 0x409504, 0x00000003); | |
246 | if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010)) | |
247 | NV_ERROR(dev, "PGRAPH: load_ctx timeout\n"); | |
248 | ||
966a5b7d BS |
249 | return 0; |
250 | } | |
251 | ||
252 | static int | |
253 | nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan) | |
254 | { | |
255 | nv_wr32(dev, 0x409840, 0x00000003); | |
256 | nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12); | |
257 | nv_wr32(dev, 0x409504, 0x00000009); | |
258 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) { | |
259 | NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n"); | |
260 | return -EBUSY; | |
261 | } | |
262 | ||
4b223eef BS |
263 | return 0; |
264 | } | |
265 | ||
266 | int | |
267 | nvc0_graph_unload_context(struct drm_device *dev) | |
268 | { | |
966a5b7d BS |
269 | u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; |
270 | return nvc0_graph_unload_context_to(dev, inst); | |
271 | } | |
272 | ||
4ea52f89 BS |
273 | int |
274 | nvc0_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class) | |
275 | { | |
276 | return 0; | |
277 | } | |
278 | ||
966a5b7d BS |
279 | static void |
280 | nvc0_graph_destroy(struct drm_device *dev) | |
281 | { | |
282 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
283 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
284 | struct nvc0_graph_priv *priv; | |
285 | ||
286 | priv = pgraph->priv; | |
287 | if (!priv) | |
288 | return; | |
289 | ||
290 | nouveau_irq_unregister(dev, 12); | |
51f73d64 | 291 | nouveau_irq_unregister(dev, 25); |
966a5b7d BS |
292 | |
293 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); | |
294 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); | |
295 | ||
296 | if (priv->grctx_vals) | |
297 | kfree(priv->grctx_vals); | |
298 | kfree(priv); | |
4b223eef BS |
299 | } |
300 | ||
301 | void | |
302 | nvc0_graph_takedown(struct drm_device *dev) | |
303 | { | |
966a5b7d BS |
304 | nvc0_graph_destroy(dev); |
305 | } | |
306 | ||
bd2f2037 BS |
307 | static int |
308 | nvc0_graph_mthd_page_flip(struct nouveau_channel *chan, | |
309 | u32 class, u32 mthd, u32 data) | |
310 | { | |
311 | nouveau_finish_page_flip(chan, NULL); | |
312 | return 0; | |
313 | } | |
314 | ||
966a5b7d BS |
315 | static int |
316 | nvc0_graph_create(struct drm_device *dev) | |
317 | { | |
318 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
319 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
320 | struct nvc0_graph_priv *priv; | |
321 | int ret, gpc, i; | |
322 | ||
323 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
324 | if (!priv) | |
325 | return -ENOMEM; | |
326 | pgraph->priv = priv; | |
327 | ||
328 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); | |
329 | if (ret) | |
330 | goto error; | |
331 | ||
332 | ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8); | |
333 | if (ret) | |
334 | goto error; | |
335 | ||
336 | for (i = 0; i < 0x1000; i += 4) { | |
337 | nv_wo32(priv->unk4188b4, i, 0x00000010); | |
338 | nv_wo32(priv->unk4188b8, i, 0x00000010); | |
339 | } | |
340 | ||
341 | priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f; | |
342 | priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16; | |
343 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
344 | priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608)); | |
345 | priv->tp_total += priv->tp_nr[gpc]; | |
346 | } | |
347 | ||
348 | /*XXX: these need figuring out... */ | |
349 | switch (dev_priv->chipset) { | |
350 | case 0xc0: | |
351 | if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */ | |
352 | priv->magic_not_rop_nr = 0x07; | |
966a5b7d BS |
353 | /* filled values up to tp_total, the rest 0 */ |
354 | priv->magicgpc980[0] = 0x22111000; | |
355 | priv->magicgpc980[1] = 0x00000233; | |
356 | priv->magicgpc980[2] = 0x00000000; | |
357 | priv->magicgpc980[3] = 0x00000000; | |
358 | priv->magicgpc918 = 0x000ba2e9; | |
359 | } else | |
360 | if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */ | |
361 | priv->magic_not_rop_nr = 0x05; | |
966a5b7d BS |
362 | priv->magicgpc980[0] = 0x11110000; |
363 | priv->magicgpc980[1] = 0x00233222; | |
364 | priv->magicgpc980[2] = 0x00000000; | |
365 | priv->magicgpc980[3] = 0x00000000; | |
366 | priv->magicgpc918 = 0x00092493; | |
367 | } else | |
368 | if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */ | |
369 | priv->magic_not_rop_nr = 0x06; | |
966a5b7d BS |
370 | priv->magicgpc980[0] = 0x11110000; |
371 | priv->magicgpc980[1] = 0x03332222; | |
372 | priv->magicgpc980[2] = 0x00000000; | |
373 | priv->magicgpc980[3] = 0x00000000; | |
374 | priv->magicgpc918 = 0x00088889; | |
375 | } | |
376 | break; | |
377 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
378 | priv->magic_not_rop_nr = 0x03; | |
966a5b7d BS |
379 | priv->magicgpc980[0] = 0x00003210; |
380 | priv->magicgpc980[1] = 0x00000000; | |
381 | priv->magicgpc980[2] = 0x00000000; | |
382 | priv->magicgpc980[3] = 0x00000000; | |
383 | priv->magicgpc918 = 0x00200000; | |
384 | break; | |
385 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
386 | priv->magic_not_rop_nr = 0x01; | |
966a5b7d BS |
387 | priv->magicgpc980[0] = 0x02321100; |
388 | priv->magicgpc980[1] = 0x00000000; | |
389 | priv->magicgpc980[2] = 0x00000000; | |
390 | priv->magicgpc980[3] = 0x00000000; | |
391 | priv->magicgpc918 = 0x00124925; | |
392 | break; | |
393 | } | |
394 | ||
b1cd916a | 395 | if (!priv->magic_not_rop_nr) { |
966a5b7d BS |
396 | NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n", |
397 | priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2], | |
398 | priv->tp_nr[3], priv->rop_nr); | |
399 | /* use 0xc3's values... */ | |
400 | priv->magic_not_rop_nr = 0x03; | |
966a5b7d BS |
401 | priv->magicgpc980[0] = 0x00003210; |
402 | priv->magicgpc980[1] = 0x00000000; | |
403 | priv->magicgpc980[2] = 0x00000000; | |
404 | priv->magicgpc980[3] = 0x00000000; | |
405 | priv->magicgpc918 = 0x00200000; | |
406 | } | |
407 | ||
408 | nouveau_irq_register(dev, 12, nvc0_graph_isr); | |
51f73d64 | 409 | nouveau_irq_register(dev, 25, nvc0_runk140_isr); |
966a5b7d BS |
410 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ |
411 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ | |
bd2f2037 | 412 | NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip); |
966a5b7d BS |
413 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ |
414 | NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ | |
415 | return 0; | |
416 | ||
417 | error: | |
418 | nvc0_graph_destroy(dev); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | static void | |
423 | nvc0_graph_init_obj418880(struct drm_device *dev) | |
424 | { | |
425 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
426 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
427 | struct nvc0_graph_priv *priv = pgraph->priv; | |
428 | int i; | |
429 | ||
430 | nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000); | |
431 | nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000); | |
432 | for (i = 0; i < 4; i++) | |
433 | nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000); | |
434 | nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8); | |
435 | nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8); | |
436 | } | |
437 | ||
438 | static void | |
439 | nvc0_graph_init_regs(struct drm_device *dev) | |
440 | { | |
441 | nv_wr32(dev, 0x400080, 0x003083c2); | |
442 | nv_wr32(dev, 0x400088, 0x00006fe7); | |
443 | nv_wr32(dev, 0x40008c, 0x00000000); | |
444 | nv_wr32(dev, 0x400090, 0x00000030); | |
445 | nv_wr32(dev, 0x40013c, 0x013901f7); | |
446 | nv_wr32(dev, 0x400140, 0x00000100); | |
447 | nv_wr32(dev, 0x400144, 0x00000000); | |
448 | nv_wr32(dev, 0x400148, 0x00000110); | |
449 | nv_wr32(dev, 0x400138, 0x00000000); | |
450 | nv_wr32(dev, 0x400130, 0x00000000); | |
451 | nv_wr32(dev, 0x400134, 0x00000000); | |
452 | nv_wr32(dev, 0x400124, 0x00000002); | |
453 | } | |
454 | ||
455 | static void | |
456 | nvc0_graph_init_gpc_0(struct drm_device *dev) | |
457 | { | |
458 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
459 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
460 | int gpc; | |
f212949c EV |
461 | |
462 | /* | |
463 | * TP ROP UNKVAL(magic_not_rop_nr) | |
464 | * 450: 4/0/0/0 2 3 | |
465 | * 460: 3/4/0/0 4 1 | |
466 | * 465: 3/4/4/0 4 7 | |
467 | * 470: 3/3/4/4 5 5 | |
468 | * 480: 3/4/4/4 6 6 | |
469 | ||
470 | * magicgpc918 | |
471 | * 450: 00200000 00000000001000000000000000000000 | |
472 | * 460: 00124925 00000000000100100100100100100101 | |
473 | * 465: 000ba2e9 00000000000010111010001011101001 | |
474 | * 470: 00092493 00000000000010010010010010010011 | |
475 | * 480: 00088889 00000000000010001000100010001001 | |
476 | ||
477 | * filled values up to tp_total, remainder 0 | |
478 | * 450: 00003210 00000000 00000000 00000000 | |
479 | * 460: 02321100 00000000 00000000 00000000 | |
480 | * 465: 22111000 00000233 00000000 00000000 | |
481 | * 470: 11110000 00233222 00000000 00000000 | |
482 | * 480: 11110000 03332222 00000000 00000000 | |
483 | */ | |
484 | ||
966a5b7d BS |
485 | nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]); |
486 | nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]); | |
487 | nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]); | |
488 | nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]); | |
489 | ||
490 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
491 | nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | | |
492 | priv->tp_nr[gpc]); | |
493 | nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total); | |
494 | nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918); | |
495 | } | |
496 | ||
497 | nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918); | |
498 | nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr); | |
499 | } | |
500 | ||
501 | static void | |
502 | nvc0_graph_init_units(struct drm_device *dev) | |
503 | { | |
504 | nv_wr32(dev, 0x409c24, 0x000f0000); | |
505 | nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */ | |
506 | nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */ | |
507 | nv_wr32(dev, 0x408030, 0xc0000000); | |
508 | nv_wr32(dev, 0x40601c, 0xc0000000); | |
509 | nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */ | |
510 | nv_wr32(dev, 0x406018, 0xc0000000); | |
511 | nv_wr32(dev, 0x405840, 0xc0000000); | |
512 | nv_wr32(dev, 0x405844, 0x00ffffff); | |
513 | nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008); | |
514 | nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000); | |
515 | } | |
516 | ||
517 | static void | |
518 | nvc0_graph_init_gpc_1(struct drm_device *dev) | |
519 | { | |
520 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
521 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
522 | int gpc, tp; | |
523 | ||
524 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
525 | nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000); | |
526 | nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
527 | nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
528 | nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
529 | for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
530 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff); | |
531 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff); | |
532 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000); | |
533 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000); | |
534 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000); | |
0f1cb203 BS |
535 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe); |
536 | nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f); | |
966a5b7d BS |
537 | } |
538 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff); | |
539 | nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
540 | } | |
541 | } | |
542 | ||
543 | static void | |
544 | nvc0_graph_init_rop(struct drm_device *dev) | |
545 | { | |
546 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
547 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
548 | int rop; | |
549 | ||
550 | for (rop = 0; rop < priv->rop_nr; rop++) { | |
551 | nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000); | |
552 | nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000); | |
553 | nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff); | |
554 | nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff); | |
555 | } | |
556 | } | |
557 | ||
558 | static int | |
559 | nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base, | |
560 | const char *code_fw, const char *data_fw) | |
561 | { | |
562 | const struct firmware *fw; | |
563 | char name[32]; | |
564 | int ret, i; | |
565 | ||
566 | snprintf(name, sizeof(name), "nouveau/%s", data_fw); | |
567 | ret = request_firmware(&fw, name, &dev->pdev->dev); | |
568 | if (ret) { | |
569 | NV_ERROR(dev, "failed to load %s\n", data_fw); | |
570 | return ret; | |
571 | } | |
572 | ||
573 | nv_wr32(dev, fuc_base + 0x01c0, 0x01000000); | |
574 | for (i = 0; i < fw->size / 4; i++) | |
575 | nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]); | |
576 | release_firmware(fw); | |
577 | ||
578 | snprintf(name, sizeof(name), "nouveau/%s", code_fw); | |
579 | ret = request_firmware(&fw, name, &dev->pdev->dev); | |
580 | if (ret) { | |
581 | NV_ERROR(dev, "failed to load %s\n", code_fw); | |
582 | return ret; | |
583 | } | |
584 | ||
585 | nv_wr32(dev, fuc_base + 0x0180, 0x01000000); | |
586 | for (i = 0; i < fw->size / 4; i++) { | |
587 | if ((i & 0x3f) == 0) | |
588 | nv_wr32(dev, fuc_base + 0x0188, i >> 6); | |
589 | nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]); | |
590 | } | |
591 | release_firmware(fw); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int | |
597 | nvc0_graph_init_ctxctl(struct drm_device *dev) | |
598 | { | |
599 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
600 | struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv; | |
601 | u32 r000260; | |
602 | int ret; | |
603 | ||
604 | /* load fuc microcode */ | |
605 | r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); | |
606 | ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d"); | |
607 | if (ret == 0) | |
eeb9cc01 | 608 | ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad"); |
966a5b7d BS |
609 | nv_wr32(dev, 0x000260, r000260); |
610 | ||
611 | if (ret) | |
612 | return ret; | |
613 | ||
614 | /* start both of them running */ | |
615 | nv_wr32(dev, 0x409840, 0xffffffff); | |
616 | nv_wr32(dev, 0x41a10c, 0x00000000); | |
617 | nv_wr32(dev, 0x40910c, 0x00000000); | |
618 | nv_wr32(dev, 0x41a100, 0x00000002); | |
619 | nv_wr32(dev, 0x409100, 0x00000002); | |
620 | if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001)) | |
621 | NV_INFO(dev, "0x409800 wait failed\n"); | |
622 | ||
623 | nv_wr32(dev, 0x409840, 0xffffffff); | |
624 | nv_wr32(dev, 0x409500, 0x7fffffff); | |
625 | nv_wr32(dev, 0x409504, 0x00000021); | |
626 | ||
627 | nv_wr32(dev, 0x409840, 0xffffffff); | |
628 | nv_wr32(dev, 0x409500, 0x00000000); | |
629 | nv_wr32(dev, 0x409504, 0x00000010); | |
630 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
631 | NV_ERROR(dev, "fuc09 req 0x10 timeout\n"); | |
632 | return -EBUSY; | |
633 | } | |
634 | priv->grctx_size = nv_rd32(dev, 0x409800); | |
635 | ||
636 | nv_wr32(dev, 0x409840, 0xffffffff); | |
637 | nv_wr32(dev, 0x409500, 0x00000000); | |
638 | nv_wr32(dev, 0x409504, 0x00000016); | |
639 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
640 | NV_ERROR(dev, "fuc09 req 0x16 timeout\n"); | |
641 | return -EBUSY; | |
642 | } | |
643 | ||
644 | nv_wr32(dev, 0x409840, 0xffffffff); | |
645 | nv_wr32(dev, 0x409500, 0x00000000); | |
646 | nv_wr32(dev, 0x409504, 0x00000025); | |
647 | if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) { | |
648 | NV_ERROR(dev, "fuc09 req 0x25 timeout\n"); | |
649 | return -EBUSY; | |
650 | } | |
651 | ||
652 | return 0; | |
4b223eef BS |
653 | } |
654 | ||
655 | int | |
656 | nvc0_graph_init(struct drm_device *dev) | |
657 | { | |
658 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
966a5b7d | 659 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
966a5b7d BS |
660 | int ret; |
661 | ||
4b223eef | 662 | dev_priv->engine.graph.accel_blocked = true; |
966a5b7d BS |
663 | |
664 | switch (dev_priv->chipset) { | |
665 | case 0xc0: | |
666 | case 0xc3: | |
667 | case 0xc4: | |
668 | break; | |
669 | default: | |
670 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); | |
671 | if (nouveau_noaccel != 0) | |
672 | return 0; | |
673 | break; | |
674 | } | |
675 | ||
676 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); | |
677 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); | |
678 | ||
679 | if (!pgraph->priv) { | |
680 | ret = nvc0_graph_create(dev); | |
681 | if (ret) | |
682 | return ret; | |
683 | } | |
966a5b7d BS |
684 | |
685 | nvc0_graph_init_obj418880(dev); | |
686 | nvc0_graph_init_regs(dev); | |
f212949c | 687 | /*nvc0_graph_init_unitplemented_magics(dev);*/ |
966a5b7d | 688 | nvc0_graph_init_gpc_0(dev); |
f212949c | 689 | /*nvc0_graph_init_unitplemented_c242(dev);*/ |
966a5b7d BS |
690 | |
691 | nv_wr32(dev, 0x400500, 0x00010001); | |
692 | nv_wr32(dev, 0x400100, 0xffffffff); | |
693 | nv_wr32(dev, 0x40013c, 0xffffffff); | |
694 | ||
695 | nvc0_graph_init_units(dev); | |
696 | nvc0_graph_init_gpc_1(dev); | |
697 | nvc0_graph_init_rop(dev); | |
698 | ||
699 | nv_wr32(dev, 0x400108, 0xffffffff); | |
700 | nv_wr32(dev, 0x400138, 0xffffffff); | |
701 | nv_wr32(dev, 0x400118, 0xffffffff); | |
702 | nv_wr32(dev, 0x400130, 0xffffffff); | |
703 | nv_wr32(dev, 0x40011c, 0xffffffff); | |
704 | nv_wr32(dev, 0x400134, 0xffffffff); | |
705 | nv_wr32(dev, 0x400054, 0x34ce3464); | |
706 | ||
707 | ret = nvc0_graph_init_ctxctl(dev); | |
eeb9cc01 BS |
708 | if (ret == 0) |
709 | dev_priv->engine.graph.accel_blocked = false; | |
4b223eef BS |
710 | return 0; |
711 | } | |
712 | ||
966a5b7d BS |
713 | static int |
714 | nvc0_graph_isr_chid(struct drm_device *dev, u64 inst) | |
715 | { | |
716 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
717 | struct nouveau_channel *chan; | |
718 | unsigned long flags; | |
719 | int i; | |
720 | ||
721 | spin_lock_irqsave(&dev_priv->channels.lock, flags); | |
722 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
723 | chan = dev_priv->channels.ptr[i]; | |
724 | if (!chan || !chan->ramin) | |
725 | continue; | |
726 | ||
727 | if (inst == chan->ramin->vinst) | |
728 | break; | |
729 | } | |
730 | spin_unlock_irqrestore(&dev_priv->channels.lock, flags); | |
731 | return i; | |
732 | } | |
733 | ||
734 | static void | |
735 | nvc0_graph_isr(struct drm_device *dev) | |
736 | { | |
737 | u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; | |
738 | u32 chid = nvc0_graph_isr_chid(dev, inst); | |
739 | u32 stat = nv_rd32(dev, 0x400100); | |
740 | u32 addr = nv_rd32(dev, 0x400704); | |
741 | u32 mthd = (addr & 0x00003ffc); | |
742 | u32 subc = (addr & 0x00070000) >> 16; | |
743 | u32 data = nv_rd32(dev, 0x400708); | |
744 | u32 code = nv_rd32(dev, 0x400110); | |
745 | u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); | |
746 | ||
747 | if (stat & 0x00000010) { | |
bd2f2037 BS |
748 | if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) { |
749 | NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] " | |
750 | "subc %d class 0x%04x mthd 0x%04x " | |
751 | "data 0x%08x\n", | |
752 | chid, inst, subc, class, mthd, data); | |
753 | } | |
966a5b7d BS |
754 | nv_wr32(dev, 0x400100, 0x00000010); |
755 | stat &= ~0x00000010; | |
756 | } | |
757 | ||
eae5e7f3 BS |
758 | if (stat & 0x00000020) { |
759 | NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d " | |
760 | "class 0x%04x mthd 0x%04x data 0x%08x\n", | |
761 | chid, inst, subc, class, mthd, data); | |
762 | nv_wr32(dev, 0x400100, 0x00000020); | |
763 | stat &= ~0x00000020; | |
764 | } | |
765 | ||
966a5b7d BS |
766 | if (stat & 0x00100000) { |
767 | NV_INFO(dev, "PGRAPH: DATA_ERROR ["); | |
6effe393 | 768 | nouveau_enum_print(nv50_data_error_names, code); |
966a5b7d BS |
769 | printk("] ch %d [0x%010llx] subc %d class 0x%04x " |
770 | "mthd 0x%04x data 0x%08x\n", | |
771 | chid, inst, subc, class, mthd, data); | |
772 | nv_wr32(dev, 0x400100, 0x00100000); | |
773 | stat &= ~0x00100000; | |
774 | } | |
775 | ||
eae5e7f3 BS |
776 | if (stat & 0x00200000) { |
777 | u32 trap = nv_rd32(dev, 0x400108); | |
778 | NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap); | |
779 | nv_wr32(dev, 0x400108, trap); | |
780 | nv_wr32(dev, 0x400100, 0x00200000); | |
781 | stat &= ~0x00200000; | |
782 | } | |
783 | ||
966a5b7d BS |
784 | if (stat & 0x00080000) { |
785 | u32 ustat = nv_rd32(dev, 0x409c18); | |
786 | ||
787 | NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat); | |
788 | ||
789 | nv_wr32(dev, 0x409c20, ustat); | |
790 | nv_wr32(dev, 0x400100, 0x00080000); | |
791 | stat &= ~0x00080000; | |
792 | } | |
793 | ||
794 | if (stat) { | |
795 | NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat); | |
796 | nv_wr32(dev, 0x400100, stat); | |
797 | } | |
798 | ||
799 | nv_wr32(dev, 0x400500, 0x00010001); | |
800 | } | |
51f73d64 BS |
801 | |
802 | static void | |
803 | nvc0_runk140_isr(struct drm_device *dev) | |
804 | { | |
805 | u32 units = nv_rd32(dev, 0x00017c) & 0x1f; | |
806 | ||
807 | while (units) { | |
808 | u32 unit = ffs(units) - 1; | |
809 | u32 reg = 0x140000 + unit * 0x2000; | |
810 | u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0); | |
811 | u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0); | |
812 | ||
813 | NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1); | |
814 | units &= ~(1 << unit); | |
815 | } | |
816 | } |