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drm/nvc0: enable protection of system-use-only structures in vm
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / nvc0_graph.c
CommitLineData
4b223eef
BS		 1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
966a5b7d
BS		 25#include <linux/firmware.h>
26
4b223eef
BS		 27#include "drmP.h"
28
29#include "nouveau_drv.h"
966a5b7d
BS		 30#include "nouveau_mm.h"
31#include "nvc0_graph.h"
32
33static void nvc0_graph_isr(struct drm_device *);
34static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
4b223eef
BS		 35
36void
37nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
38{
39}
40
41struct nouveau_channel *
42nvc0_graph_channel(struct drm_device *dev)
43{
44 return NULL;
45}
46
966a5b7d
BS		 47static int
48nvc0_graph_construct_context(struct nouveau_channel *chan)
49{
50 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
51 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
52 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
53 struct drm_device *dev = chan->dev;
54 int ret, i;
55 u32 *ctx;
56
57 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
58 if (!ctx)
59 return -ENOMEM;
60
61 nvc0_graph_load_context(chan);
62
63 nv_wo32(grch->grctx, 0x1c, 1);
64 nv_wo32(grch->grctx, 0x20, 0);
65 nv_wo32(grch->grctx, 0x28, 0);
66 nv_wo32(grch->grctx, 0x2c, 0);
67 dev_priv->engine.instmem.flush(dev);
68
69 ret = nvc0_grctx_generate(chan);
70 if (ret) {
71 kfree(ctx);
72 return ret;
73 }
74
75 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
76 if (ret) {
77 kfree(ctx);
78 return ret;
79 }
80
81 for (i = 0; i < priv->grctx_size; i += 4)
82 ctx[i / 4] = nv_ro32(grch->grctx, i);
83
84 priv->grctx_vals = ctx;
85 return 0;
86}
87
88static int
89nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
90{
91 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
92 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
93 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
94 struct drm_device *dev = chan->dev;
95 int i = 0, gpc, tp, ret;
96 u32 magic;
97
98 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
99 &grch->unk408004);
100 if (ret)
101 return ret;
102
103 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
104 &grch->unk40800c);
105 if (ret)
106 return ret;
107
c906ca0f
BS		 108 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
109 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
966a5b7d
BS		 110 &grch->unk418810);
111 if (ret)
112 return ret;
113
114 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
115 &grch->mmio);
116 if (ret)
117 return ret;
118
119
120 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
121 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
122 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
123 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
124
125 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
126 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
127 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
128 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
129
130 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
131 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
132 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
133 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
134
135 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
136 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
137 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
138 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
139
140 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
141 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
142 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
143 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
144
145 magic = 0x02180000;
146 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
147 nv_wo32(grch->mmio, i++ * 4, magic);
148 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
149 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
150 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
151 nv_wo32(grch->mmio, i++ * 4, reg);
152 nv_wo32(grch->mmio, i++ * 4, magic);
153 }
154 }
155
156 grch->mmio_nr = i / 2;
157 return 0;
158}
159
4b223eef
BS		 160int
161nvc0_graph_create_context(struct nouveau_channel *chan)
162{
966a5b7d
BS		 163 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
164 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
165 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
166 struct nvc0_graph_priv *priv = pgraph->priv;
167 struct nvc0_graph_chan *grch;
168 struct drm_device *dev = chan->dev;
169 struct nouveau_gpuobj *grctx;
170 int ret, i;
171
172 chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL);
173 if (!chan->pgraph_ctx)
174 return -ENOMEM;
175 grch = chan->pgraph_ctx;
176
177 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
178 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
179 &grch->grctx);
180 if (ret)
181 goto error;
182 chan->ramin_grctx = grch->grctx;
183 grctx = grch->grctx;
184
185 ret = nvc0_graph_create_context_mmio_list(chan);
186 if (ret)
187 goto error;
188
189 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
190 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
191 pinstmem->flush(dev);
192
193 if (!priv->grctx_vals) {
194 ret = nvc0_graph_construct_context(chan);
195 if (ret)
196 goto error;
197 }
198
199 for (i = 0; i < priv->grctx_size; i += 4)
200 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
201
202 nv_wo32(grctx, 0xf4, 0);
203 nv_wo32(grctx, 0xf8, 0);
204 nv_wo32(grctx, 0x10, grch->mmio_nr);
205 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
206 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
207 nv_wo32(grctx, 0x1c, 1);
208 nv_wo32(grctx, 0x20, 0);
209 nv_wo32(grctx, 0x28, 0);
210 nv_wo32(grctx, 0x2c, 0);
211 pinstmem->flush(dev);
4b223eef 212 return 0;
966a5b7d
BS		 213
214error:
215 pgraph->destroy_context(chan);
216 return ret;
4b223eef
BS		 217}
218
219void
220nvc0_graph_destroy_context(struct nouveau_channel *chan)
221{
966a5b7d
BS		 222 struct nvc0_graph_chan *grch;
223
224 grch = chan->pgraph_ctx;
225 chan->pgraph_ctx = NULL;
226 if (!grch)
227 return;
228
229 nouveau_gpuobj_ref(NULL, &grch->mmio);
230 nouveau_gpuobj_ref(NULL, &grch->unk418810);
231 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
232 nouveau_gpuobj_ref(NULL, &grch->unk408004);
233 nouveau_gpuobj_ref(NULL, &grch->grctx);
234 chan->ramin_grctx = NULL;
4b223eef
BS		 235}
236
237int
238nvc0_graph_load_context(struct nouveau_channel *chan)
239{
966a5b7d
BS		 240 struct drm_device *dev = chan->dev;
241
242 nv_wr32(dev, 0x409840, 0x00000030);
243 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
244 nv_wr32(dev, 0x409504, 0x00000003);
245 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
246 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
247
966a5b7d
BS		 248 return 0;
249}
250
251static int
252nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
253{
254 nv_wr32(dev, 0x409840, 0x00000003);
255 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
256 nv_wr32(dev, 0x409504, 0x00000009);
257 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
258 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
259 return -EBUSY;
260 }
261
4b223eef
BS		 262 return 0;
263}
264
265int
266nvc0_graph_unload_context(struct drm_device *dev)
267{
966a5b7d
BS		 268 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
269 return nvc0_graph_unload_context_to(dev, inst);
270}
271
272static void
273nvc0_graph_destroy(struct drm_device *dev)
274{
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
277 struct nvc0_graph_priv *priv;
278
279 priv = pgraph->priv;
280 if (!priv)
281 return;
282
283 nouveau_irq_unregister(dev, 12);
284
285 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
286 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
287
288 if (priv->grctx_vals)
289 kfree(priv->grctx_vals);
290 kfree(priv);
4b223eef
BS		 291}
292
293void
294nvc0_graph_takedown(struct drm_device *dev)
295{
966a5b7d
BS		 296 nvc0_graph_destroy(dev);
297}
298
299static int
300nvc0_graph_create(struct drm_device *dev)
301{
302 struct drm_nouveau_private *dev_priv = dev->dev_private;
303 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
304 struct nvc0_graph_priv *priv;
305 int ret, gpc, i;
306
307 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
308 if (!priv)
309 return -ENOMEM;
310 pgraph->priv = priv;
311
312 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
313 if (ret)
314 goto error;
315
316 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
317 if (ret)
318 goto error;
319
320 for (i = 0; i < 0x1000; i += 4) {
321 nv_wo32(priv->unk4188b4, i, 0x00000010);
322 nv_wo32(priv->unk4188b8, i, 0x00000010);
323 }
324
325 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
326 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
327 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
328 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
329 priv->tp_total += priv->tp_nr[gpc];
330 }
331
332 /*XXX: these need figuring out... */
333 switch (dev_priv->chipset) {
334 case 0xc0:
335 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
336 priv->magic_not_rop_nr = 0x07;
966a5b7d
BS		 337 /* filled values up to tp_total, the rest 0 */
338 priv->magicgpc980[0] = 0x22111000;
339 priv->magicgpc980[1] = 0x00000233;
340 priv->magicgpc980[2] = 0x00000000;
341 priv->magicgpc980[3] = 0x00000000;
342 priv->magicgpc918 = 0x000ba2e9;
343 } else
344 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
345 priv->magic_not_rop_nr = 0x05;
966a5b7d
BS		 346 priv->magicgpc980[0] = 0x11110000;
347 priv->magicgpc980[1] = 0x00233222;
348 priv->magicgpc980[2] = 0x00000000;
349 priv->magicgpc980[3] = 0x00000000;
350 priv->magicgpc918 = 0x00092493;
351 } else
352 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
353 priv->magic_not_rop_nr = 0x06;
966a5b7d
BS		 354 priv->magicgpc980[0] = 0x11110000;
355 priv->magicgpc980[1] = 0x03332222;
356 priv->magicgpc980[2] = 0x00000000;
357 priv->magicgpc980[3] = 0x00000000;
358 priv->magicgpc918 = 0x00088889;
359 }
360 break;
361 case 0xc3: /* 450, 4/0/0/0, 2 */
362 priv->magic_not_rop_nr = 0x03;
966a5b7d
BS		 363 priv->magicgpc980[0] = 0x00003210;
364 priv->magicgpc980[1] = 0x00000000;
365 priv->magicgpc980[2] = 0x00000000;
366 priv->magicgpc980[3] = 0x00000000;
367 priv->magicgpc918 = 0x00200000;
368 break;
369 case 0xc4: /* 460, 3/4/0/0, 4 */
370 priv->magic_not_rop_nr = 0x01;
966a5b7d
BS		 371 priv->magicgpc980[0] = 0x02321100;
372 priv->magicgpc980[1] = 0x00000000;
373 priv->magicgpc980[2] = 0x00000000;
374 priv->magicgpc980[3] = 0x00000000;
375 priv->magicgpc918 = 0x00124925;
376 break;
377 }
378
b1cd916a 379 if (!priv->magic_not_rop_nr) {
966a5b7d
BS		 380 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
381 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
382 priv->tp_nr[3], priv->rop_nr);
383 /* use 0xc3's values... */
384 priv->magic_not_rop_nr = 0x03;
966a5b7d
BS		 385 priv->magicgpc980[0] = 0x00003210;
386 priv->magicgpc980[1] = 0x00000000;
387 priv->magicgpc980[2] = 0x00000000;
388 priv->magicgpc980[3] = 0x00000000;
389 priv->magicgpc918 = 0x00200000;
390 }
391
392 nouveau_irq_register(dev, 12, nvc0_graph_isr);
393 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
394 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
395 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
396 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
397 return 0;
398
399error:
400 nvc0_graph_destroy(dev);
401 return ret;
402}
403
404static void
405nvc0_graph_init_obj418880(struct drm_device *dev)
406{
407 struct drm_nouveau_private *dev_priv = dev->dev_private;
408 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
409 struct nvc0_graph_priv *priv = pgraph->priv;
410 int i;
411
412 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
413 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
414 for (i = 0; i < 4; i++)
415 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
416 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
417 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
418}
419
420static void
421nvc0_graph_init_regs(struct drm_device *dev)
422{
423 nv_wr32(dev, 0x400080, 0x003083c2);
424 nv_wr32(dev, 0x400088, 0x00006fe7);
425 nv_wr32(dev, 0x40008c, 0x00000000);
426 nv_wr32(dev, 0x400090, 0x00000030);
427 nv_wr32(dev, 0x40013c, 0x013901f7);
428 nv_wr32(dev, 0x400140, 0x00000100);
429 nv_wr32(dev, 0x400144, 0x00000000);
430 nv_wr32(dev, 0x400148, 0x00000110);
431 nv_wr32(dev, 0x400138, 0x00000000);
432 nv_wr32(dev, 0x400130, 0x00000000);
433 nv_wr32(dev, 0x400134, 0x00000000);
434 nv_wr32(dev, 0x400124, 0x00000002);
435}
436
437static void
438nvc0_graph_init_gpc_0(struct drm_device *dev)
439{
440 struct drm_nouveau_private *dev_priv = dev->dev_private;
441 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
442 int gpc;
443
444 // TP ROP UNKVAL(magic_not_rop_nr)
445 // 450: 4/0/0/0 2 3
446 // 460: 3/4/0/0 4 1
447 // 465: 3/4/4/0 4 7
448 // 470: 3/3/4/4 5 5
449 // 480: 3/4/4/4 6 6
450
451 // magicgpc918
452 // 450: 00200000 00000000001000000000000000000000
453 // 460: 00124925 00000000000100100100100100100101
454 // 465: 000ba2e9 00000000000010111010001011101001
455 // 470: 00092493 00000000000010010010010010010011
456 // 480: 00088889 00000000000010001000100010001001
457
458 /* filled values up to tp_total, remainder 0 */
459 // 450: 00003210 00000000 00000000 00000000
460 // 460: 02321100 00000000 00000000 00000000
461 // 465: 22111000 00000233 00000000 00000000
462 // 470: 11110000 00233222 00000000 00000000
463 // 480: 11110000 03332222 00000000 00000000
464
465 nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
466 nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
467 nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
468 nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
469
470 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
471 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
472 priv->tp_nr[gpc]);
473 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
474 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
475 }
476
477 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
478 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
479}
480
481static void
482nvc0_graph_init_units(struct drm_device *dev)
483{
484 nv_wr32(dev, 0x409c24, 0x000f0000);
485 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
486 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
487 nv_wr32(dev, 0x408030, 0xc0000000);
488 nv_wr32(dev, 0x40601c, 0xc0000000);
489 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
490 nv_wr32(dev, 0x406018, 0xc0000000);
491 nv_wr32(dev, 0x405840, 0xc0000000);
492 nv_wr32(dev, 0x405844, 0x00ffffff);
493 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
494 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
495}
496
497static void
498nvc0_graph_init_gpc_1(struct drm_device *dev)
499{
500 struct drm_nouveau_private *dev_priv = dev->dev_private;
501 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
502 int gpc, tp;
503
504 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
505 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
506 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
507 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
508 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
509 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
510 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
511 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
512 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
513 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
514 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
515 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe44), 0x001ffffe);
516 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe4c), 0x0000000f);
517 }
518 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
519 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
520 }
521}
522
523static void
524nvc0_graph_init_rop(struct drm_device *dev)
525{
526 struct drm_nouveau_private *dev_priv = dev->dev_private;
527 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
528 int rop;
529
530 for (rop = 0; rop < priv->rop_nr; rop++) {
531 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
532 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
533 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
534 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
535 }
536}
537
538static int
539nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
540 const char *code_fw, const char *data_fw)
541{
542 const struct firmware *fw;
543 char name[32];
544 int ret, i;
545
546 snprintf(name, sizeof(name), "nouveau/%s", data_fw);
547 ret = request_firmware(&fw, name, &dev->pdev->dev);
548 if (ret) {
549 NV_ERROR(dev, "failed to load %s\n", data_fw);
550 return ret;
551 }
552
553 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
554 for (i = 0; i < fw->size / 4; i++)
555 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
556 release_firmware(fw);
557
558 snprintf(name, sizeof(name), "nouveau/%s", code_fw);
559 ret = request_firmware(&fw, name, &dev->pdev->dev);
560 if (ret) {
561 NV_ERROR(dev, "failed to load %s\n", code_fw);
562 return ret;
563 }
564
565 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
566 for (i = 0; i < fw->size / 4; i++) {
567 if ((i & 0x3f) == 0)
568 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
569 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
570 }
571 release_firmware(fw);
572
573 return 0;
574}
575
576static int
577nvc0_graph_init_ctxctl(struct drm_device *dev)
578{
579 struct drm_nouveau_private *dev_priv = dev->dev_private;
580 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
581 u32 r000260;
582 int ret;
583
584 /* load fuc microcode */
585 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
586 ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
587 if (ret == 0)
eeb9cc01 588 ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
966a5b7d
BS		 589 nv_wr32(dev, 0x000260, r000260);
590
591 if (ret)
592 return ret;
593
594 /* start both of them running */
595 nv_wr32(dev, 0x409840, 0xffffffff);
596 nv_wr32(dev, 0x41a10c, 0x00000000);
597 nv_wr32(dev, 0x40910c, 0x00000000);
598 nv_wr32(dev, 0x41a100, 0x00000002);
599 nv_wr32(dev, 0x409100, 0x00000002);
600 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
601 NV_INFO(dev, "0x409800 wait failed\n");
602
603 nv_wr32(dev, 0x409840, 0xffffffff);
604 nv_wr32(dev, 0x409500, 0x7fffffff);
605 nv_wr32(dev, 0x409504, 0x00000021);
606
607 nv_wr32(dev, 0x409840, 0xffffffff);
608 nv_wr32(dev, 0x409500, 0x00000000);
609 nv_wr32(dev, 0x409504, 0x00000010);
610 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
611 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
612 return -EBUSY;
613 }
614 priv->grctx_size = nv_rd32(dev, 0x409800);
615
616 nv_wr32(dev, 0x409840, 0xffffffff);
617 nv_wr32(dev, 0x409500, 0x00000000);
618 nv_wr32(dev, 0x409504, 0x00000016);
619 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
620 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
621 return -EBUSY;
622 }
623
624 nv_wr32(dev, 0x409840, 0xffffffff);
625 nv_wr32(dev, 0x409500, 0x00000000);
626 nv_wr32(dev, 0x409504, 0x00000025);
627 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
628 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
629 return -EBUSY;
630 }
631
632 return 0;
4b223eef
BS		 633}
634
635int
636nvc0_graph_init(struct drm_device *dev)
637{
638 struct drm_nouveau_private *dev_priv = dev->dev_private;
966a5b7d
BS		 639 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
640 struct nvc0_graph_priv *priv;
641 int ret;
642
4b223eef 643 dev_priv->engine.graph.accel_blocked = true;
966a5b7d
BS		 644
645 switch (dev_priv->chipset) {
646 case 0xc0:
647 case 0xc3:
648 case 0xc4:
649 break;
650 default:
651 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
652 if (nouveau_noaccel != 0)
653 return 0;
654 break;
655 }
656
657 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
658 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
659
660 if (!pgraph->priv) {
661 ret = nvc0_graph_create(dev);
662 if (ret)
663 return ret;
664 }
665 priv = pgraph->priv;
666
667 nvc0_graph_init_obj418880(dev);
668 nvc0_graph_init_regs(dev);
669 //nvc0_graph_init_unitplemented_magics(dev);
670 nvc0_graph_init_gpc_0(dev);
671 //nvc0_graph_init_unitplemented_c242(dev);
672
673 nv_wr32(dev, 0x400500, 0x00010001);
674 nv_wr32(dev, 0x400100, 0xffffffff);
675 nv_wr32(dev, 0x40013c, 0xffffffff);
676
677 nvc0_graph_init_units(dev);
678 nvc0_graph_init_gpc_1(dev);
679 nvc0_graph_init_rop(dev);
680
681 nv_wr32(dev, 0x400108, 0xffffffff);
682 nv_wr32(dev, 0x400138, 0xffffffff);
683 nv_wr32(dev, 0x400118, 0xffffffff);
684 nv_wr32(dev, 0x400130, 0xffffffff);
685 nv_wr32(dev, 0x40011c, 0xffffffff);
686 nv_wr32(dev, 0x400134, 0xffffffff);
687 nv_wr32(dev, 0x400054, 0x34ce3464);
688
689 ret = nvc0_graph_init_ctxctl(dev);
eeb9cc01
BS		 690 if (ret == 0)
691 dev_priv->engine.graph.accel_blocked = false;
4b223eef
BS		 692 return 0;
693}
694
966a5b7d
BS		 695static int
696nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
697{
698 struct drm_nouveau_private *dev_priv = dev->dev_private;
699 struct nouveau_channel *chan;
700 unsigned long flags;
701 int i;
702
703 spin_lock_irqsave(&dev_priv->channels.lock, flags);
704 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
705 chan = dev_priv->channels.ptr[i];
706 if (!chan || !chan->ramin)
707 continue;
708
709 if (inst == chan->ramin->vinst)
710 break;
711 }
712 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
713 return i;
714}
715
716static void
717nvc0_graph_isr(struct drm_device *dev)
718{
719 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
720 u32 chid = nvc0_graph_isr_chid(dev, inst);
721 u32 stat = nv_rd32(dev, 0x400100);
722 u32 addr = nv_rd32(dev, 0x400704);
723 u32 mthd = (addr & 0x00003ffc);
724 u32 subc = (addr & 0x00070000) >> 16;
725 u32 data = nv_rd32(dev, 0x400708);
726 u32 code = nv_rd32(dev, 0x400110);
727 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
728
729 if (stat & 0x00000010) {
730 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d "
731 "class 0x%04x mthd 0x%04x data 0x%08x\n",
732 chid, inst, subc, class, mthd, data);
733 nv_wr32(dev, 0x400100, 0x00000010);
734 stat &= ~0x00000010;
735 }
736
eae5e7f3
BS		 737 if (stat & 0x00000020) {
738 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
739 "class 0x%04x mthd 0x%04x data 0x%08x\n",
740 chid, inst, subc, class, mthd, data);
741 nv_wr32(dev, 0x400100, 0x00000020);
742 stat &= ~0x00000020;
743 }
744
966a5b7d
BS		 745 if (stat & 0x00100000) {
746 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
6effe393 747 nouveau_enum_print(nv50_data_error_names, code);
966a5b7d
BS		 748 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
749 "mthd 0x%04x data 0x%08x\n",
750 chid, inst, subc, class, mthd, data);
751 nv_wr32(dev, 0x400100, 0x00100000);
752 stat &= ~0x00100000;
753 }
754
eae5e7f3
BS		 755 if (stat & 0x00200000) {
756 u32 trap = nv_rd32(dev, 0x400108);
757 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
758 nv_wr32(dev, 0x400108, trap);
759 nv_wr32(dev, 0x400100, 0x00200000);
760 stat &= ~0x00200000;
761 }
762
966a5b7d
BS		 763 if (stat & 0x00080000) {
764 u32 ustat = nv_rd32(dev, 0x409c18);
765
766 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
767
768 nv_wr32(dev, 0x409c20, ustat);
769 nv_wr32(dev, 0x400100, 0x00080000);
770 stat &= ~0x00080000;
771 }
772
773 if (stat) {
774 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
775 nv_wr32(dev, 0x400100, stat);
776 }
777
778 nv_wr32(dev, 0x400500, 0x00010001);
779}
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