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26f6d88b BS |
1 | /* |
2 | * Copyright 2011 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
26f6d88b | 27 | #include "drmP.h" |
83fc083c | 28 | #include "drm_crtc_helper.h" |
26f6d88b BS |
29 | |
30 | #include "nouveau_drv.h" | |
31 | #include "nouveau_connector.h" | |
32 | #include "nouveau_encoder.h" | |
33 | #include "nouveau_crtc.h" | |
37b034a6 | 34 | #include "nouveau_dma.h" |
438d99e3 | 35 | #include "nouveau_fb.h" |
3a89cd02 | 36 | #include "nv50_display.h" |
26f6d88b | 37 | |
8a46438a BS |
38 | #define EVO_DMA_NR 9 |
39 | ||
bdb8c212 | 40 | #define EVO_MASTER (0x00) |
a63a97eb | 41 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
42 | #define EVO_OVLY(c) (0x05 + (c)) |
43 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
44 | #define EVO_CURS(c) (0x0d + (c)) |
45 | ||
816af2f2 BS |
46 | /* offsets in shared sync bo of various structures */ |
47 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
48 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) | |
49 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00) | |
50 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10) | |
51 | ||
3376ee37 BS |
52 | struct evo { |
53 | int idx; | |
54 | dma_addr_t handle; | |
55 | u32 *ptr; | |
56 | struct { | |
3376ee37 BS |
57 | u32 offset; |
58 | u16 value; | |
59 | } sem; | |
60 | }; | |
61 | ||
26f6d88b BS |
62 | struct nvd0_display { |
63 | struct nouveau_gpuobj *mem; | |
816af2f2 | 64 | struct nouveau_bo *sync; |
8a46438a | 65 | struct evo evo[9]; |
f20ce962 BS |
66 | |
67 | struct tasklet_struct tasklet; | |
ee41779e | 68 | u32 modeset; |
26f6d88b BS |
69 | }; |
70 | ||
71 | static struct nvd0_display * | |
72 | nvd0_display(struct drm_device *dev) | |
73 | { | |
74 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
75 | return dev_priv->engine.display.priv; | |
76 | } | |
77 | ||
bdb8c212 BS |
78 | static struct drm_crtc * |
79 | nvd0_display_crtc_get(struct drm_encoder *encoder) | |
80 | { | |
81 | return nouveau_encoder(encoder)->crtc; | |
82 | } | |
83 | ||
84 | /****************************************************************************** | |
85 | * EVO channel helpers | |
86 | *****************************************************************************/ | |
37b034a6 | 87 | static inline int |
51beb428 BS |
88 | evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data) |
89 | { | |
90 | int ret = 0; | |
91 | nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001); | |
92 | nv_wr32(dev, 0x610704 + (id * 0x10), data); | |
93 | nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd); | |
94 | if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000)) | |
95 | ret = -EBUSY; | |
96 | nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000); | |
97 | return ret; | |
98 | } | |
99 | ||
100 | static u32 * | |
101 | evo_wait(struct drm_device *dev, int id, int nr) | |
102 | { | |
103 | struct nvd0_display *disp = nvd0_display(dev); | |
104 | u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4; | |
105 | ||
106 | if (put + nr >= (PAGE_SIZE / 4)) { | |
107 | disp->evo[id].ptr[put] = 0x20000000; | |
108 | ||
109 | nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000); | |
110 | if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) { | |
111 | NV_ERROR(dev, "evo %d dma stalled\n", id); | |
112 | return NULL; | |
113 | } | |
114 | ||
115 | put = 0; | |
116 | } | |
117 | ||
27517ddb BS |
118 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) |
119 | NV_INFO(dev, "Evo%d: %p START\n", id, disp->evo[id].ptr + put); | |
120 | ||
51beb428 BS |
121 | return disp->evo[id].ptr + put; |
122 | } | |
123 | ||
124 | static void | |
125 | evo_kick(u32 *push, struct drm_device *dev, int id) | |
126 | { | |
127 | struct nvd0_display *disp = nvd0_display(dev); | |
27517ddb BS |
128 | |
129 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) { | |
130 | u32 curp = nv_rd32(dev, 0x640000 + (id * 0x1000)) >> 2; | |
131 | u32 *cur = disp->evo[id].ptr + curp; | |
132 | ||
133 | while (cur < push) | |
134 | NV_INFO(dev, "Evo%d: 0x%08x\n", id, *cur++); | |
135 | NV_INFO(dev, "Evo%d: %p KICK!\n", id, push); | |
136 | } | |
137 | ||
51beb428 BS |
138 | nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2); |
139 | } | |
140 | ||
141 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) | |
142 | #define evo_data(p,d) *((p)++) = (d) | |
143 | ||
bdb8c212 BS |
144 | static int |
145 | evo_init_dma(struct drm_device *dev, int ch) | |
83fc083c | 146 | { |
bdb8c212 BS |
147 | struct nvd0_display *disp = nvd0_display(dev); |
148 | u32 flags; | |
149 | ||
150 | flags = 0x00000000; | |
151 | if (ch == EVO_MASTER) | |
152 | flags |= 0x01000000; | |
153 | ||
154 | nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3); | |
155 | nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000); | |
156 | nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001); | |
157 | nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010); | |
158 | nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000); | |
159 | nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags); | |
160 | if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) { | |
161 | NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch, | |
162 | nv_rd32(dev, 0x610490 + (ch * 0x0010))); | |
163 | return -EBUSY; | |
164 | } | |
165 | ||
166 | nv_mask(dev, 0x610090, (1 << ch), (1 << ch)); | |
167 | nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch)); | |
168 | return 0; | |
169 | } | |
170 | ||
171 | static void | |
172 | evo_fini_dma(struct drm_device *dev, int ch) | |
173 | { | |
174 | if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010)) | |
175 | return; | |
176 | ||
177 | nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000); | |
178 | nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000); | |
179 | nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000); | |
180 | nv_mask(dev, 0x610090, (1 << ch), 0x00000000); | |
181 | nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000); | |
182 | } | |
183 | ||
4acd4293 BS |
184 | static inline void |
185 | evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data) | |
186 | { | |
187 | nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data); | |
188 | } | |
189 | ||
bdb8c212 BS |
190 | static int |
191 | evo_init_pio(struct drm_device *dev, int ch) | |
192 | { | |
193 | nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001); | |
194 | if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) { | |
195 | NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch, | |
196 | nv_rd32(dev, 0x610490 + (ch * 0x0010))); | |
197 | return -EBUSY; | |
198 | } | |
199 | ||
200 | nv_mask(dev, 0x610090, (1 << ch), (1 << ch)); | |
201 | nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch)); | |
202 | return 0; | |
203 | } | |
204 | ||
205 | static void | |
206 | evo_fini_pio(struct drm_device *dev, int ch) | |
207 | { | |
208 | if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001)) | |
209 | return; | |
210 | ||
211 | nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010); | |
212 | nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000); | |
213 | nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000); | |
214 | nv_mask(dev, 0x610090, (1 << ch), 0x00000000); | |
215 | nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000); | |
83fc083c BS |
216 | } |
217 | ||
3376ee37 BS |
218 | static bool |
219 | evo_sync_wait(void *data) | |
220 | { | |
816af2f2 | 221 | return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000; |
3376ee37 BS |
222 | } |
223 | ||
224 | static int | |
225 | evo_sync(struct drm_device *dev, int ch) | |
226 | { | |
227 | struct nvd0_display *disp = nvd0_display(dev); | |
816af2f2 | 228 | u32 *push = evo_wait(dev, ch, 8); |
3376ee37 | 229 | if (push) { |
816af2f2 | 230 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 231 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 232 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
233 | evo_mthd(push, 0x0080, 2); |
234 | evo_data(push, 0x00000000); | |
235 | evo_data(push, 0x00000000); | |
236 | evo_kick(push, dev, ch); | |
816af2f2 | 237 | if (nv_wait_cb(dev, evo_sync_wait, disp->sync)) |
3376ee37 BS |
238 | return 0; |
239 | } | |
240 | ||
241 | return -EBUSY; | |
242 | } | |
243 | ||
244 | /****************************************************************************** | |
a63a97eb | 245 | * Page flipping channel |
3376ee37 BS |
246 | *****************************************************************************/ |
247 | struct nouveau_bo * | |
248 | nvd0_display_crtc_sema(struct drm_device *dev, int crtc) | |
249 | { | |
816af2f2 | 250 | return nvd0_display(dev)->sync; |
3376ee37 BS |
251 | } |
252 | ||
253 | void | |
254 | nvd0_display_flip_stop(struct drm_crtc *crtc) | |
255 | { | |
256 | struct nvd0_display *disp = nvd0_display(crtc->dev); | |
257 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
a63a97eb | 258 | struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)]; |
3376ee37 BS |
259 | u32 *push; |
260 | ||
261 | push = evo_wait(crtc->dev, evo->idx, 8); | |
262 | if (push) { | |
263 | evo_mthd(push, 0x0084, 1); | |
264 | evo_data(push, 0x00000000); | |
265 | evo_mthd(push, 0x0094, 1); | |
266 | evo_data(push, 0x00000000); | |
267 | evo_mthd(push, 0x00c0, 1); | |
268 | evo_data(push, 0x00000000); | |
269 | evo_mthd(push, 0x0080, 1); | |
270 | evo_data(push, 0x00000000); | |
271 | evo_kick(push, crtc->dev, evo->idx); | |
272 | } | |
273 | } | |
274 | ||
275 | int | |
276 | nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
277 | struct nouveau_channel *chan, u32 swap_interval) | |
278 | { | |
279 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
280 | struct nvd0_display *disp = nvd0_display(crtc->dev); | |
281 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
a63a97eb | 282 | struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)]; |
3376ee37 BS |
283 | u64 offset; |
284 | u32 *push; | |
285 | int ret; | |
286 | ||
4cbb0f8d BS |
287 | evo_sync(crtc->dev, EVO_MASTER); |
288 | ||
3376ee37 BS |
289 | swap_interval <<= 4; |
290 | if (swap_interval == 0) | |
291 | swap_interval |= 0x100; | |
292 | ||
293 | push = evo_wait(crtc->dev, evo->idx, 128); | |
294 | if (unlikely(push == NULL)) | |
295 | return -EBUSY; | |
296 | ||
297 | /* synchronise with the rendering channel, if necessary */ | |
298 | if (likely(chan)) { | |
299 | ret = RING_SPACE(chan, 10); | |
300 | if (ret) | |
301 | return ret; | |
302 | ||
303 | offset = chan->dispc_vma[nv_crtc->index].offset; | |
304 | offset += evo->sem.offset; | |
305 | ||
b5b2e598 | 306 | BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
3376ee37 BS |
307 | OUT_RING (chan, upper_32_bits(offset)); |
308 | OUT_RING (chan, lower_32_bits(offset)); | |
309 | OUT_RING (chan, 0xf00d0000 | evo->sem.value); | |
310 | OUT_RING (chan, 0x1002); | |
b5b2e598 | 311 | BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); |
3376ee37 BS |
312 | OUT_RING (chan, upper_32_bits(offset)); |
313 | OUT_RING (chan, lower_32_bits(offset ^ 0x10)); | |
314 | OUT_RING (chan, 0x74b1e000); | |
315 | OUT_RING (chan, 0x1001); | |
316 | FIRE_RING (chan); | |
317 | } else { | |
816af2f2 | 318 | nouveau_bo_wr32(disp->sync, evo->sem.offset / 4, |
3376ee37 BS |
319 | 0xf00d0000 | evo->sem.value); |
320 | evo_sync(crtc->dev, EVO_MASTER); | |
321 | } | |
322 | ||
323 | /* queue the flip */ | |
324 | evo_mthd(push, 0x0100, 1); | |
325 | evo_data(push, 0xfffe0000); | |
326 | evo_mthd(push, 0x0084, 1); | |
327 | evo_data(push, swap_interval); | |
328 | if (!(swap_interval & 0x00000100)) { | |
329 | evo_mthd(push, 0x00e0, 1); | |
330 | evo_data(push, 0x40000000); | |
331 | } | |
332 | evo_mthd(push, 0x0088, 4); | |
333 | evo_data(push, evo->sem.offset); | |
334 | evo_data(push, 0xf00d0000 | evo->sem.value); | |
335 | evo_data(push, 0x74b1e000); | |
336 | evo_data(push, NvEvoSync); | |
337 | evo_mthd(push, 0x00a0, 2); | |
338 | evo_data(push, 0x00000000); | |
339 | evo_data(push, 0x00000000); | |
340 | evo_mthd(push, 0x00c0, 1); | |
341 | evo_data(push, nv_fb->r_dma); | |
342 | evo_mthd(push, 0x0110, 2); | |
343 | evo_data(push, 0x00000000); | |
344 | evo_data(push, 0x00000000); | |
345 | evo_mthd(push, 0x0400, 5); | |
346 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
347 | evo_data(push, 0); | |
348 | evo_data(push, (fb->height << 16) | fb->width); | |
349 | evo_data(push, nv_fb->r_pitch); | |
350 | evo_data(push, nv_fb->r_format); | |
351 | evo_mthd(push, 0x0080, 1); | |
352 | evo_data(push, 0x00000000); | |
353 | evo_kick(push, crtc->dev, evo->idx); | |
354 | ||
355 | evo->sem.offset ^= 0x10; | |
356 | evo->sem.value++; | |
357 | return 0; | |
358 | } | |
359 | ||
438d99e3 BS |
360 | /****************************************************************************** |
361 | * CRTC | |
362 | *****************************************************************************/ | |
363 | static int | |
488ff207 | 364 | nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 BS |
365 | { |
366 | struct drm_device *dev = nv_crtc->base.dev; | |
de691855 BS |
367 | struct nouveau_connector *nv_connector; |
368 | struct drm_connector *connector; | |
369 | u32 *push, mode = 0x00; | |
438d99e3 | 370 | |
488ff207 | 371 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
372 | connector = &nv_connector->base; |
373 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
374 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | |
375 | mode = DITHERING_MODE_DYNAMIC2X2; | |
376 | } else { | |
377 | mode = nv_connector->dithering_mode; | |
378 | } | |
379 | ||
380 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
381 | if (connector->display_info.bpc >= 8) | |
382 | mode |= DITHERING_DEPTH_8BPC; | |
383 | } else { | |
384 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
385 | } |
386 | ||
2eac77b7 | 387 | push = evo_wait(dev, EVO_MASTER, 4); |
438d99e3 BS |
388 | if (push) { |
389 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x300), 1); | |
390 | evo_data(push, mode); | |
391 | if (update) { | |
392 | evo_mthd(push, 0x0080, 1); | |
393 | evo_data(push, 0x00000000); | |
394 | } | |
2eac77b7 | 395 | evo_kick(push, dev, EVO_MASTER); |
438d99e3 BS |
396 | } |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int | |
488ff207 | 402 | nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 403 | { |
92854622 | 404 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
438d99e3 | 405 | struct drm_device *dev = nv_crtc->base.dev; |
3376ee37 | 406 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 407 | struct nouveau_connector *nv_connector; |
92854622 BS |
408 | int mode = DRM_MODE_SCALE_NONE; |
409 | u32 oX, oY, *push; | |
f3fdc52d | 410 | |
92854622 BS |
411 | /* start off at the resolution we programmed the crtc for, this |
412 | * effectively handles NONE/FULL scaling | |
413 | */ | |
f3fdc52d | 414 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
92854622 BS |
415 | if (nv_connector && nv_connector->native_mode) |
416 | mode = nv_connector->scaling_mode; | |
417 | ||
418 | if (mode != DRM_MODE_SCALE_NONE) | |
419 | omode = nv_connector->native_mode; | |
420 | else | |
421 | omode = umode; | |
422 | ||
423 | oX = omode->hdisplay; | |
424 | oY = omode->vdisplay; | |
425 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
426 | oY *= 2; | |
427 | ||
428 | /* add overscan compensation if necessary, will keep the aspect | |
429 | * ratio the same as the backend mode unless overridden by the | |
430 | * user setting both hborder and vborder properties. | |
431 | */ | |
432 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
433 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
434 | nv_connector->edid && | |
435 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
436 | u32 bX = nv_connector->underscan_hborder; | |
437 | u32 bY = nv_connector->underscan_vborder; | |
438 | u32 aspect = (oY << 19) / oX; | |
439 | ||
440 | if (bX) { | |
441 | oX -= (bX * 2); | |
442 | if (bY) oY -= (bY * 2); | |
443 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
444 | } else { | |
445 | oX -= (oX >> 4) + 32; | |
446 | if (bY) oY -= (bY * 2); | |
447 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
448 | } | |
449 | } | |
450 | ||
451 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
452 | * removed already for overscan compensation | |
453 | */ | |
454 | switch (mode) { | |
455 | case DRM_MODE_SCALE_CENTER: | |
456 | oX = min((u32)umode->hdisplay, oX); | |
457 | oY = min((u32)umode->vdisplay, oY); | |
458 | /* fall-through */ | |
459 | case DRM_MODE_SCALE_ASPECT: | |
460 | if (oY < oX) { | |
461 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
462 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
463 | } else { | |
464 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
465 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 466 | } |
92854622 BS |
467 | break; |
468 | default: | |
469 | break; | |
f3fdc52d | 470 | } |
438d99e3 | 471 | |
3376ee37 | 472 | push = evo_wait(dev, EVO_MASTER, 8); |
438d99e3 BS |
473 | if (push) { |
474 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
92854622 BS |
475 | evo_data(push, (oY << 16) | oX); |
476 | evo_data(push, (oY << 16) | oX); | |
477 | evo_data(push, (oY << 16) | oX); | |
438d99e3 BS |
478 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); |
479 | evo_data(push, 0x00000000); | |
438d99e3 | 480 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); |
92854622 | 481 | evo_data(push, (umode->vdisplay << 16) | umode->hdisplay); |
3376ee37 | 482 | evo_kick(push, dev, EVO_MASTER); |
438d99e3 | 483 | if (update) { |
3376ee37 BS |
484 | nvd0_display_flip_stop(crtc); |
485 | nvd0_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 | 486 | } |
438d99e3 BS |
487 | } |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static int | |
493 | nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, | |
494 | int x, int y, bool update) | |
495 | { | |
496 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
497 | u32 *push; | |
498 | ||
2eac77b7 | 499 | push = evo_wait(fb->dev, EVO_MASTER, 16); |
438d99e3 BS |
500 | if (push) { |
501 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
502 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
503 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
504 | evo_data(push, (fb->height << 16) | fb->width); | |
505 | evo_data(push, nvfb->r_pitch); | |
506 | evo_data(push, nvfb->r_format); | |
c0cc92a1 | 507 | evo_data(push, nvfb->r_dma); |
c6f2f71d BS |
508 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); |
509 | evo_data(push, (y << 16) | x); | |
a46232ee BS |
510 | if (update) { |
511 | evo_mthd(push, 0x0080, 1); | |
512 | evo_data(push, 0x00000000); | |
513 | } | |
2eac77b7 | 514 | evo_kick(push, fb->dev, EVO_MASTER); |
438d99e3 BS |
515 | } |
516 | ||
c0cc92a1 | 517 | nv_crtc->fb.tile_flags = nvfb->r_dma; |
438d99e3 BS |
518 | return 0; |
519 | } | |
520 | ||
521 | static void | |
522 | nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update) | |
523 | { | |
524 | struct drm_device *dev = nv_crtc->base.dev; | |
2eac77b7 | 525 | u32 *push = evo_wait(dev, EVO_MASTER, 16); |
438d99e3 BS |
526 | if (push) { |
527 | if (show) { | |
528 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); | |
529 | evo_data(push, 0x85000000); | |
530 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
531 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
37b034a6 | 532 | evo_data(push, NvEvoVRAM); |
438d99e3 BS |
533 | } else { |
534 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
535 | evo_data(push, 0x05000000); | |
536 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
537 | evo_data(push, 0x00000000); | |
538 | } | |
539 | ||
540 | if (update) { | |
541 | evo_mthd(push, 0x0080, 1); | |
542 | evo_data(push, 0x00000000); | |
543 | } | |
544 | ||
2eac77b7 | 545 | evo_kick(push, dev, EVO_MASTER); |
438d99e3 BS |
546 | } |
547 | } | |
548 | ||
549 | static void | |
550 | nvd0_crtc_dpms(struct drm_crtc *crtc, int mode) | |
551 | { | |
552 | } | |
553 | ||
554 | static void | |
555 | nvd0_crtc_prepare(struct drm_crtc *crtc) | |
556 | { | |
557 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
558 | u32 *push; | |
559 | ||
3376ee37 BS |
560 | nvd0_display_flip_stop(crtc); |
561 | ||
2eac77b7 | 562 | push = evo_wait(crtc->dev, EVO_MASTER, 2); |
438d99e3 BS |
563 | if (push) { |
564 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
565 | evo_data(push, 0x00000000); | |
566 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
567 | evo_data(push, 0x03000000); | |
568 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
569 | evo_data(push, 0x00000000); | |
2eac77b7 | 570 | evo_kick(push, crtc->dev, EVO_MASTER); |
438d99e3 BS |
571 | } |
572 | ||
573 | nvd0_crtc_cursor_show(nv_crtc, false, false); | |
574 | } | |
575 | ||
576 | static void | |
577 | nvd0_crtc_commit(struct drm_crtc *crtc) | |
578 | { | |
579 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
580 | u32 *push; | |
581 | ||
2eac77b7 | 582 | push = evo_wait(crtc->dev, EVO_MASTER, 32); |
438d99e3 BS |
583 | if (push) { |
584 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
585 | evo_data(push, nv_crtc->fb.tile_flags); | |
586 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); | |
587 | evo_data(push, 0x83000000); | |
588 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
589 | evo_data(push, 0x00000000); | |
590 | evo_data(push, 0x00000000); | |
591 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
37b034a6 | 592 | evo_data(push, NvEvoVRAM); |
8ea0d4aa BS |
593 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); |
594 | evo_data(push, 0xffffff00); | |
2eac77b7 | 595 | evo_kick(push, crtc->dev, EVO_MASTER); |
438d99e3 BS |
596 | } |
597 | ||
4cbb0f8d | 598 | nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true); |
3376ee37 | 599 | nvd0_display_flip_next(crtc, crtc->fb, NULL, 1); |
438d99e3 BS |
600 | } |
601 | ||
602 | static bool | |
603 | nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
604 | struct drm_display_mode *adjusted_mode) | |
605 | { | |
606 | return true; | |
607 | } | |
608 | ||
609 | static int | |
610 | nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) | |
611 | { | |
612 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); | |
613 | int ret; | |
614 | ||
615 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); | |
616 | if (ret) | |
617 | return ret; | |
618 | ||
619 | if (old_fb) { | |
620 | nvfb = nouveau_framebuffer(old_fb); | |
621 | nouveau_bo_unpin(nvfb->nvbo); | |
622 | } | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static int | |
628 | nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, | |
629 | struct drm_display_mode *mode, int x, int y, | |
630 | struct drm_framebuffer *old_fb) | |
631 | { | |
632 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
633 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
634 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
635 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
636 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
637 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
638 | u32 vblan2e = 0, vblan2s = 1; | |
3488c57b | 639 | u32 *push; |
438d99e3 BS |
640 | int ret; |
641 | ||
2d1d898b BS |
642 | hactive = mode->htotal; |
643 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
644 | hbackp = mode->htotal - mode->hsync_end; | |
645 | hblanke = hsynce + hbackp; | |
646 | hfrontp = mode->hsync_start - mode->hdisplay; | |
647 | hblanks = mode->htotal - hfrontp - 1; | |
648 | ||
649 | vactive = mode->vtotal * vscan / ilace; | |
650 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
651 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
652 | vblanke = vsynce + vbackp; | |
653 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
654 | vblanks = vactive - vfrontp - 1; | |
655 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
656 | vblan2e = vactive + vsynce + vbackp; | |
657 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
658 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
659 | } |
660 | ||
438d99e3 BS |
661 | ret = nvd0_crtc_swap_fbs(crtc, old_fb); |
662 | if (ret) | |
663 | return ret; | |
664 | ||
2eac77b7 | 665 | push = evo_wait(crtc->dev, EVO_MASTER, 64); |
438d99e3 | 666 | if (push) { |
2d1d898b | 667 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); |
629c1b92 | 668 | evo_data(push, 0x00000000); |
2d1d898b BS |
669 | evo_data(push, (vactive << 16) | hactive); |
670 | evo_data(push, ( vsynce << 16) | hsynce); | |
671 | evo_data(push, (vblanke << 16) | hblanke); | |
672 | evo_data(push, (vblanks << 16) | hblanks); | |
673 | evo_data(push, (vblan2e << 16) | vblan2s); | |
438d99e3 BS |
674 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); |
675 | evo_data(push, 0x00000000); /* ??? */ | |
676 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
677 | evo_data(push, mode->clock * 1000); | |
678 | evo_data(push, 0x00200000); /* ??? */ | |
679 | evo_data(push, mode->clock * 1000); | |
3376ee37 BS |
680 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); |
681 | evo_data(push, 0x00000311); | |
682 | evo_data(push, 0x00000100); | |
2eac77b7 | 683 | evo_kick(push, crtc->dev, EVO_MASTER); |
438d99e3 BS |
684 | } |
685 | ||
686 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
488ff207 BS |
687 | nvd0_crtc_set_dither(nv_crtc, false); |
688 | nvd0_crtc_set_scale(nv_crtc, false); | |
438d99e3 BS |
689 | nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false); |
690 | return 0; | |
691 | } | |
692 | ||
693 | static int | |
694 | nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
695 | struct drm_framebuffer *old_fb) | |
696 | { | |
697 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
698 | int ret; | |
699 | ||
84e2ad8b BS |
700 | if (!crtc->fb) { |
701 | NV_DEBUG_KMS(crtc->dev, "No FB bound\n"); | |
702 | return 0; | |
703 | } | |
704 | ||
438d99e3 BS |
705 | ret = nvd0_crtc_swap_fbs(crtc, old_fb); |
706 | if (ret) | |
707 | return ret; | |
708 | ||
3376ee37 | 709 | nvd0_display_flip_stop(crtc); |
438d99e3 | 710 | nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true); |
3376ee37 | 711 | nvd0_display_flip_next(crtc, crtc->fb, NULL, 1); |
438d99e3 BS |
712 | return 0; |
713 | } | |
714 | ||
715 | static int | |
716 | nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc, | |
717 | struct drm_framebuffer *fb, int x, int y, | |
718 | enum mode_set_atomic state) | |
719 | { | |
720 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
3376ee37 | 721 | nvd0_display_flip_stop(crtc); |
438d99e3 BS |
722 | nvd0_crtc_set_image(nv_crtc, fb, x, y, true); |
723 | return 0; | |
724 | } | |
725 | ||
726 | static void | |
727 | nvd0_crtc_lut_load(struct drm_crtc *crtc) | |
728 | { | |
729 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
730 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
731 | int i; | |
732 | ||
733 | for (i = 0; i < 256; i++) { | |
8ea0d4aa BS |
734 | writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0); |
735 | writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2); | |
736 | writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4); | |
438d99e3 BS |
737 | } |
738 | } | |
739 | ||
740 | static int | |
741 | nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, | |
742 | uint32_t handle, uint32_t width, uint32_t height) | |
743 | { | |
744 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
745 | struct drm_device *dev = crtc->dev; | |
746 | struct drm_gem_object *gem; | |
747 | struct nouveau_bo *nvbo; | |
748 | bool visible = (handle != 0); | |
749 | int i, ret = 0; | |
750 | ||
751 | if (visible) { | |
752 | if (width != 64 || height != 64) | |
753 | return -EINVAL; | |
754 | ||
755 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
756 | if (unlikely(!gem)) | |
757 | return -ENOENT; | |
758 | nvbo = nouveau_gem_object(gem); | |
759 | ||
760 | ret = nouveau_bo_map(nvbo); | |
761 | if (ret == 0) { | |
762 | for (i = 0; i < 64 * 64; i++) { | |
763 | u32 v = nouveau_bo_rd32(nvbo, i); | |
764 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); | |
765 | } | |
766 | nouveau_bo_unmap(nvbo); | |
767 | } | |
768 | ||
769 | drm_gem_object_unreference_unlocked(gem); | |
770 | } | |
771 | ||
772 | if (visible != nv_crtc->cursor.visible) { | |
773 | nvd0_crtc_cursor_show(nv_crtc, visible, true); | |
774 | nv_crtc->cursor.visible = visible; | |
775 | } | |
776 | ||
777 | return ret; | |
778 | } | |
779 | ||
780 | static int | |
781 | nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
782 | { | |
783 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
4acd4293 | 784 | int ch = EVO_CURS(nv_crtc->index); |
438d99e3 | 785 | |
4acd4293 BS |
786 | evo_piow(crtc->dev, ch, 0x0084, (y << 16) | x); |
787 | evo_piow(crtc->dev, ch, 0x0080, 0x00000000); | |
438d99e3 BS |
788 | return 0; |
789 | } | |
790 | ||
791 | static void | |
792 | nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
793 | uint32_t start, uint32_t size) | |
794 | { | |
795 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
796 | u32 end = max(start + size, (u32)256); | |
797 | u32 i; | |
798 | ||
799 | for (i = start; i < end; i++) { | |
800 | nv_crtc->lut.r[i] = r[i]; | |
801 | nv_crtc->lut.g[i] = g[i]; | |
802 | nv_crtc->lut.b[i] = b[i]; | |
803 | } | |
804 | ||
805 | nvd0_crtc_lut_load(crtc); | |
806 | } | |
807 | ||
808 | static void | |
809 | nvd0_crtc_destroy(struct drm_crtc *crtc) | |
810 | { | |
811 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
812 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); | |
813 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
814 | nouveau_bo_unmap(nv_crtc->lut.nvbo); | |
815 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
816 | drm_crtc_cleanup(crtc); | |
817 | kfree(crtc); | |
818 | } | |
819 | ||
820 | static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = { | |
821 | .dpms = nvd0_crtc_dpms, | |
822 | .prepare = nvd0_crtc_prepare, | |
823 | .commit = nvd0_crtc_commit, | |
824 | .mode_fixup = nvd0_crtc_mode_fixup, | |
825 | .mode_set = nvd0_crtc_mode_set, | |
826 | .mode_set_base = nvd0_crtc_mode_set_base, | |
827 | .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic, | |
828 | .load_lut = nvd0_crtc_lut_load, | |
829 | }; | |
830 | ||
831 | static const struct drm_crtc_funcs nvd0_crtc_func = { | |
832 | .cursor_set = nvd0_crtc_cursor_set, | |
833 | .cursor_move = nvd0_crtc_cursor_move, | |
834 | .gamma_set = nvd0_crtc_gamma_set, | |
835 | .set_config = drm_crtc_helper_set_config, | |
836 | .destroy = nvd0_crtc_destroy, | |
3376ee37 | 837 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
838 | }; |
839 | ||
c20ab3e1 BS |
840 | static void |
841 | nvd0_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) | |
842 | { | |
843 | } | |
844 | ||
845 | static void | |
846 | nvd0_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) | |
847 | { | |
848 | } | |
849 | ||
438d99e3 BS |
850 | static int |
851 | nvd0_crtc_create(struct drm_device *dev, int index) | |
852 | { | |
853 | struct nouveau_crtc *nv_crtc; | |
854 | struct drm_crtc *crtc; | |
855 | int ret, i; | |
856 | ||
857 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); | |
858 | if (!nv_crtc) | |
859 | return -ENOMEM; | |
860 | ||
861 | nv_crtc->index = index; | |
862 | nv_crtc->set_dither = nvd0_crtc_set_dither; | |
863 | nv_crtc->set_scale = nvd0_crtc_set_scale; | |
c20ab3e1 BS |
864 | nv_crtc->cursor.set_offset = nvd0_cursor_set_offset; |
865 | nv_crtc->cursor.set_pos = nvd0_cursor_set_pos; | |
438d99e3 BS |
866 | for (i = 0; i < 256; i++) { |
867 | nv_crtc->lut.r[i] = i << 8; | |
868 | nv_crtc->lut.g[i] = i << 8; | |
869 | nv_crtc->lut.b[i] = i << 8; | |
870 | } | |
871 | ||
872 | crtc = &nv_crtc->base; | |
873 | drm_crtc_init(dev, crtc, &nvd0_crtc_func); | |
874 | drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc); | |
875 | drm_mode_crtc_set_gamma_size(crtc, 256); | |
876 | ||
877 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, | |
878 | 0, 0x0000, &nv_crtc->cursor.nvbo); | |
879 | if (!ret) { | |
880 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
881 | if (!ret) | |
882 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
883 | if (ret) | |
884 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
885 | } | |
886 | ||
887 | if (ret) | |
888 | goto out; | |
889 | ||
8ea0d4aa | 890 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
438d99e3 BS |
891 | 0, 0x0000, &nv_crtc->lut.nvbo); |
892 | if (!ret) { | |
893 | ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); | |
894 | if (!ret) | |
895 | ret = nouveau_bo_map(nv_crtc->lut.nvbo); | |
896 | if (ret) | |
897 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
898 | } | |
899 | ||
900 | if (ret) | |
901 | goto out; | |
902 | ||
903 | nvd0_crtc_lut_load(crtc); | |
904 | ||
905 | out: | |
906 | if (ret) | |
907 | nvd0_crtc_destroy(crtc); | |
908 | return ret; | |
909 | } | |
910 | ||
26f6d88b BS |
911 | /****************************************************************************** |
912 | * DAC | |
913 | *****************************************************************************/ | |
8eaa9669 BS |
914 | static void |
915 | nvd0_dac_dpms(struct drm_encoder *encoder, int mode) | |
916 | { | |
917 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
918 | struct drm_device *dev = encoder->dev; | |
919 | int or = nv_encoder->or; | |
920 | u32 dpms_ctrl; | |
921 | ||
922 | dpms_ctrl = 0x80000000; | |
923 | if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF) | |
924 | dpms_ctrl |= 0x00000001; | |
925 | if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) | |
926 | dpms_ctrl |= 0x00000004; | |
927 | ||
928 | nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000); | |
929 | nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl); | |
930 | nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000); | |
931 | } | |
932 | ||
933 | static bool | |
934 | nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
935 | struct drm_display_mode *adjusted_mode) | |
936 | { | |
937 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
938 | struct nouveau_connector *nv_connector; | |
939 | ||
940 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
941 | if (nv_connector && nv_connector->native_mode) { | |
942 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
943 | int id = adjusted_mode->base.id; | |
944 | *adjusted_mode = *nv_connector->native_mode; | |
945 | adjusted_mode->base.id = id; | |
946 | } | |
947 | } | |
948 | ||
949 | return true; | |
950 | } | |
951 | ||
8eaa9669 BS |
952 | static void |
953 | nvd0_dac_commit(struct drm_encoder *encoder) | |
954 | { | |
955 | } | |
956 | ||
957 | static void | |
958 | nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
959 | struct drm_display_mode *adjusted_mode) | |
960 | { | |
961 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
962 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3488c57b BS |
963 | u32 syncs, magic, *push; |
964 | ||
965 | syncs = 0x00000001; | |
966 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
967 | syncs |= 0x00000008; | |
968 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
969 | syncs |= 0x00000010; | |
970 | ||
971 | magic = 0x31ec6000 | (nv_crtc->index << 25); | |
972 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
973 | magic |= 0x00000001; | |
8eaa9669 BS |
974 | |
975 | nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON); | |
976 | ||
3488c57b | 977 | push = evo_wait(encoder->dev, EVO_MASTER, 8); |
8eaa9669 | 978 | if (push) { |
3488c57b BS |
979 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
980 | evo_data(push, syncs); | |
981 | evo_data(push, magic); | |
982 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2); | |
8eaa9669 | 983 | evo_data(push, 1 << nv_crtc->index); |
ff8ff503 | 984 | evo_data(push, 0x00ff); |
2eac77b7 | 985 | evo_kick(push, encoder->dev, EVO_MASTER); |
8eaa9669 BS |
986 | } |
987 | ||
988 | nv_encoder->crtc = encoder->crtc; | |
989 | } | |
990 | ||
991 | static void | |
992 | nvd0_dac_disconnect(struct drm_encoder *encoder) | |
993 | { | |
994 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
995 | struct drm_device *dev = encoder->dev; | |
996 | u32 *push; | |
997 | ||
998 | if (nv_encoder->crtc) { | |
999 | nvd0_crtc_prepare(nv_encoder->crtc); | |
1000 | ||
2eac77b7 | 1001 | push = evo_wait(dev, EVO_MASTER, 4); |
8eaa9669 BS |
1002 | if (push) { |
1003 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1); | |
1004 | evo_data(push, 0x00000000); | |
1005 | evo_mthd(push, 0x0080, 1); | |
1006 | evo_data(push, 0x00000000); | |
2eac77b7 | 1007 | evo_kick(push, dev, EVO_MASTER); |
8eaa9669 BS |
1008 | } |
1009 | ||
1010 | nv_encoder->crtc = NULL; | |
1011 | } | |
1012 | } | |
1013 | ||
b6d8e7ec BS |
1014 | static enum drm_connector_status |
1015 | nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
1016 | { | |
b681993f BS |
1017 | enum drm_connector_status status = connector_status_disconnected; |
1018 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1019 | struct drm_device *dev = encoder->dev; | |
1020 | int or = nv_encoder->or; | |
1021 | u32 load; | |
1022 | ||
1023 | nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000); | |
1024 | udelay(9500); | |
1025 | nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000); | |
1026 | ||
1027 | load = nv_rd32(dev, 0x61a00c + (or * 0x800)); | |
1028 | if ((load & 0x38000000) == 0x38000000) | |
1029 | status = connector_status_connected; | |
1030 | ||
1031 | nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000); | |
1032 | return status; | |
b6d8e7ec BS |
1033 | } |
1034 | ||
8eaa9669 BS |
1035 | static void |
1036 | nvd0_dac_destroy(struct drm_encoder *encoder) | |
1037 | { | |
1038 | drm_encoder_cleanup(encoder); | |
1039 | kfree(encoder); | |
1040 | } | |
1041 | ||
1042 | static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = { | |
1043 | .dpms = nvd0_dac_dpms, | |
1044 | .mode_fixup = nvd0_dac_mode_fixup, | |
4cbb0f8d | 1045 | .prepare = nvd0_dac_disconnect, |
8eaa9669 BS |
1046 | .commit = nvd0_dac_commit, |
1047 | .mode_set = nvd0_dac_mode_set, | |
1048 | .disable = nvd0_dac_disconnect, | |
1049 | .get_crtc = nvd0_display_crtc_get, | |
b6d8e7ec | 1050 | .detect = nvd0_dac_detect |
8eaa9669 BS |
1051 | }; |
1052 | ||
1053 | static const struct drm_encoder_funcs nvd0_dac_func = { | |
1054 | .destroy = nvd0_dac_destroy, | |
1055 | }; | |
1056 | ||
1057 | static int | |
1058 | nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe) | |
1059 | { | |
1060 | struct drm_device *dev = connector->dev; | |
1061 | struct nouveau_encoder *nv_encoder; | |
1062 | struct drm_encoder *encoder; | |
1063 | ||
1064 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1065 | if (!nv_encoder) | |
1066 | return -ENOMEM; | |
1067 | nv_encoder->dcb = dcbe; | |
1068 | nv_encoder->or = ffs(dcbe->or) - 1; | |
1069 | ||
1070 | encoder = to_drm_encoder(nv_encoder); | |
1071 | encoder->possible_crtcs = dcbe->heads; | |
1072 | encoder->possible_clones = 0; | |
1073 | drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC); | |
1074 | drm_encoder_helper_add(encoder, &nvd0_dac_hfunc); | |
1075 | ||
1076 | drm_mode_connector_attach_encoder(connector, encoder); | |
1077 | return 0; | |
1078 | } | |
26f6d88b | 1079 | |
78951d22 BS |
1080 | /****************************************************************************** |
1081 | * Audio | |
1082 | *****************************************************************************/ | |
1083 | static void | |
1084 | nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
1085 | { | |
1086 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1087 | struct nouveau_connector *nv_connector; | |
1088 | struct drm_device *dev = encoder->dev; | |
1089 | int i, or = nv_encoder->or * 0x30; | |
1090 | ||
1091 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1092 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1093 | return; | |
1094 | ||
1095 | nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001); | |
1096 | ||
1097 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); | |
1098 | if (nv_connector->base.eld[0]) { | |
1099 | u8 *eld = nv_connector->base.eld; | |
1100 | ||
1101 | for (i = 0; i < eld[2] * 4; i++) | |
1102 | nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]); | |
1103 | for (i = eld[2] * 4; i < 0x60; i++) | |
1104 | nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00); | |
1105 | ||
1106 | nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | static void | |
1111 | nvd0_audio_disconnect(struct drm_encoder *encoder) | |
1112 | { | |
1113 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1114 | struct drm_device *dev = encoder->dev; | |
1115 | int or = nv_encoder->or * 0x30; | |
1116 | ||
1117 | nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000); | |
1118 | } | |
1119 | ||
1120 | /****************************************************************************** | |
1121 | * HDMI | |
1122 | *****************************************************************************/ | |
1123 | static void | |
1124 | nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
1125 | { | |
64d9cc04 BS |
1126 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1127 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1128 | struct nouveau_connector *nv_connector; | |
1129 | struct drm_device *dev = encoder->dev; | |
1130 | int head = nv_crtc->index * 0x800; | |
1131 | u32 rekey = 56; /* binary driver, and tegra constant */ | |
1132 | u32 max_ac_packet; | |
1133 | ||
1134 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1135 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1136 | return; | |
1137 | ||
1138 | max_ac_packet = mode->htotal - mode->hdisplay; | |
1139 | max_ac_packet -= rekey; | |
1140 | max_ac_packet -= 18; /* constant from tegra */ | |
1141 | max_ac_packet /= 32; | |
1142 | ||
1143 | /* AVI InfoFrame */ | |
1144 | nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000); | |
1145 | nv_wr32(dev, 0x61671c + head, 0x000d0282); | |
1146 | nv_wr32(dev, 0x616720 + head, 0x0000006f); | |
1147 | nv_wr32(dev, 0x616724 + head, 0x00000000); | |
1148 | nv_wr32(dev, 0x616728 + head, 0x00000000); | |
1149 | nv_wr32(dev, 0x61672c + head, 0x00000000); | |
1150 | nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001); | |
1151 | ||
1152 | /* ??? InfoFrame? */ | |
1153 | nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000); | |
1154 | nv_wr32(dev, 0x6167ac + head, 0x00000010); | |
1155 | nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001); | |
1156 | ||
1157 | /* HDMI_CTRL */ | |
1158 | nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey | | |
1159 | max_ac_packet << 16); | |
1160 | ||
091e40cd BS |
1161 | /* NFI, audio doesn't work without it though.. */ |
1162 | nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000); | |
1163 | ||
78951d22 BS |
1164 | nvd0_audio_mode_set(encoder, mode); |
1165 | } | |
1166 | ||
1167 | static void | |
1168 | nvd0_hdmi_disconnect(struct drm_encoder *encoder) | |
1169 | { | |
64d9cc04 BS |
1170 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1171 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
1172 | struct drm_device *dev = encoder->dev; | |
1173 | int head = nv_crtc->index * 0x800; | |
1174 | ||
78951d22 | 1175 | nvd0_audio_disconnect(encoder); |
64d9cc04 BS |
1176 | |
1177 | nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000); | |
1178 | nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000); | |
1179 | nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000); | |
78951d22 BS |
1180 | } |
1181 | ||
26f6d88b BS |
1182 | /****************************************************************************** |
1183 | * SOR | |
1184 | *****************************************************************************/ | |
6e83fda2 BS |
1185 | static inline u32 |
1186 | nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) | |
1187 | { | |
1188 | static const u8 nvd0[] = { 16, 8, 0, 24 }; | |
1189 | return nvd0[lane]; | |
1190 | } | |
1191 | ||
1192 | static void | |
1193 | nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern) | |
1194 | { | |
1195 | const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); | |
1196 | const u32 loff = (or * 0x800) + (link * 0x80); | |
1197 | nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); | |
1198 | } | |
1199 | ||
1200 | static void | |
1201 | nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb, | |
1202 | u8 lane, u8 swing, u8 preem) | |
1203 | { | |
1204 | const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); | |
1205 | const u32 loff = (or * 0x800) + (link * 0x80); | |
1206 | u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane); | |
1207 | u32 mask = 0x000000ff << shift; | |
1208 | u8 *table, *entry, *config = NULL; | |
1209 | ||
1210 | switch (swing) { | |
1211 | case 0: preem += 0; break; | |
1212 | case 1: preem += 4; break; | |
1213 | case 2: preem += 7; break; | |
1214 | case 3: preem += 9; break; | |
1215 | } | |
1216 | ||
1217 | table = nouveau_dp_bios_data(dev, dcb, &entry); | |
1218 | if (table) { | |
1219 | if (table[0] == 0x30) { | |
1220 | config = entry + table[4]; | |
1221 | config += table[5] * preem; | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | if (!config) { | |
1226 | NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n"); | |
1227 | return; | |
1228 | } | |
1229 | ||
1230 | nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift); | |
1231 | nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift); | |
1232 | nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8); | |
1233 | nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000); | |
1234 | } | |
1235 | ||
1236 | static void | |
1237 | nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc, | |
1238 | int link_nr, u32 link_bw, bool enhframe) | |
1239 | { | |
1240 | const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); | |
1241 | const u32 loff = (or * 0x800) + (link * 0x80); | |
1242 | const u32 soff = (or * 0x800); | |
1243 | u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000; | |
1244 | u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000; | |
1245 | u32 script = 0x0000, lane_mask = 0; | |
1246 | u8 *table, *entry; | |
1247 | int i; | |
1248 | ||
1249 | link_bw /= 27000; | |
1250 | ||
1251 | table = nouveau_dp_bios_data(dev, dcb, &entry); | |
1252 | if (table) { | |
1253 | if (table[0] == 0x30) entry = ROMPTR(dev, entry[10]); | |
1254 | else entry = NULL; | |
1255 | ||
1256 | while (entry) { | |
1257 | if (entry[0] >= link_bw) | |
1258 | break; | |
1259 | entry += 3; | |
1260 | } | |
1261 | ||
1262 | nouveau_bios_run_init_table(dev, script, dcb, crtc); | |
1263 | } | |
1264 | ||
1265 | clksor |= link_bw << 18; | |
1266 | dpctrl |= ((1 << link_nr) - 1) << 16; | |
1267 | if (enhframe) | |
1268 | dpctrl |= 0x00004000; | |
1269 | ||
1270 | for (i = 0; i < link_nr; i++) | |
1271 | lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3); | |
1272 | ||
1273 | nv_wr32(dev, 0x612300 + soff, clksor); | |
1274 | nv_wr32(dev, 0x61c10c + loff, dpctrl); | |
1275 | nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask); | |
1276 | } | |
1277 | ||
1278 | static void | |
1279 | nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb, | |
1280 | u32 *link_nr, u32 *link_bw) | |
1281 | { | |
1282 | const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); | |
1283 | const u32 loff = (or * 0x800) + (link * 0x80); | |
1284 | const u32 soff = (or * 0x800); | |
1285 | u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000; | |
1286 | u32 clksor = nv_rd32(dev, 0x612300 + soff); | |
1287 | ||
1288 | if (dpctrl > 0x00030000) *link_nr = 4; | |
1289 | else if (dpctrl > 0x00010000) *link_nr = 2; | |
1290 | else *link_nr = 1; | |
1291 | ||
1292 | *link_bw = (clksor & 0x007c0000) >> 18; | |
1293 | *link_bw *= 27000; | |
1294 | } | |
1295 | ||
1296 | static void | |
1297 | nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_entry *dcb, | |
1298 | u32 crtc, u32 datarate) | |
1299 | { | |
1300 | const u32 symbol = 100000; | |
1301 | const u32 TU = 64; | |
1302 | u32 link_nr, link_bw; | |
1303 | u64 ratio, value; | |
1304 | ||
1305 | nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw); | |
1306 | ||
1307 | ratio = datarate; | |
1308 | ratio *= symbol; | |
1309 | do_div(ratio, link_nr * link_bw); | |
1310 | ||
1311 | value = (symbol - ratio) * TU; | |
1312 | value *= ratio; | |
1313 | do_div(value, symbol); | |
1314 | do_div(value, symbol); | |
1315 | ||
1316 | value += 5; | |
1317 | value |= 0x08000000; | |
1318 | ||
1319 | nv_wr32(dev, 0x616610 + (crtc * 0x800), value); | |
1320 | } | |
1321 | ||
83fc083c BS |
1322 | static void |
1323 | nvd0_sor_dpms(struct drm_encoder *encoder, int mode) | |
1324 | { | |
1325 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1326 | struct drm_device *dev = encoder->dev; | |
1327 | struct drm_encoder *partner; | |
1328 | int or = nv_encoder->or; | |
1329 | u32 dpms_ctrl; | |
1330 | ||
1331 | nv_encoder->last_dpms = mode; | |
1332 | ||
1333 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1334 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1335 | ||
1336 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1337 | continue; | |
1338 | ||
1339 | if (nv_partner != nv_encoder && | |
26cfa813 | 1340 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1341 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1342 | return; | |
1343 | break; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | dpms_ctrl = (mode == DRM_MODE_DPMS_ON); | |
1348 | dpms_ctrl |= 0x80000000; | |
1349 | ||
1350 | nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); | |
1351 | nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl); | |
1352 | nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); | |
1353 | nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000); | |
6e83fda2 BS |
1354 | |
1355 | if (nv_encoder->dcb->type == OUTPUT_DP) { | |
1356 | struct dp_train_func func = { | |
1357 | .link_set = nvd0_sor_dp_link_set, | |
1358 | .train_set = nvd0_sor_dp_train_set, | |
1359 | .train_adj = nvd0_sor_dp_train_adj | |
1360 | }; | |
1361 | ||
1362 | nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func); | |
1363 | } | |
83fc083c BS |
1364 | } |
1365 | ||
1366 | static bool | |
1367 | nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
1368 | struct drm_display_mode *adjusted_mode) | |
1369 | { | |
1370 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1371 | struct nouveau_connector *nv_connector; | |
1372 | ||
1373 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1374 | if (nv_connector && nv_connector->native_mode) { | |
1375 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1376 | int id = adjusted_mode->base.id; | |
1377 | *adjusted_mode = *nv_connector->native_mode; | |
1378 | adjusted_mode->base.id = id; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | return true; | |
1383 | } | |
1384 | ||
4cbb0f8d BS |
1385 | static void |
1386 | nvd0_sor_disconnect(struct drm_encoder *encoder) | |
1387 | { | |
1388 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1389 | struct drm_device *dev = encoder->dev; | |
1390 | u32 *push; | |
1391 | ||
1392 | if (nv_encoder->crtc) { | |
1393 | nvd0_crtc_prepare(nv_encoder->crtc); | |
1394 | ||
1395 | push = evo_wait(dev, EVO_MASTER, 4); | |
1396 | if (push) { | |
1397 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); | |
1398 | evo_data(push, 0x00000000); | |
1399 | evo_mthd(push, 0x0080, 1); | |
1400 | evo_data(push, 0x00000000); | |
1401 | evo_kick(push, dev, EVO_MASTER); | |
1402 | } | |
1403 | ||
1404 | nvd0_hdmi_disconnect(encoder); | |
1405 | ||
1406 | nv_encoder->crtc = NULL; | |
1407 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1408 | } | |
1409 | } | |
1410 | ||
83fc083c BS |
1411 | static void |
1412 | nvd0_sor_prepare(struct drm_encoder *encoder) | |
1413 | { | |
4cbb0f8d BS |
1414 | nvd0_sor_disconnect(encoder); |
1415 | if (nouveau_encoder(encoder)->dcb->type == OUTPUT_DP) | |
1416 | evo_sync(encoder->dev, EVO_MASTER); | |
83fc083c BS |
1417 | } |
1418 | ||
1419 | static void | |
1420 | nvd0_sor_commit(struct drm_encoder *encoder) | |
1421 | { | |
1422 | } | |
1423 | ||
1424 | static void | |
3b6d83d1 BS |
1425 | nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
1426 | struct drm_display_mode *mode) | |
83fc083c | 1427 | { |
78951d22 BS |
1428 | struct drm_device *dev = encoder->dev; |
1429 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
83fc083c BS |
1430 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1431 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3b6d83d1 BS |
1432 | struct nouveau_connector *nv_connector; |
1433 | struct nvbios *bios = &dev_priv->vbios; | |
83fc083c | 1434 | u32 mode_ctrl = (1 << nv_crtc->index); |
3488c57b BS |
1435 | u32 syncs, magic, *push; |
1436 | u32 or_config; | |
1437 | ||
1438 | syncs = 0x00000001; | |
1439 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1440 | syncs |= 0x00000008; | |
1441 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1442 | syncs |= 0x00000010; | |
1443 | ||
1444 | magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1445 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1446 | magic |= 0x00000001; | |
83fc083c | 1447 | |
3b6d83d1 BS |
1448 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1449 | switch (nv_encoder->dcb->type) { | |
1450 | case OUTPUT_TMDS: | |
1451 | if (nv_encoder->dcb->sorconf.link & 1) { | |
1452 | if (mode->clock < 165000) | |
1453 | mode_ctrl |= 0x00000100; | |
1454 | else | |
1455 | mode_ctrl |= 0x00000500; | |
1456 | } else { | |
1457 | mode_ctrl |= 0x00000200; | |
1458 | } | |
1459 | ||
1460 | or_config = (mode_ctrl & 0x00000f00) >> 8; | |
1461 | if (mode->clock >= 165000) | |
1462 | or_config |= 0x0100; | |
78951d22 BS |
1463 | |
1464 | nvd0_hdmi_mode_set(encoder, mode); | |
3b6d83d1 BS |
1465 | break; |
1466 | case OUTPUT_LVDS: | |
1467 | or_config = (mode_ctrl & 0x00000f00) >> 8; | |
1468 | if (bios->fp_no_ddc) { | |
1469 | if (bios->fp.dual_link) | |
1470 | or_config |= 0x0100; | |
1471 | if (bios->fp.if_is_24bit) | |
1472 | or_config |= 0x0200; | |
1473 | } else { | |
befb51e9 | 1474 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 BS |
1475 | if (((u8 *)nv_connector->edid)[121] == 2) |
1476 | or_config |= 0x0100; | |
1477 | } else | |
1478 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
1479 | or_config |= 0x0100; | |
1480 | } | |
83fc083c | 1481 | |
3b6d83d1 BS |
1482 | if (or_config & 0x0100) { |
1483 | if (bios->fp.strapless_is_24bit & 2) | |
1484 | or_config |= 0x0200; | |
1485 | } else { | |
1486 | if (bios->fp.strapless_is_24bit & 1) | |
1487 | or_config |= 0x0200; | |
1488 | } | |
1489 | ||
1490 | if (nv_connector->base.display_info.bpc == 8) | |
1491 | or_config |= 0x0200; | |
1492 | ||
1493 | } | |
1494 | break; | |
6e83fda2 | 1495 | case OUTPUT_DP: |
3488c57b | 1496 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 1497 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
3488c57b BS |
1498 | syncs |= 0x00000140; |
1499 | } else { | |
6e83fda2 | 1500 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
3488c57b BS |
1501 | syncs |= 0x00000180; |
1502 | } | |
6e83fda2 BS |
1503 | |
1504 | if (nv_encoder->dcb->sorconf.link & 1) | |
1505 | mode_ctrl |= 0x00000800; | |
1506 | else | |
1507 | mode_ctrl |= 0x00000900; | |
1508 | ||
1509 | or_config = (mode_ctrl & 0x00000f00) >> 8; | |
1510 | break; | |
3b6d83d1 BS |
1511 | default: |
1512 | BUG_ON(1); | |
1513 | break; | |
1514 | } | |
ff8ff503 | 1515 | |
83fc083c BS |
1516 | nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON); |
1517 | ||
6e83fda2 BS |
1518 | if (nv_encoder->dcb->type == OUTPUT_DP) { |
1519 | nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index, | |
1520 | nv_encoder->dp.datarate); | |
1521 | } | |
1522 | ||
3488c57b | 1523 | push = evo_wait(dev, EVO_MASTER, 8); |
83fc083c | 1524 | if (push) { |
3488c57b BS |
1525 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
1526 | evo_data(push, syncs); | |
1527 | evo_data(push, magic); | |
1528 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2); | |
83fc083c | 1529 | evo_data(push, mode_ctrl); |
ff8ff503 | 1530 | evo_data(push, or_config); |
2eac77b7 | 1531 | evo_kick(push, dev, EVO_MASTER); |
83fc083c BS |
1532 | } |
1533 | ||
1534 | nv_encoder->crtc = encoder->crtc; | |
1535 | } | |
1536 | ||
83fc083c BS |
1537 | static void |
1538 | nvd0_sor_destroy(struct drm_encoder *encoder) | |
1539 | { | |
1540 | drm_encoder_cleanup(encoder); | |
1541 | kfree(encoder); | |
1542 | } | |
1543 | ||
1544 | static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = { | |
1545 | .dpms = nvd0_sor_dpms, | |
1546 | .mode_fixup = nvd0_sor_mode_fixup, | |
1547 | .prepare = nvd0_sor_prepare, | |
1548 | .commit = nvd0_sor_commit, | |
1549 | .mode_set = nvd0_sor_mode_set, | |
1550 | .disable = nvd0_sor_disconnect, | |
1551 | .get_crtc = nvd0_display_crtc_get, | |
1552 | }; | |
1553 | ||
1554 | static const struct drm_encoder_funcs nvd0_sor_func = { | |
1555 | .destroy = nvd0_sor_destroy, | |
1556 | }; | |
1557 | ||
1558 | static int | |
1559 | nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe) | |
1560 | { | |
1561 | struct drm_device *dev = connector->dev; | |
1562 | struct nouveau_encoder *nv_encoder; | |
1563 | struct drm_encoder *encoder; | |
1564 | ||
1565 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1566 | if (!nv_encoder) | |
1567 | return -ENOMEM; | |
1568 | nv_encoder->dcb = dcbe; | |
1569 | nv_encoder->or = ffs(dcbe->or) - 1; | |
1570 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1571 | ||
1572 | encoder = to_drm_encoder(nv_encoder); | |
1573 | encoder->possible_crtcs = dcbe->heads; | |
1574 | encoder->possible_clones = 0; | |
1575 | drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS); | |
1576 | drm_encoder_helper_add(encoder, &nvd0_sor_hfunc); | |
1577 | ||
1578 | drm_mode_connector_attach_encoder(connector, encoder); | |
1579 | return 0; | |
1580 | } | |
26f6d88b BS |
1581 | |
1582 | /****************************************************************************** | |
1583 | * IRQ | |
1584 | *****************************************************************************/ | |
3a89cd02 BS |
1585 | static struct dcb_entry * |
1586 | lookup_dcb(struct drm_device *dev, int id, u32 mc) | |
1587 | { | |
1588 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c674844b | 1589 | int type, or, i, link = -1; |
3a89cd02 BS |
1590 | |
1591 | if (id < 4) { | |
1592 | type = OUTPUT_ANALOG; | |
1593 | or = id; | |
1594 | } else { | |
3b6d83d1 | 1595 | switch (mc & 0x00000f00) { |
c674844b BS |
1596 | case 0x00000000: link = 0; type = OUTPUT_LVDS; break; |
1597 | case 0x00000100: link = 0; type = OUTPUT_TMDS; break; | |
1598 | case 0x00000200: link = 1; type = OUTPUT_TMDS; break; | |
1599 | case 0x00000500: link = 0; type = OUTPUT_TMDS; break; | |
1600 | case 0x00000800: link = 0; type = OUTPUT_DP; break; | |
1601 | case 0x00000900: link = 1; type = OUTPUT_DP; break; | |
3b6d83d1 | 1602 | default: |
ee41779e | 1603 | NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc); |
3b6d83d1 BS |
1604 | return NULL; |
1605 | } | |
1606 | ||
1607 | or = id - 4; | |
3a89cd02 BS |
1608 | } |
1609 | ||
1610 | for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { | |
1611 | struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; | |
c674844b BS |
1612 | if (dcb->type == type && (dcb->or & (1 << or)) && |
1613 | (link < 0 || link == !(dcb->sorconf.link & 1))) | |
3a89cd02 BS |
1614 | return dcb; |
1615 | } | |
1616 | ||
ee41779e | 1617 | NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc); |
3a89cd02 BS |
1618 | return NULL; |
1619 | } | |
1620 | ||
270a5747 | 1621 | static void |
37b034a6 | 1622 | nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask) |
270a5747 | 1623 | { |
3a89cd02 | 1624 | struct dcb_entry *dcb; |
3a89cd02 BS |
1625 | int i; |
1626 | ||
ee41779e | 1627 | for (i = 0; mask && i < 8; i++) { |
3a89cd02 | 1628 | u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20)); |
ee41779e BS |
1629 | if (!(mcc & (1 << crtc))) |
1630 | continue; | |
3a89cd02 | 1631 | |
ee41779e BS |
1632 | dcb = lookup_dcb(dev, i, mcc); |
1633 | if (!dcb) | |
1634 | continue; | |
3a89cd02 | 1635 | |
3a89cd02 | 1636 | nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc); |
ee41779e | 1637 | } |
3a89cd02 | 1638 | |
270a5747 BS |
1639 | nv_wr32(dev, 0x6101d4, 0x00000000); |
1640 | nv_wr32(dev, 0x6109d4, 0x00000000); | |
1641 | nv_wr32(dev, 0x6101d0, 0x80000000); | |
1642 | } | |
1643 | ||
1644 | static void | |
37b034a6 | 1645 | nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask) |
270a5747 | 1646 | { |
3a89cd02 | 1647 | struct dcb_entry *dcb; |
37b034a6 | 1648 | u32 or, tmp, pclk; |
ee41779e | 1649 | int i; |
3a89cd02 | 1650 | |
ee41779e BS |
1651 | for (i = 0; mask && i < 8; i++) { |
1652 | u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20)); | |
1653 | if (!(mcc & (1 << crtc))) | |
1654 | continue; | |
1655 | ||
1656 | dcb = lookup_dcb(dev, i, mcc); | |
1657 | if (!dcb) | |
1658 | continue; | |
270a5747 | 1659 | |
3a89cd02 | 1660 | nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc); |
ee41779e | 1661 | } |
3a89cd02 | 1662 | |
ee41779e BS |
1663 | pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; |
1664 | if (mask & 0x00010000) { | |
1665 | nv50_crtc_set_clock(dev, crtc, pclk); | |
1666 | } | |
3a89cd02 | 1667 | |
ee41779e BS |
1668 | for (i = 0; mask && i < 8; i++) { |
1669 | u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20)); | |
1670 | u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20)); | |
1671 | if (!(mcp & (1 << crtc))) | |
1672 | continue; | |
3a89cd02 | 1673 | |
ee41779e BS |
1674 | dcb = lookup_dcb(dev, i, mcp); |
1675 | if (!dcb) | |
1676 | continue; | |
1677 | or = ffs(dcb->or) - 1; | |
3a89cd02 | 1678 | |
ee41779e BS |
1679 | nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc); |
1680 | ||
1681 | nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000); | |
1682 | switch (dcb->type) { | |
1683 | case OUTPUT_ANALOG: | |
1684 | nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000); | |
1685 | break; | |
1686 | case OUTPUT_TMDS: | |
1687 | case OUTPUT_LVDS: | |
6e83fda2 | 1688 | case OUTPUT_DP: |
ee41779e BS |
1689 | if (cfg & 0x00000100) |
1690 | tmp = 0x00000101; | |
1691 | else | |
1692 | tmp = 0x00000000; | |
1693 | ||
1694 | nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp); | |
1695 | break; | |
1696 | default: | |
1697 | break; | |
1698 | } | |
3a89cd02 | 1699 | |
3a89cd02 BS |
1700 | break; |
1701 | } | |
1702 | ||
270a5747 BS |
1703 | nv_wr32(dev, 0x6101d4, 0x00000000); |
1704 | nv_wr32(dev, 0x6109d4, 0x00000000); | |
1705 | nv_wr32(dev, 0x6101d0, 0x80000000); | |
1706 | } | |
1707 | ||
1708 | static void | |
37b034a6 | 1709 | nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask) |
270a5747 | 1710 | { |
3a89cd02 | 1711 | struct dcb_entry *dcb; |
ee41779e | 1712 | int pclk, i; |
3a89cd02 | 1713 | |
ee41779e | 1714 | pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; |
3a89cd02 | 1715 | |
ee41779e BS |
1716 | for (i = 0; mask && i < 8; i++) { |
1717 | u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20)); | |
1718 | u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20)); | |
1719 | if (!(mcp & (1 << crtc))) | |
1720 | continue; | |
1721 | ||
1722 | dcb = lookup_dcb(dev, i, mcp); | |
1723 | if (!dcb) | |
1724 | continue; | |
1725 | ||
1726 | nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc); | |
1727 | } | |
3a89cd02 | 1728 | |
270a5747 BS |
1729 | nv_wr32(dev, 0x6101d4, 0x00000000); |
1730 | nv_wr32(dev, 0x6109d4, 0x00000000); | |
1731 | nv_wr32(dev, 0x6101d0, 0x80000000); | |
1732 | } | |
1733 | ||
f20ce962 BS |
1734 | static void |
1735 | nvd0_display_bh(unsigned long data) | |
1736 | { | |
1737 | struct drm_device *dev = (struct drm_device *)data; | |
1738 | struct nvd0_display *disp = nvd0_display(dev); | |
7c5f6a87 | 1739 | u32 mask = 0, crtc = ~0; |
37b034a6 BS |
1740 | int i; |
1741 | ||
1742 | if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) { | |
1743 | NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset); | |
1744 | NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n", | |
1745 | nv_rd32(dev, 0x6101d0), | |
1746 | nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4)); | |
1747 | for (i = 0; i < 8; i++) { | |
1748 | NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n", | |
1749 | i < 4 ? "DAC" : "SOR", i, | |
1750 | nv_rd32(dev, 0x640180 + (i * 0x20)), | |
1751 | nv_rd32(dev, 0x660180 + (i * 0x20))); | |
1752 | } | |
1753 | } | |
1754 | ||
7c5f6a87 BS |
1755 | while (!mask && ++crtc < dev->mode_config.num_crtc) |
1756 | mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800)); | |
f20ce962 | 1757 | |
ee41779e | 1758 | if (disp->modeset & 0x00000001) |
37b034a6 | 1759 | nvd0_display_unk1_handler(dev, crtc, mask); |
ee41779e | 1760 | if (disp->modeset & 0x00000002) |
37b034a6 | 1761 | nvd0_display_unk2_handler(dev, crtc, mask); |
ee41779e | 1762 | if (disp->modeset & 0x00000004) |
37b034a6 | 1763 | nvd0_display_unk4_handler(dev, crtc, mask); |
f20ce962 BS |
1764 | } |
1765 | ||
4600522a BS |
1766 | static void |
1767 | nvd0_display_intr(struct drm_device *dev) | |
1768 | { | |
f20ce962 | 1769 | struct nvd0_display *disp = nvd0_display(dev); |
4600522a | 1770 | u32 intr = nv_rd32(dev, 0x610088); |
7c5f6a87 | 1771 | int i; |
4600522a | 1772 | |
84e052e6 BS |
1773 | if (intr & 0x00000001) { |
1774 | u32 stat = nv_rd32(dev, 0x61008c); | |
1775 | nv_wr32(dev, 0x61008c, stat); | |
1776 | intr &= ~0x00000001; | |
1777 | } | |
1778 | ||
4600522a BS |
1779 | if (intr & 0x00000002) { |
1780 | u32 stat = nv_rd32(dev, 0x61009c); | |
1781 | int chid = ffs(stat) - 1; | |
1782 | if (chid >= 0) { | |
1783 | u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12)); | |
1784 | u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12)); | |
1785 | u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12)); | |
1786 | ||
1787 | NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x " | |
1788 | "0x%08x 0x%08x\n", | |
1789 | chid, (mthd & 0x0000ffc), data, mthd, unkn); | |
1790 | nv_wr32(dev, 0x61009c, (1 << chid)); | |
1791 | nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000); | |
1792 | } | |
1793 | ||
1794 | intr &= ~0x00000002; | |
1795 | } | |
1796 | ||
270a5747 BS |
1797 | if (intr & 0x00100000) { |
1798 | u32 stat = nv_rd32(dev, 0x6100ac); | |
1799 | ||
1800 | if (stat & 0x00000007) { | |
ee41779e | 1801 | disp->modeset = stat; |
f20ce962 | 1802 | tasklet_schedule(&disp->tasklet); |
270a5747 | 1803 | |
f20ce962 | 1804 | nv_wr32(dev, 0x6100ac, (stat & 0x00000007)); |
270a5747 BS |
1805 | stat &= ~0x00000007; |
1806 | } | |
1807 | ||
1808 | if (stat) { | |
1809 | NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat); | |
1810 | nv_wr32(dev, 0x6100ac, stat); | |
1811 | } | |
1812 | ||
1813 | intr &= ~0x00100000; | |
1814 | } | |
1815 | ||
7c5f6a87 BS |
1816 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
1817 | u32 mask = 0x01000000 << i; | |
1818 | if (intr & mask) { | |
1819 | u32 stat = nv_rd32(dev, 0x6100bc + (i * 0x800)); | |
1820 | nv_wr32(dev, 0x6100bc + (i * 0x800), stat); | |
1821 | intr &= ~mask; | |
1822 | } | |
4600522a BS |
1823 | } |
1824 | ||
1825 | if (intr) | |
1826 | NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr); | |
1827 | } | |
26f6d88b BS |
1828 | |
1829 | /****************************************************************************** | |
1830 | * Init | |
1831 | *****************************************************************************/ | |
2a44e499 | 1832 | void |
26f6d88b BS |
1833 | nvd0_display_fini(struct drm_device *dev) |
1834 | { | |
1835 | int i; | |
1836 | ||
a63a97eb | 1837 | /* fini cursors + overlays + flips */ |
bdb8c212 BS |
1838 | for (i = 1; i >= 0; i--) { |
1839 | evo_fini_pio(dev, EVO_CURS(i)); | |
8a46438a BS |
1840 | evo_fini_pio(dev, EVO_OIMM(i)); |
1841 | evo_fini_dma(dev, EVO_OVLY(i)); | |
a63a97eb | 1842 | evo_fini_dma(dev, EVO_FLIP(i)); |
26f6d88b BS |
1843 | } |
1844 | ||
1845 | /* fini master */ | |
bdb8c212 | 1846 | evo_fini_dma(dev, EVO_MASTER); |
26f6d88b BS |
1847 | } |
1848 | ||
1849 | int | |
1850 | nvd0_display_init(struct drm_device *dev) | |
1851 | { | |
1852 | struct nvd0_display *disp = nvd0_display(dev); | |
bdb8c212 | 1853 | int ret, i; |
efd272a7 | 1854 | u32 *push; |
26f6d88b | 1855 | |
a36f04c0 BS |
1856 | if (nv_rd32(dev, 0x6100ac) & 0x00000100) { |
1857 | nv_wr32(dev, 0x6100ac, 0x00000100); | |
1858 | nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000); | |
1859 | if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) { | |
1860 | NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n", | |
1861 | nv_rd32(dev, 0x6194e8)); | |
1862 | return -EBUSY; | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't | |
1867 | * work at all unless you do the SOR part below. | |
1868 | */ | |
1d6e7a59 BS |
1869 | for (i = 0; i < 3; i++) { |
1870 | u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800)); | |
1871 | nv_wr32(dev, 0x6101c0 + (i * 0x800), dac); | |
1872 | } | |
1873 | ||
1d6e7a59 BS |
1874 | for (i = 0; i < 4; i++) { |
1875 | u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800)); | |
1876 | nv_wr32(dev, 0x6301c4 + (i * 0x800), sor); | |
1877 | } | |
1878 | ||
bdb8c212 | 1879 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
a36f04c0 BS |
1880 | u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800)); |
1881 | u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800)); | |
1882 | u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800)); | |
1883 | nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0); | |
1884 | nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1); | |
1885 | nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2); | |
26f6d88b BS |
1886 | } |
1887 | ||
a36f04c0 | 1888 | /* point at our hash table / objects, enable interrupts */ |
26f6d88b | 1889 | nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9); |
270a5747 | 1890 | nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307); |
26f6d88b BS |
1891 | |
1892 | /* init master */ | |
bdb8c212 BS |
1893 | ret = evo_init_dma(dev, EVO_MASTER); |
1894 | if (ret) | |
1895 | goto error; | |
26f6d88b | 1896 | |
a63a97eb | 1897 | /* init flips + overlays + cursors */ |
bdb8c212 | 1898 | for (i = 0; i < dev->mode_config.num_crtc; i++) { |
a63a97eb | 1899 | if ((ret = evo_init_dma(dev, EVO_FLIP(i))) || |
8a46438a BS |
1900 | (ret = evo_init_dma(dev, EVO_OVLY(i))) || |
1901 | (ret = evo_init_pio(dev, EVO_OIMM(i))) || | |
bdb8c212 BS |
1902 | (ret = evo_init_pio(dev, EVO_CURS(i)))) |
1903 | goto error; | |
26f6d88b BS |
1904 | } |
1905 | ||
2eac77b7 | 1906 | push = evo_wait(dev, EVO_MASTER, 32); |
bdb8c212 BS |
1907 | if (!push) { |
1908 | ret = -EBUSY; | |
1909 | goto error; | |
1910 | } | |
efd272a7 | 1911 | evo_mthd(push, 0x0088, 1); |
37b034a6 | 1912 | evo_data(push, NvEvoSync); |
efd272a7 BS |
1913 | evo_mthd(push, 0x0084, 1); |
1914 | evo_data(push, 0x00000000); | |
1915 | evo_mthd(push, 0x0084, 1); | |
1916 | evo_data(push, 0x80000000); | |
1917 | evo_mthd(push, 0x008c, 1); | |
1918 | evo_data(push, 0x00000000); | |
2eac77b7 | 1919 | evo_kick(push, dev, EVO_MASTER); |
efd272a7 | 1920 | |
bdb8c212 BS |
1921 | error: |
1922 | if (ret) | |
1923 | nvd0_display_fini(dev); | |
1924 | return ret; | |
26f6d88b BS |
1925 | } |
1926 | ||
1927 | void | |
1928 | nvd0_display_destroy(struct drm_device *dev) | |
1929 | { | |
1930 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1931 | struct nvd0_display *disp = nvd0_display(dev); | |
51beb428 | 1932 | struct pci_dev *pdev = dev->pdev; |
bdb8c212 BS |
1933 | int i; |
1934 | ||
8a46438a | 1935 | for (i = 0; i < EVO_DMA_NR; i++) { |
3376ee37 | 1936 | struct evo *evo = &disp->evo[i]; |
3376ee37 | 1937 | pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle); |
bdb8c212 | 1938 | } |
26f6d88b | 1939 | |
26f6d88b | 1940 | nouveau_gpuobj_ref(NULL, &disp->mem); |
816af2f2 BS |
1941 | nouveau_bo_unmap(disp->sync); |
1942 | nouveau_bo_ref(NULL, &disp->sync); | |
4600522a | 1943 | nouveau_irq_unregister(dev, 26); |
51beb428 BS |
1944 | |
1945 | dev_priv->engine.display.priv = NULL; | |
26f6d88b BS |
1946 | kfree(disp); |
1947 | } | |
1948 | ||
1949 | int | |
1950 | nvd0_display_create(struct drm_device *dev) | |
1951 | { | |
1952 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
efd272a7 | 1953 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; |
83fc083c BS |
1954 | struct dcb_table *dcb = &dev_priv->vbios.dcb; |
1955 | struct drm_connector *connector, *tmp; | |
51beb428 | 1956 | struct pci_dev *pdev = dev->pdev; |
26f6d88b | 1957 | struct nvd0_display *disp; |
83fc083c | 1958 | struct dcb_entry *dcbe; |
7c5f6a87 | 1959 | int crtcs, ret, i; |
26f6d88b BS |
1960 | |
1961 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
1962 | if (!disp) | |
1963 | return -ENOMEM; | |
1964 | dev_priv->engine.display.priv = disp; | |
1965 | ||
438d99e3 | 1966 | /* create crtc objects to represent the hw heads */ |
7c5f6a87 BS |
1967 | crtcs = nv_rd32(dev, 0x022448); |
1968 | for (i = 0; i < crtcs; i++) { | |
438d99e3 BS |
1969 | ret = nvd0_crtc_create(dev, i); |
1970 | if (ret) | |
1971 | goto out; | |
1972 | } | |
1973 | ||
83fc083c BS |
1974 | /* create encoder/connector objects based on VBIOS DCB table */ |
1975 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
1976 | connector = nouveau_connector_create(dev, dcbe->connector); | |
1977 | if (IS_ERR(connector)) | |
1978 | continue; | |
1979 | ||
1980 | if (dcbe->location != DCB_LOC_ON_CHIP) { | |
1981 | NV_WARN(dev, "skipping off-chip encoder %d/%d\n", | |
1982 | dcbe->type, ffs(dcbe->or) - 1); | |
1983 | continue; | |
1984 | } | |
1985 | ||
1986 | switch (dcbe->type) { | |
1987 | case OUTPUT_TMDS: | |
3b6d83d1 | 1988 | case OUTPUT_LVDS: |
6e83fda2 | 1989 | case OUTPUT_DP: |
83fc083c BS |
1990 | nvd0_sor_create(connector, dcbe); |
1991 | break; | |
8eaa9669 BS |
1992 | case OUTPUT_ANALOG: |
1993 | nvd0_dac_create(connector, dcbe); | |
1994 | break; | |
83fc083c BS |
1995 | default: |
1996 | NV_WARN(dev, "skipping unsupported encoder %d/%d\n", | |
1997 | dcbe->type, ffs(dcbe->or) - 1); | |
1998 | continue; | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | /* cull any connectors we created that don't have an encoder */ | |
2003 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2004 | if (connector->encoder_ids[0]) | |
2005 | continue; | |
2006 | ||
2007 | NV_WARN(dev, "%s has no encoders, removing\n", | |
2008 | drm_get_connector_name(connector)); | |
2009 | connector->funcs->destroy(connector); | |
2010 | } | |
2011 | ||
4600522a | 2012 | /* setup interrupt handling */ |
f20ce962 | 2013 | tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev); |
4600522a BS |
2014 | nouveau_irq_register(dev, 26, nvd0_display_intr); |
2015 | ||
816af2f2 BS |
2016 | /* small shared memory area we use for notifiers and semaphores */ |
2017 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
2018 | 0, 0x0000, &disp->sync); | |
2019 | if (!ret) { | |
2020 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); | |
2021 | if (!ret) | |
2022 | ret = nouveau_bo_map(disp->sync); | |
2023 | if (ret) | |
2024 | nouveau_bo_ref(NULL, &disp->sync); | |
2025 | } | |
2026 | ||
2027 | if (ret) | |
2028 | goto out; | |
2029 | ||
51beb428 | 2030 | /* hash table and dma objects for the memory areas we care about */ |
efd272a7 BS |
2031 | ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000, |
2032 | NVOBJ_FLAG_ZERO_ALLOC, &disp->mem); | |
26f6d88b BS |
2033 | if (ret) |
2034 | goto out; | |
2035 | ||
3376ee37 | 2036 | /* create evo dma channels */ |
8a46438a | 2037 | for (i = 0; i < EVO_DMA_NR; i++) { |
3376ee37 | 2038 | struct evo *evo = &disp->evo[i]; |
816af2f2 | 2039 | u64 offset = disp->sync->bo.offset; |
3376ee37 BS |
2040 | u32 dmao = 0x1000 + (i * 0x100); |
2041 | u32 hash = 0x0000 + (i * 0x040); | |
3376ee37 BS |
2042 | |
2043 | evo->idx = i; | |
816af2f2 | 2044 | evo->sem.offset = EVO_SYNC(evo->idx, 0x00); |
3376ee37 BS |
2045 | evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle); |
2046 | if (!evo->ptr) { | |
bdb8c212 BS |
2047 | ret = -ENOMEM; |
2048 | goto out; | |
2049 | } | |
3376ee37 | 2050 | |
3376ee37 BS |
2051 | nv_wo32(disp->mem, dmao + 0x00, 0x00000049); |
2052 | nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8); | |
2053 | nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8); | |
2054 | nv_wo32(disp->mem, dmao + 0x0c, 0x00000000); | |
2055 | nv_wo32(disp->mem, dmao + 0x10, 0x00000000); | |
2056 | nv_wo32(disp->mem, dmao + 0x14, 0x00000000); | |
2057 | nv_wo32(disp->mem, hash + 0x00, NvEvoSync); | |
2058 | nv_wo32(disp->mem, hash + 0x04, 0x00000001 | (i << 27) | | |
2059 | ((dmao + 0x00) << 9)); | |
2060 | ||
2061 | nv_wo32(disp->mem, dmao + 0x20, 0x00000049); | |
2062 | nv_wo32(disp->mem, dmao + 0x24, 0x00000000); | |
2063 | nv_wo32(disp->mem, dmao + 0x28, (dev_priv->vram_size - 1) >> 8); | |
2064 | nv_wo32(disp->mem, dmao + 0x2c, 0x00000000); | |
2065 | nv_wo32(disp->mem, dmao + 0x30, 0x00000000); | |
2066 | nv_wo32(disp->mem, dmao + 0x34, 0x00000000); | |
2067 | nv_wo32(disp->mem, hash + 0x08, NvEvoVRAM); | |
2068 | nv_wo32(disp->mem, hash + 0x0c, 0x00000001 | (i << 27) | | |
2069 | ((dmao + 0x20) << 9)); | |
2070 | ||
2071 | nv_wo32(disp->mem, dmao + 0x40, 0x00000009); | |
2072 | nv_wo32(disp->mem, dmao + 0x44, 0x00000000); | |
2073 | nv_wo32(disp->mem, dmao + 0x48, (dev_priv->vram_size - 1) >> 8); | |
2074 | nv_wo32(disp->mem, dmao + 0x4c, 0x00000000); | |
2075 | nv_wo32(disp->mem, dmao + 0x50, 0x00000000); | |
2076 | nv_wo32(disp->mem, dmao + 0x54, 0x00000000); | |
2077 | nv_wo32(disp->mem, hash + 0x10, NvEvoVRAM_LP); | |
2078 | nv_wo32(disp->mem, hash + 0x14, 0x00000001 | (i << 27) | | |
2079 | ((dmao + 0x40) << 9)); | |
2080 | ||
2081 | nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009); | |
2082 | nv_wo32(disp->mem, dmao + 0x64, 0x00000000); | |
2083 | nv_wo32(disp->mem, dmao + 0x68, (dev_priv->vram_size - 1) >> 8); | |
2084 | nv_wo32(disp->mem, dmao + 0x6c, 0x00000000); | |
2085 | nv_wo32(disp->mem, dmao + 0x70, 0x00000000); | |
2086 | nv_wo32(disp->mem, dmao + 0x74, 0x00000000); | |
2087 | nv_wo32(disp->mem, hash + 0x18, NvEvoFB32); | |
2088 | nv_wo32(disp->mem, hash + 0x1c, 0x00000001 | (i << 27) | | |
2089 | ((dmao + 0x60) << 9)); | |
51beb428 BS |
2090 | } |
2091 | ||
3376ee37 BS |
2092 | pinstmem->flush(dev); |
2093 | ||
26f6d88b BS |
2094 | out: |
2095 | if (ret) | |
2096 | nvd0_display_destroy(dev); | |
2097 | return ret; | |
2098 | } |