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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b BS |
24 | #include "priv.h" |
25 | #include "acpi.h" | |
9274f4a9 | 26 | |
9719047b | 27 | #include <core/notify.h> |
a1bfb29a | 28 | #include <core/option.h> |
d01c3092 | 29 | |
a1bfb29a | 30 | #include <subdev/bios.h> |
9274f4a9 BS |
31 | |
32 | static DEFINE_MUTEX(nv_devices_mutex); | |
33 | static LIST_HEAD(nv_devices); | |
34 | ||
7974dd1b BS |
35 | static struct nvkm_device * |
36 | nvkm_device_find_locked(u64 handle) | |
9274f4a9 | 37 | { |
7974dd1b | 38 | struct nvkm_device *device; |
9274f4a9 | 39 | list_for_each_entry(device, &nv_devices, head) { |
7974dd1b BS |
40 | if (device->handle == handle) |
41 | return device; | |
9274f4a9 | 42 | } |
7974dd1b BS |
43 | return NULL; |
44 | } | |
45 | ||
46 | struct nvkm_device * | |
47 | nvkm_device_find(u64 handle) | |
48 | { | |
49 | struct nvkm_device *device; | |
50 | mutex_lock(&nv_devices_mutex); | |
51 | device = nvkm_device_find_locked(handle); | |
9274f4a9 | 52 | mutex_unlock(&nv_devices_mutex); |
7974dd1b | 53 | return device; |
9274f4a9 BS |
54 | } |
55 | ||
803c1787 | 56 | int |
9719047b | 57 | nvkm_device_list(u64 *name, int size) |
803c1787 | 58 | { |
9719047b | 59 | struct nvkm_device *device; |
803c1787 BS |
60 | int nr = 0; |
61 | mutex_lock(&nv_devices_mutex); | |
62 | list_for_each_entry(device, &nv_devices, head) { | |
63 | if (nr++ < size) | |
64 | name[nr - 1] = device->handle; | |
65 | } | |
66 | mutex_unlock(&nv_devices_mutex); | |
67 | return nr; | |
68 | } | |
69 | ||
6cf813fb BS |
70 | static const struct nvkm_device_chip |
71 | null_chipset = { | |
72 | .name = "NULL", | |
46484438 | 73 | .bios = nvkm_bios_new, |
6cf813fb BS |
74 | }; |
75 | ||
76 | static const struct nvkm_device_chip | |
77 | nv4_chipset = { | |
78 | .name = "NV04", | |
46484438 | 79 | .bios = nvkm_bios_new, |
bb23f9d7 | 80 | .bus = nv04_bus_new, |
6625f55c | 81 | .clk = nv04_clk_new, |
151abd44 | 82 | .devinit = nv04_devinit_new, |
03c8952f | 83 | .fb = nv04_fb_new, |
49bd8da5 | 84 | .i2c = nv04_i2c_new, |
b7a2bc18 | 85 | .imem = nv04_instmem_new, |
54dcadd5 | 86 | .mc = nv04_mc_new, |
c9582455 | 87 | .mmu = nv04_mmu_new, |
0a34fb31 | 88 | .pci = nv04_pci_new, |
31649ecf | 89 | .timer = nv04_timer_new, |
70aa8670 | 90 | .disp = nv04_disp_new, |
bd70563f | 91 | .dma = nv04_dma_new, |
13de7f46 | 92 | .fifo = nv04_fifo_new, |
c85ee6ca | 93 | .gr = nv04_gr_new, |
6f41c7c5 | 94 | .sw = nv04_sw_new, |
6cf813fb BS |
95 | }; |
96 | ||
97 | static const struct nvkm_device_chip | |
98 | nv5_chipset = { | |
99 | .name = "NV05", | |
46484438 | 100 | .bios = nvkm_bios_new, |
bb23f9d7 | 101 | .bus = nv04_bus_new, |
6625f55c | 102 | .clk = nv04_clk_new, |
151abd44 | 103 | .devinit = nv05_devinit_new, |
03c8952f | 104 | .fb = nv04_fb_new, |
49bd8da5 | 105 | .i2c = nv04_i2c_new, |
b7a2bc18 | 106 | .imem = nv04_instmem_new, |
54dcadd5 | 107 | .mc = nv04_mc_new, |
c9582455 | 108 | .mmu = nv04_mmu_new, |
0a34fb31 | 109 | .pci = nv04_pci_new, |
31649ecf | 110 | .timer = nv04_timer_new, |
70aa8670 | 111 | .disp = nv04_disp_new, |
bd70563f | 112 | .dma = nv04_dma_new, |
13de7f46 | 113 | .fifo = nv04_fifo_new, |
c85ee6ca | 114 | .gr = nv04_gr_new, |
6f41c7c5 | 115 | .sw = nv04_sw_new, |
6cf813fb BS |
116 | }; |
117 | ||
118 | static const struct nvkm_device_chip | |
119 | nv10_chipset = { | |
120 | .name = "NV10", | |
46484438 | 121 | .bios = nvkm_bios_new, |
bb23f9d7 | 122 | .bus = nv04_bus_new, |
6625f55c | 123 | .clk = nv04_clk_new, |
151abd44 | 124 | .devinit = nv10_devinit_new, |
03c8952f | 125 | .fb = nv10_fb_new, |
2ea7249f | 126 | .gpio = nv10_gpio_new, |
49bd8da5 | 127 | .i2c = nv04_i2c_new, |
b7a2bc18 | 128 | .imem = nv04_instmem_new, |
54dcadd5 | 129 | .mc = nv04_mc_new, |
c9582455 | 130 | .mmu = nv04_mmu_new, |
0a34fb31 | 131 | .pci = nv04_pci_new, |
31649ecf | 132 | .timer = nv04_timer_new, |
70aa8670 | 133 | .disp = nv04_disp_new, |
bd70563f | 134 | .dma = nv04_dma_new, |
c85ee6ca | 135 | .gr = nv10_gr_new, |
6cf813fb BS |
136 | }; |
137 | ||
138 | static const struct nvkm_device_chip | |
139 | nv11_chipset = { | |
140 | .name = "NV11", | |
46484438 | 141 | .bios = nvkm_bios_new, |
bb23f9d7 | 142 | .bus = nv04_bus_new, |
6625f55c | 143 | .clk = nv04_clk_new, |
151abd44 | 144 | .devinit = nv10_devinit_new, |
03c8952f | 145 | .fb = nv10_fb_new, |
2ea7249f | 146 | .gpio = nv10_gpio_new, |
49bd8da5 | 147 | .i2c = nv04_i2c_new, |
b7a2bc18 | 148 | .imem = nv04_instmem_new, |
667e99ab | 149 | .mc = nv11_mc_new, |
c9582455 | 150 | .mmu = nv04_mmu_new, |
0a34fb31 | 151 | .pci = nv04_pci_new, |
31649ecf | 152 | .timer = nv04_timer_new, |
70aa8670 | 153 | .disp = nv04_disp_new, |
bd70563f | 154 | .dma = nv04_dma_new, |
13de7f46 | 155 | .fifo = nv10_fifo_new, |
c85ee6ca | 156 | .gr = nv15_gr_new, |
6f41c7c5 | 157 | .sw = nv10_sw_new, |
6cf813fb BS |
158 | }; |
159 | ||
160 | static const struct nvkm_device_chip | |
161 | nv15_chipset = { | |
162 | .name = "NV15", | |
46484438 | 163 | .bios = nvkm_bios_new, |
bb23f9d7 | 164 | .bus = nv04_bus_new, |
6625f55c | 165 | .clk = nv04_clk_new, |
151abd44 | 166 | .devinit = nv10_devinit_new, |
03c8952f | 167 | .fb = nv10_fb_new, |
2ea7249f | 168 | .gpio = nv10_gpio_new, |
49bd8da5 | 169 | .i2c = nv04_i2c_new, |
b7a2bc18 | 170 | .imem = nv04_instmem_new, |
54dcadd5 | 171 | .mc = nv04_mc_new, |
c9582455 | 172 | .mmu = nv04_mmu_new, |
0a34fb31 | 173 | .pci = nv04_pci_new, |
31649ecf | 174 | .timer = nv04_timer_new, |
70aa8670 | 175 | .disp = nv04_disp_new, |
bd70563f | 176 | .dma = nv04_dma_new, |
13de7f46 | 177 | .fifo = nv10_fifo_new, |
c85ee6ca | 178 | .gr = nv15_gr_new, |
6f41c7c5 | 179 | .sw = nv10_sw_new, |
6cf813fb BS |
180 | }; |
181 | ||
182 | static const struct nvkm_device_chip | |
183 | nv17_chipset = { | |
184 | .name = "NV17", | |
46484438 | 185 | .bios = nvkm_bios_new, |
bb23f9d7 | 186 | .bus = nv04_bus_new, |
6625f55c | 187 | .clk = nv04_clk_new, |
151abd44 | 188 | .devinit = nv10_devinit_new, |
03c8952f | 189 | .fb = nv10_fb_new, |
2ea7249f | 190 | .gpio = nv10_gpio_new, |
49bd8da5 | 191 | .i2c = nv04_i2c_new, |
b7a2bc18 | 192 | .imem = nv04_instmem_new, |
79360b7d | 193 | .mc = nv17_mc_new, |
c9582455 | 194 | .mmu = nv04_mmu_new, |
0a34fb31 | 195 | .pci = nv04_pci_new, |
31649ecf | 196 | .timer = nv04_timer_new, |
70aa8670 | 197 | .disp = nv04_disp_new, |
bd70563f | 198 | .dma = nv04_dma_new, |
13de7f46 | 199 | .fifo = nv17_fifo_new, |
c85ee6ca | 200 | .gr = nv17_gr_new, |
6f41c7c5 | 201 | .sw = nv10_sw_new, |
6cf813fb BS |
202 | }; |
203 | ||
204 | static const struct nvkm_device_chip | |
205 | nv18_chipset = { | |
206 | .name = "NV18", | |
46484438 | 207 | .bios = nvkm_bios_new, |
bb23f9d7 | 208 | .bus = nv04_bus_new, |
6625f55c | 209 | .clk = nv04_clk_new, |
151abd44 | 210 | .devinit = nv10_devinit_new, |
03c8952f | 211 | .fb = nv10_fb_new, |
2ea7249f | 212 | .gpio = nv10_gpio_new, |
49bd8da5 | 213 | .i2c = nv04_i2c_new, |
b7a2bc18 | 214 | .imem = nv04_instmem_new, |
79360b7d | 215 | .mc = nv17_mc_new, |
c9582455 | 216 | .mmu = nv04_mmu_new, |
0a34fb31 | 217 | .pci = nv04_pci_new, |
31649ecf | 218 | .timer = nv04_timer_new, |
70aa8670 | 219 | .disp = nv04_disp_new, |
bd70563f | 220 | .dma = nv04_dma_new, |
13de7f46 | 221 | .fifo = nv17_fifo_new, |
c85ee6ca | 222 | .gr = nv17_gr_new, |
6f41c7c5 | 223 | .sw = nv10_sw_new, |
6cf813fb BS |
224 | }; |
225 | ||
226 | static const struct nvkm_device_chip | |
227 | nv1a_chipset = { | |
228 | .name = "nForce", | |
46484438 | 229 | .bios = nvkm_bios_new, |
bb23f9d7 | 230 | .bus = nv04_bus_new, |
6625f55c | 231 | .clk = nv04_clk_new, |
151abd44 | 232 | .devinit = nv1a_devinit_new, |
03c8952f | 233 | .fb = nv1a_fb_new, |
2ea7249f | 234 | .gpio = nv10_gpio_new, |
49bd8da5 | 235 | .i2c = nv04_i2c_new, |
b7a2bc18 | 236 | .imem = nv04_instmem_new, |
54dcadd5 | 237 | .mc = nv04_mc_new, |
c9582455 | 238 | .mmu = nv04_mmu_new, |
0a34fb31 | 239 | .pci = nv04_pci_new, |
31649ecf | 240 | .timer = nv04_timer_new, |
70aa8670 | 241 | .disp = nv04_disp_new, |
bd70563f | 242 | .dma = nv04_dma_new, |
13de7f46 | 243 | .fifo = nv10_fifo_new, |
c85ee6ca | 244 | .gr = nv15_gr_new, |
6f41c7c5 | 245 | .sw = nv10_sw_new, |
6cf813fb BS |
246 | }; |
247 | ||
248 | static const struct nvkm_device_chip | |
249 | nv1f_chipset = { | |
250 | .name = "nForce2", | |
46484438 | 251 | .bios = nvkm_bios_new, |
bb23f9d7 | 252 | .bus = nv04_bus_new, |
6625f55c | 253 | .clk = nv04_clk_new, |
151abd44 | 254 | .devinit = nv1a_devinit_new, |
03c8952f | 255 | .fb = nv1a_fb_new, |
2ea7249f | 256 | .gpio = nv10_gpio_new, |
49bd8da5 | 257 | .i2c = nv04_i2c_new, |
b7a2bc18 | 258 | .imem = nv04_instmem_new, |
79360b7d | 259 | .mc = nv17_mc_new, |
c9582455 | 260 | .mmu = nv04_mmu_new, |
0a34fb31 | 261 | .pci = nv04_pci_new, |
31649ecf | 262 | .timer = nv04_timer_new, |
70aa8670 | 263 | .disp = nv04_disp_new, |
bd70563f | 264 | .dma = nv04_dma_new, |
13de7f46 | 265 | .fifo = nv17_fifo_new, |
c85ee6ca | 266 | .gr = nv17_gr_new, |
6f41c7c5 | 267 | .sw = nv10_sw_new, |
6cf813fb BS |
268 | }; |
269 | ||
270 | static const struct nvkm_device_chip | |
271 | nv20_chipset = { | |
272 | .name = "NV20", | |
46484438 | 273 | .bios = nvkm_bios_new, |
bb23f9d7 | 274 | .bus = nv04_bus_new, |
6625f55c | 275 | .clk = nv04_clk_new, |
151abd44 | 276 | .devinit = nv20_devinit_new, |
03c8952f | 277 | .fb = nv20_fb_new, |
2ea7249f | 278 | .gpio = nv10_gpio_new, |
49bd8da5 | 279 | .i2c = nv04_i2c_new, |
b7a2bc18 | 280 | .imem = nv04_instmem_new, |
79360b7d | 281 | .mc = nv17_mc_new, |
c9582455 | 282 | .mmu = nv04_mmu_new, |
0a34fb31 | 283 | .pci = nv04_pci_new, |
31649ecf | 284 | .timer = nv04_timer_new, |
70aa8670 | 285 | .disp = nv04_disp_new, |
bd70563f | 286 | .dma = nv04_dma_new, |
13de7f46 | 287 | .fifo = nv17_fifo_new, |
c85ee6ca | 288 | .gr = nv20_gr_new, |
6f41c7c5 | 289 | .sw = nv10_sw_new, |
6cf813fb BS |
290 | }; |
291 | ||
292 | static const struct nvkm_device_chip | |
293 | nv25_chipset = { | |
294 | .name = "NV25", | |
46484438 | 295 | .bios = nvkm_bios_new, |
bb23f9d7 | 296 | .bus = nv04_bus_new, |
6625f55c | 297 | .clk = nv04_clk_new, |
151abd44 | 298 | .devinit = nv20_devinit_new, |
03c8952f | 299 | .fb = nv25_fb_new, |
2ea7249f | 300 | .gpio = nv10_gpio_new, |
49bd8da5 | 301 | .i2c = nv04_i2c_new, |
b7a2bc18 | 302 | .imem = nv04_instmem_new, |
79360b7d | 303 | .mc = nv17_mc_new, |
c9582455 | 304 | .mmu = nv04_mmu_new, |
0a34fb31 | 305 | .pci = nv04_pci_new, |
31649ecf | 306 | .timer = nv04_timer_new, |
70aa8670 | 307 | .disp = nv04_disp_new, |
bd70563f | 308 | .dma = nv04_dma_new, |
13de7f46 | 309 | .fifo = nv17_fifo_new, |
c85ee6ca | 310 | .gr = nv25_gr_new, |
6f41c7c5 | 311 | .sw = nv10_sw_new, |
6cf813fb BS |
312 | }; |
313 | ||
314 | static const struct nvkm_device_chip | |
315 | nv28_chipset = { | |
316 | .name = "NV28", | |
46484438 | 317 | .bios = nvkm_bios_new, |
bb23f9d7 | 318 | .bus = nv04_bus_new, |
6625f55c | 319 | .clk = nv04_clk_new, |
151abd44 | 320 | .devinit = nv20_devinit_new, |
03c8952f | 321 | .fb = nv25_fb_new, |
2ea7249f | 322 | .gpio = nv10_gpio_new, |
49bd8da5 | 323 | .i2c = nv04_i2c_new, |
b7a2bc18 | 324 | .imem = nv04_instmem_new, |
79360b7d | 325 | .mc = nv17_mc_new, |
c9582455 | 326 | .mmu = nv04_mmu_new, |
0a34fb31 | 327 | .pci = nv04_pci_new, |
31649ecf | 328 | .timer = nv04_timer_new, |
70aa8670 | 329 | .disp = nv04_disp_new, |
bd70563f | 330 | .dma = nv04_dma_new, |
13de7f46 | 331 | .fifo = nv17_fifo_new, |
c85ee6ca | 332 | .gr = nv25_gr_new, |
6f41c7c5 | 333 | .sw = nv10_sw_new, |
6cf813fb BS |
334 | }; |
335 | ||
336 | static const struct nvkm_device_chip | |
337 | nv2a_chipset = { | |
338 | .name = "NV2A", | |
46484438 | 339 | .bios = nvkm_bios_new, |
bb23f9d7 | 340 | .bus = nv04_bus_new, |
6625f55c | 341 | .clk = nv04_clk_new, |
151abd44 | 342 | .devinit = nv20_devinit_new, |
03c8952f | 343 | .fb = nv25_fb_new, |
2ea7249f | 344 | .gpio = nv10_gpio_new, |
49bd8da5 | 345 | .i2c = nv04_i2c_new, |
b7a2bc18 | 346 | .imem = nv04_instmem_new, |
79360b7d | 347 | .mc = nv17_mc_new, |
c9582455 | 348 | .mmu = nv04_mmu_new, |
0a34fb31 | 349 | .pci = nv04_pci_new, |
31649ecf | 350 | .timer = nv04_timer_new, |
70aa8670 | 351 | .disp = nv04_disp_new, |
bd70563f | 352 | .dma = nv04_dma_new, |
13de7f46 | 353 | .fifo = nv17_fifo_new, |
c85ee6ca | 354 | .gr = nv2a_gr_new, |
6f41c7c5 | 355 | .sw = nv10_sw_new, |
6cf813fb BS |
356 | }; |
357 | ||
358 | static const struct nvkm_device_chip | |
359 | nv30_chipset = { | |
360 | .name = "NV30", | |
46484438 | 361 | .bios = nvkm_bios_new, |
bb23f9d7 | 362 | .bus = nv04_bus_new, |
6625f55c | 363 | .clk = nv04_clk_new, |
151abd44 | 364 | .devinit = nv20_devinit_new, |
03c8952f | 365 | .fb = nv30_fb_new, |
2ea7249f | 366 | .gpio = nv10_gpio_new, |
49bd8da5 | 367 | .i2c = nv04_i2c_new, |
b7a2bc18 | 368 | .imem = nv04_instmem_new, |
79360b7d | 369 | .mc = nv17_mc_new, |
c9582455 | 370 | .mmu = nv04_mmu_new, |
0a34fb31 | 371 | .pci = nv04_pci_new, |
31649ecf | 372 | .timer = nv04_timer_new, |
70aa8670 | 373 | .disp = nv04_disp_new, |
bd70563f | 374 | .dma = nv04_dma_new, |
13de7f46 | 375 | .fifo = nv17_fifo_new, |
c85ee6ca | 376 | .gr = nv30_gr_new, |
6f41c7c5 | 377 | .sw = nv10_sw_new, |
6cf813fb BS |
378 | }; |
379 | ||
380 | static const struct nvkm_device_chip | |
381 | nv31_chipset = { | |
382 | .name = "NV31", | |
46484438 | 383 | .bios = nvkm_bios_new, |
bb23f9d7 | 384 | .bus = nv31_bus_new, |
6625f55c | 385 | .clk = nv04_clk_new, |
151abd44 | 386 | .devinit = nv20_devinit_new, |
03c8952f | 387 | .fb = nv30_fb_new, |
2ea7249f | 388 | .gpio = nv10_gpio_new, |
49bd8da5 | 389 | .i2c = nv04_i2c_new, |
b7a2bc18 | 390 | .imem = nv04_instmem_new, |
79360b7d | 391 | .mc = nv17_mc_new, |
c9582455 | 392 | .mmu = nv04_mmu_new, |
0a34fb31 | 393 | .pci = nv04_pci_new, |
31649ecf | 394 | .timer = nv04_timer_new, |
70aa8670 | 395 | .disp = nv04_disp_new, |
bd70563f | 396 | .dma = nv04_dma_new, |
13de7f46 | 397 | .fifo = nv17_fifo_new, |
c85ee6ca | 398 | .gr = nv30_gr_new, |
7624fc01 | 399 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 400 | .sw = nv10_sw_new, |
6cf813fb BS |
401 | }; |
402 | ||
403 | static const struct nvkm_device_chip | |
404 | nv34_chipset = { | |
405 | .name = "NV34", | |
46484438 | 406 | .bios = nvkm_bios_new, |
bb23f9d7 | 407 | .bus = nv31_bus_new, |
6625f55c | 408 | .clk = nv04_clk_new, |
151abd44 | 409 | .devinit = nv10_devinit_new, |
03c8952f | 410 | .fb = nv10_fb_new, |
2ea7249f | 411 | .gpio = nv10_gpio_new, |
49bd8da5 | 412 | .i2c = nv04_i2c_new, |
b7a2bc18 | 413 | .imem = nv04_instmem_new, |
79360b7d | 414 | .mc = nv17_mc_new, |
c9582455 | 415 | .mmu = nv04_mmu_new, |
0a34fb31 | 416 | .pci = nv04_pci_new, |
31649ecf | 417 | .timer = nv04_timer_new, |
70aa8670 | 418 | .disp = nv04_disp_new, |
bd70563f | 419 | .dma = nv04_dma_new, |
13de7f46 | 420 | .fifo = nv17_fifo_new, |
c85ee6ca | 421 | .gr = nv34_gr_new, |
7624fc01 | 422 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 423 | .sw = nv10_sw_new, |
6cf813fb BS |
424 | }; |
425 | ||
426 | static const struct nvkm_device_chip | |
427 | nv35_chipset = { | |
428 | .name = "NV35", | |
46484438 | 429 | .bios = nvkm_bios_new, |
bb23f9d7 | 430 | .bus = nv04_bus_new, |
6625f55c | 431 | .clk = nv04_clk_new, |
151abd44 | 432 | .devinit = nv20_devinit_new, |
03c8952f | 433 | .fb = nv35_fb_new, |
2ea7249f | 434 | .gpio = nv10_gpio_new, |
49bd8da5 | 435 | .i2c = nv04_i2c_new, |
b7a2bc18 | 436 | .imem = nv04_instmem_new, |
79360b7d | 437 | .mc = nv17_mc_new, |
c9582455 | 438 | .mmu = nv04_mmu_new, |
0a34fb31 | 439 | .pci = nv04_pci_new, |
31649ecf | 440 | .timer = nv04_timer_new, |
70aa8670 | 441 | .disp = nv04_disp_new, |
bd70563f | 442 | .dma = nv04_dma_new, |
13de7f46 | 443 | .fifo = nv17_fifo_new, |
c85ee6ca | 444 | .gr = nv35_gr_new, |
6f41c7c5 | 445 | .sw = nv10_sw_new, |
6cf813fb BS |
446 | }; |
447 | ||
448 | static const struct nvkm_device_chip | |
449 | nv36_chipset = { | |
450 | .name = "NV36", | |
46484438 | 451 | .bios = nvkm_bios_new, |
bb23f9d7 | 452 | .bus = nv31_bus_new, |
6625f55c | 453 | .clk = nv04_clk_new, |
151abd44 | 454 | .devinit = nv20_devinit_new, |
03c8952f | 455 | .fb = nv36_fb_new, |
2ea7249f | 456 | .gpio = nv10_gpio_new, |
49bd8da5 | 457 | .i2c = nv04_i2c_new, |
b7a2bc18 | 458 | .imem = nv04_instmem_new, |
79360b7d | 459 | .mc = nv17_mc_new, |
c9582455 | 460 | .mmu = nv04_mmu_new, |
0a34fb31 | 461 | .pci = nv04_pci_new, |
31649ecf | 462 | .timer = nv04_timer_new, |
70aa8670 | 463 | .disp = nv04_disp_new, |
bd70563f | 464 | .dma = nv04_dma_new, |
13de7f46 | 465 | .fifo = nv17_fifo_new, |
c85ee6ca | 466 | .gr = nv35_gr_new, |
7624fc01 | 467 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 468 | .sw = nv10_sw_new, |
6cf813fb BS |
469 | }; |
470 | ||
471 | static const struct nvkm_device_chip | |
472 | nv40_chipset = { | |
473 | .name = "NV40", | |
46484438 | 474 | .bios = nvkm_bios_new, |
bb23f9d7 | 475 | .bus = nv31_bus_new, |
6625f55c | 476 | .clk = nv40_clk_new, |
151abd44 | 477 | .devinit = nv1a_devinit_new, |
03c8952f | 478 | .fb = nv40_fb_new, |
2ea7249f | 479 | .gpio = nv10_gpio_new, |
49bd8da5 | 480 | .i2c = nv04_i2c_new, |
b7a2bc18 | 481 | .imem = nv40_instmem_new, |
79360b7d | 482 | .mc = nv17_mc_new, |
c9582455 | 483 | .mmu = nv04_mmu_new, |
0a34fb31 | 484 | .pci = nv40_pci_new, |
57113c01 | 485 | .therm = nv40_therm_new, |
31649ecf | 486 | .timer = nv40_timer_new, |
437b2296 | 487 | .volt = nv40_volt_new, |
70aa8670 | 488 | .disp = nv04_disp_new, |
bd70563f | 489 | .dma = nv04_dma_new, |
13de7f46 | 490 | .fifo = nv40_fifo_new, |
c85ee6ca | 491 | .gr = nv40_gr_new, |
7624fc01 | 492 | .mpeg = nv40_mpeg_new, |
97070f23 | 493 | .pm = nv40_pm_new, |
6f41c7c5 | 494 | .sw = nv10_sw_new, |
6cf813fb BS |
495 | }; |
496 | ||
497 | static const struct nvkm_device_chip | |
498 | nv41_chipset = { | |
499 | .name = "NV41", | |
46484438 | 500 | .bios = nvkm_bios_new, |
bb23f9d7 | 501 | .bus = nv31_bus_new, |
6625f55c | 502 | .clk = nv40_clk_new, |
151abd44 | 503 | .devinit = nv1a_devinit_new, |
03c8952f | 504 | .fb = nv41_fb_new, |
2ea7249f | 505 | .gpio = nv10_gpio_new, |
49bd8da5 | 506 | .i2c = nv04_i2c_new, |
b7a2bc18 | 507 | .imem = nv40_instmem_new, |
79360b7d | 508 | .mc = nv17_mc_new, |
c9582455 | 509 | .mmu = nv41_mmu_new, |
0a34fb31 | 510 | .pci = nv40_pci_new, |
57113c01 | 511 | .therm = nv40_therm_new, |
31649ecf | 512 | .timer = nv41_timer_new, |
437b2296 | 513 | .volt = nv40_volt_new, |
70aa8670 | 514 | .disp = nv04_disp_new, |
bd70563f | 515 | .dma = nv04_dma_new, |
13de7f46 | 516 | .fifo = nv40_fifo_new, |
c85ee6ca | 517 | .gr = nv40_gr_new, |
7624fc01 | 518 | .mpeg = nv40_mpeg_new, |
97070f23 | 519 | .pm = nv40_pm_new, |
6f41c7c5 | 520 | .sw = nv10_sw_new, |
6cf813fb BS |
521 | }; |
522 | ||
523 | static const struct nvkm_device_chip | |
524 | nv42_chipset = { | |
525 | .name = "NV42", | |
46484438 | 526 | .bios = nvkm_bios_new, |
bb23f9d7 | 527 | .bus = nv31_bus_new, |
6625f55c | 528 | .clk = nv40_clk_new, |
151abd44 | 529 | .devinit = nv1a_devinit_new, |
03c8952f | 530 | .fb = nv41_fb_new, |
2ea7249f | 531 | .gpio = nv10_gpio_new, |
49bd8da5 | 532 | .i2c = nv04_i2c_new, |
b7a2bc18 | 533 | .imem = nv40_instmem_new, |
79360b7d | 534 | .mc = nv17_mc_new, |
c9582455 | 535 | .mmu = nv41_mmu_new, |
0a34fb31 | 536 | .pci = nv40_pci_new, |
57113c01 | 537 | .therm = nv40_therm_new, |
31649ecf | 538 | .timer = nv41_timer_new, |
437b2296 | 539 | .volt = nv40_volt_new, |
70aa8670 | 540 | .disp = nv04_disp_new, |
bd70563f | 541 | .dma = nv04_dma_new, |
13de7f46 | 542 | .fifo = nv40_fifo_new, |
c85ee6ca | 543 | .gr = nv40_gr_new, |
7624fc01 | 544 | .mpeg = nv40_mpeg_new, |
97070f23 | 545 | .pm = nv40_pm_new, |
6f41c7c5 | 546 | .sw = nv10_sw_new, |
6cf813fb BS |
547 | }; |
548 | ||
549 | static const struct nvkm_device_chip | |
550 | nv43_chipset = { | |
551 | .name = "NV43", | |
46484438 | 552 | .bios = nvkm_bios_new, |
bb23f9d7 | 553 | .bus = nv31_bus_new, |
6625f55c | 554 | .clk = nv40_clk_new, |
151abd44 | 555 | .devinit = nv1a_devinit_new, |
03c8952f | 556 | .fb = nv41_fb_new, |
2ea7249f | 557 | .gpio = nv10_gpio_new, |
49bd8da5 | 558 | .i2c = nv04_i2c_new, |
b7a2bc18 | 559 | .imem = nv40_instmem_new, |
79360b7d | 560 | .mc = nv17_mc_new, |
c9582455 | 561 | .mmu = nv41_mmu_new, |
0a34fb31 | 562 | .pci = nv40_pci_new, |
57113c01 | 563 | .therm = nv40_therm_new, |
31649ecf | 564 | .timer = nv41_timer_new, |
437b2296 | 565 | .volt = nv40_volt_new, |
70aa8670 | 566 | .disp = nv04_disp_new, |
bd70563f | 567 | .dma = nv04_dma_new, |
13de7f46 | 568 | .fifo = nv40_fifo_new, |
c85ee6ca | 569 | .gr = nv40_gr_new, |
7624fc01 | 570 | .mpeg = nv40_mpeg_new, |
97070f23 | 571 | .pm = nv40_pm_new, |
6f41c7c5 | 572 | .sw = nv10_sw_new, |
6cf813fb BS |
573 | }; |
574 | ||
575 | static const struct nvkm_device_chip | |
576 | nv44_chipset = { | |
577 | .name = "NV44", | |
46484438 | 578 | .bios = nvkm_bios_new, |
bb23f9d7 | 579 | .bus = nv31_bus_new, |
6625f55c | 580 | .clk = nv40_clk_new, |
151abd44 | 581 | .devinit = nv1a_devinit_new, |
03c8952f | 582 | .fb = nv44_fb_new, |
2ea7249f | 583 | .gpio = nv10_gpio_new, |
49bd8da5 | 584 | .i2c = nv04_i2c_new, |
b7a2bc18 | 585 | .imem = nv40_instmem_new, |
54dcadd5 | 586 | .mc = nv44_mc_new, |
c9582455 | 587 | .mmu = nv44_mmu_new, |
0a34fb31 | 588 | .pci = nv40_pci_new, |
57113c01 | 589 | .therm = nv40_therm_new, |
31649ecf | 590 | .timer = nv41_timer_new, |
437b2296 | 591 | .volt = nv40_volt_new, |
70aa8670 | 592 | .disp = nv04_disp_new, |
bd70563f | 593 | .dma = nv04_dma_new, |
13de7f46 | 594 | .fifo = nv40_fifo_new, |
c85ee6ca | 595 | .gr = nv44_gr_new, |
7624fc01 | 596 | .mpeg = nv44_mpeg_new, |
97070f23 | 597 | .pm = nv40_pm_new, |
6f41c7c5 | 598 | .sw = nv10_sw_new, |
6cf813fb BS |
599 | }; |
600 | ||
601 | static const struct nvkm_device_chip | |
602 | nv45_chipset = { | |
603 | .name = "NV45", | |
46484438 | 604 | .bios = nvkm_bios_new, |
bb23f9d7 | 605 | .bus = nv31_bus_new, |
6625f55c | 606 | .clk = nv40_clk_new, |
151abd44 | 607 | .devinit = nv1a_devinit_new, |
03c8952f | 608 | .fb = nv40_fb_new, |
2ea7249f | 609 | .gpio = nv10_gpio_new, |
49bd8da5 | 610 | .i2c = nv04_i2c_new, |
b7a2bc18 | 611 | .imem = nv40_instmem_new, |
79360b7d | 612 | .mc = nv17_mc_new, |
c9582455 | 613 | .mmu = nv04_mmu_new, |
0a34fb31 | 614 | .pci = nv40_pci_new, |
57113c01 | 615 | .therm = nv40_therm_new, |
31649ecf | 616 | .timer = nv41_timer_new, |
437b2296 | 617 | .volt = nv40_volt_new, |
70aa8670 | 618 | .disp = nv04_disp_new, |
bd70563f | 619 | .dma = nv04_dma_new, |
13de7f46 | 620 | .fifo = nv40_fifo_new, |
c85ee6ca | 621 | .gr = nv40_gr_new, |
7624fc01 | 622 | .mpeg = nv44_mpeg_new, |
97070f23 | 623 | .pm = nv40_pm_new, |
6f41c7c5 | 624 | .sw = nv10_sw_new, |
6cf813fb BS |
625 | }; |
626 | ||
627 | static const struct nvkm_device_chip | |
628 | nv46_chipset = { | |
629 | .name = "G72", | |
46484438 | 630 | .bios = nvkm_bios_new, |
bb23f9d7 | 631 | .bus = nv31_bus_new, |
6625f55c | 632 | .clk = nv40_clk_new, |
151abd44 | 633 | .devinit = nv1a_devinit_new, |
03c8952f | 634 | .fb = nv46_fb_new, |
2ea7249f | 635 | .gpio = nv10_gpio_new, |
49bd8da5 | 636 | .i2c = nv04_i2c_new, |
b7a2bc18 | 637 | .imem = nv40_instmem_new, |
54dcadd5 | 638 | .mc = nv44_mc_new, |
c9582455 | 639 | .mmu = nv44_mmu_new, |
c4266a9c | 640 | .pci = nv46_pci_new, |
57113c01 | 641 | .therm = nv40_therm_new, |
31649ecf | 642 | .timer = nv41_timer_new, |
437b2296 | 643 | .volt = nv40_volt_new, |
70aa8670 | 644 | .disp = nv04_disp_new, |
bd70563f | 645 | .dma = nv04_dma_new, |
13de7f46 | 646 | .fifo = nv40_fifo_new, |
c85ee6ca | 647 | .gr = nv44_gr_new, |
7624fc01 | 648 | .mpeg = nv44_mpeg_new, |
97070f23 | 649 | .pm = nv40_pm_new, |
6f41c7c5 | 650 | .sw = nv10_sw_new, |
6cf813fb BS |
651 | }; |
652 | ||
653 | static const struct nvkm_device_chip | |
654 | nv47_chipset = { | |
655 | .name = "G70", | |
46484438 | 656 | .bios = nvkm_bios_new, |
bb23f9d7 | 657 | .bus = nv31_bus_new, |
6625f55c | 658 | .clk = nv40_clk_new, |
151abd44 | 659 | .devinit = nv1a_devinit_new, |
03c8952f | 660 | .fb = nv47_fb_new, |
2ea7249f | 661 | .gpio = nv10_gpio_new, |
49bd8da5 | 662 | .i2c = nv04_i2c_new, |
b7a2bc18 | 663 | .imem = nv40_instmem_new, |
79360b7d | 664 | .mc = nv17_mc_new, |
c9582455 | 665 | .mmu = nv41_mmu_new, |
0a34fb31 | 666 | .pci = nv40_pci_new, |
57113c01 | 667 | .therm = nv40_therm_new, |
31649ecf | 668 | .timer = nv41_timer_new, |
437b2296 | 669 | .volt = nv40_volt_new, |
70aa8670 | 670 | .disp = nv04_disp_new, |
bd70563f | 671 | .dma = nv04_dma_new, |
13de7f46 | 672 | .fifo = nv40_fifo_new, |
c85ee6ca | 673 | .gr = nv40_gr_new, |
7624fc01 | 674 | .mpeg = nv44_mpeg_new, |
97070f23 | 675 | .pm = nv40_pm_new, |
6f41c7c5 | 676 | .sw = nv10_sw_new, |
6cf813fb BS |
677 | }; |
678 | ||
679 | static const struct nvkm_device_chip | |
680 | nv49_chipset = { | |
681 | .name = "G71", | |
46484438 | 682 | .bios = nvkm_bios_new, |
bb23f9d7 | 683 | .bus = nv31_bus_new, |
6625f55c | 684 | .clk = nv40_clk_new, |
151abd44 | 685 | .devinit = nv1a_devinit_new, |
03c8952f | 686 | .fb = nv49_fb_new, |
2ea7249f | 687 | .gpio = nv10_gpio_new, |
49bd8da5 | 688 | .i2c = nv04_i2c_new, |
b7a2bc18 | 689 | .imem = nv40_instmem_new, |
79360b7d | 690 | .mc = nv17_mc_new, |
c9582455 | 691 | .mmu = nv41_mmu_new, |
0a34fb31 | 692 | .pci = nv40_pci_new, |
57113c01 | 693 | .therm = nv40_therm_new, |
31649ecf | 694 | .timer = nv41_timer_new, |
437b2296 | 695 | .volt = nv40_volt_new, |
70aa8670 | 696 | .disp = nv04_disp_new, |
bd70563f | 697 | .dma = nv04_dma_new, |
13de7f46 | 698 | .fifo = nv40_fifo_new, |
c85ee6ca | 699 | .gr = nv40_gr_new, |
7624fc01 | 700 | .mpeg = nv44_mpeg_new, |
97070f23 | 701 | .pm = nv40_pm_new, |
6f41c7c5 | 702 | .sw = nv10_sw_new, |
6cf813fb BS |
703 | }; |
704 | ||
705 | static const struct nvkm_device_chip | |
706 | nv4a_chipset = { | |
707 | .name = "NV44A", | |
46484438 | 708 | .bios = nvkm_bios_new, |
bb23f9d7 | 709 | .bus = nv31_bus_new, |
6625f55c | 710 | .clk = nv40_clk_new, |
151abd44 | 711 | .devinit = nv1a_devinit_new, |
03c8952f | 712 | .fb = nv44_fb_new, |
2ea7249f | 713 | .gpio = nv10_gpio_new, |
49bd8da5 | 714 | .i2c = nv04_i2c_new, |
b7a2bc18 | 715 | .imem = nv40_instmem_new, |
54dcadd5 | 716 | .mc = nv44_mc_new, |
c9582455 | 717 | .mmu = nv44_mmu_new, |
0a34fb31 | 718 | .pci = nv40_pci_new, |
57113c01 | 719 | .therm = nv40_therm_new, |
31649ecf | 720 | .timer = nv41_timer_new, |
437b2296 | 721 | .volt = nv40_volt_new, |
70aa8670 | 722 | .disp = nv04_disp_new, |
bd70563f | 723 | .dma = nv04_dma_new, |
13de7f46 | 724 | .fifo = nv40_fifo_new, |
c85ee6ca | 725 | .gr = nv44_gr_new, |
7624fc01 | 726 | .mpeg = nv44_mpeg_new, |
97070f23 | 727 | .pm = nv40_pm_new, |
6f41c7c5 | 728 | .sw = nv10_sw_new, |
6cf813fb BS |
729 | }; |
730 | ||
731 | static const struct nvkm_device_chip | |
732 | nv4b_chipset = { | |
733 | .name = "G73", | |
46484438 | 734 | .bios = nvkm_bios_new, |
bb23f9d7 | 735 | .bus = nv31_bus_new, |
6625f55c | 736 | .clk = nv40_clk_new, |
151abd44 | 737 | .devinit = nv1a_devinit_new, |
03c8952f | 738 | .fb = nv49_fb_new, |
2ea7249f | 739 | .gpio = nv10_gpio_new, |
49bd8da5 | 740 | .i2c = nv04_i2c_new, |
b7a2bc18 | 741 | .imem = nv40_instmem_new, |
79360b7d | 742 | .mc = nv17_mc_new, |
c9582455 | 743 | .mmu = nv41_mmu_new, |
0a34fb31 | 744 | .pci = nv40_pci_new, |
57113c01 | 745 | .therm = nv40_therm_new, |
31649ecf | 746 | .timer = nv41_timer_new, |
437b2296 | 747 | .volt = nv40_volt_new, |
70aa8670 | 748 | .disp = nv04_disp_new, |
bd70563f | 749 | .dma = nv04_dma_new, |
13de7f46 | 750 | .fifo = nv40_fifo_new, |
c85ee6ca | 751 | .gr = nv40_gr_new, |
7624fc01 | 752 | .mpeg = nv44_mpeg_new, |
97070f23 | 753 | .pm = nv40_pm_new, |
6f41c7c5 | 754 | .sw = nv10_sw_new, |
6cf813fb BS |
755 | }; |
756 | ||
757 | static const struct nvkm_device_chip | |
758 | nv4c_chipset = { | |
759 | .name = "C61", | |
46484438 | 760 | .bios = nvkm_bios_new, |
bb23f9d7 | 761 | .bus = nv31_bus_new, |
6625f55c | 762 | .clk = nv40_clk_new, |
151abd44 | 763 | .devinit = nv1a_devinit_new, |
03c8952f | 764 | .fb = nv46_fb_new, |
2ea7249f | 765 | .gpio = nv10_gpio_new, |
49bd8da5 | 766 | .i2c = nv04_i2c_new, |
b7a2bc18 | 767 | .imem = nv40_instmem_new, |
2b700825 | 768 | .mc = nv44_mc_new, |
c9582455 | 769 | .mmu = nv44_mmu_new, |
0a34fb31 | 770 | .pci = nv4c_pci_new, |
57113c01 | 771 | .therm = nv40_therm_new, |
31649ecf | 772 | .timer = nv41_timer_new, |
437b2296 | 773 | .volt = nv40_volt_new, |
70aa8670 | 774 | .disp = nv04_disp_new, |
bd70563f | 775 | .dma = nv04_dma_new, |
13de7f46 | 776 | .fifo = nv40_fifo_new, |
c85ee6ca | 777 | .gr = nv44_gr_new, |
7624fc01 | 778 | .mpeg = nv44_mpeg_new, |
97070f23 | 779 | .pm = nv40_pm_new, |
6f41c7c5 | 780 | .sw = nv10_sw_new, |
6cf813fb BS |
781 | }; |
782 | ||
783 | static const struct nvkm_device_chip | |
784 | nv4e_chipset = { | |
785 | .name = "C51", | |
46484438 | 786 | .bios = nvkm_bios_new, |
bb23f9d7 | 787 | .bus = nv31_bus_new, |
6625f55c | 788 | .clk = nv40_clk_new, |
151abd44 | 789 | .devinit = nv1a_devinit_new, |
03c8952f | 790 | .fb = nv4e_fb_new, |
2ea7249f | 791 | .gpio = nv10_gpio_new, |
49bd8da5 | 792 | .i2c = nv4e_i2c_new, |
b7a2bc18 | 793 | .imem = nv40_instmem_new, |
2b700825 | 794 | .mc = nv44_mc_new, |
c9582455 | 795 | .mmu = nv44_mmu_new, |
0a34fb31 | 796 | .pci = nv4c_pci_new, |
57113c01 | 797 | .therm = nv40_therm_new, |
31649ecf | 798 | .timer = nv41_timer_new, |
437b2296 | 799 | .volt = nv40_volt_new, |
70aa8670 | 800 | .disp = nv04_disp_new, |
bd70563f | 801 | .dma = nv04_dma_new, |
13de7f46 | 802 | .fifo = nv40_fifo_new, |
c85ee6ca | 803 | .gr = nv44_gr_new, |
7624fc01 | 804 | .mpeg = nv44_mpeg_new, |
97070f23 | 805 | .pm = nv40_pm_new, |
6f41c7c5 | 806 | .sw = nv10_sw_new, |
6cf813fb BS |
807 | }; |
808 | ||
809 | static const struct nvkm_device_chip | |
810 | nv50_chipset = { | |
811 | .name = "G80", | |
32932281 | 812 | .bar = nv50_bar_new, |
46484438 | 813 | .bios = nvkm_bios_new, |
bb23f9d7 | 814 | .bus = nv50_bus_new, |
6625f55c | 815 | .clk = nv50_clk_new, |
151abd44 | 816 | .devinit = nv50_devinit_new, |
03c8952f | 817 | .fb = nv50_fb_new, |
c5fcafa5 | 818 | .fuse = nv50_fuse_new, |
2ea7249f | 819 | .gpio = nv50_gpio_new, |
49bd8da5 | 820 | .i2c = nv50_i2c_new, |
b7a2bc18 | 821 | .imem = nv50_instmem_new, |
54dcadd5 | 822 | .mc = nv50_mc_new, |
c9582455 | 823 | .mmu = nv50_mmu_new, |
a4f7bd36 | 824 | .mxm = nv50_mxm_new, |
c4266a9c | 825 | .pci = nv46_pci_new, |
57113c01 | 826 | .therm = nv50_therm_new, |
31649ecf | 827 | .timer = nv41_timer_new, |
437b2296 | 828 | .volt = nv40_volt_new, |
70aa8670 | 829 | .disp = nv50_disp_new, |
bd70563f | 830 | .dma = nv50_dma_new, |
13de7f46 | 831 | .fifo = nv50_fifo_new, |
c85ee6ca | 832 | .gr = nv50_gr_new, |
7624fc01 | 833 | .mpeg = nv50_mpeg_new, |
97070f23 | 834 | .pm = nv50_pm_new, |
6f41c7c5 | 835 | .sw = nv50_sw_new, |
6cf813fb BS |
836 | }; |
837 | ||
838 | static const struct nvkm_device_chip | |
839 | nv63_chipset = { | |
840 | .name = "C73", | |
46484438 | 841 | .bios = nvkm_bios_new, |
bb23f9d7 | 842 | .bus = nv31_bus_new, |
6625f55c | 843 | .clk = nv40_clk_new, |
151abd44 | 844 | .devinit = nv1a_devinit_new, |
03c8952f | 845 | .fb = nv46_fb_new, |
2ea7249f | 846 | .gpio = nv10_gpio_new, |
49bd8da5 | 847 | .i2c = nv04_i2c_new, |
b7a2bc18 | 848 | .imem = nv40_instmem_new, |
2b700825 | 849 | .mc = nv44_mc_new, |
c9582455 | 850 | .mmu = nv44_mmu_new, |
0a34fb31 | 851 | .pci = nv4c_pci_new, |
57113c01 | 852 | .therm = nv40_therm_new, |
31649ecf | 853 | .timer = nv41_timer_new, |
437b2296 | 854 | .volt = nv40_volt_new, |
70aa8670 | 855 | .disp = nv04_disp_new, |
bd70563f | 856 | .dma = nv04_dma_new, |
13de7f46 | 857 | .fifo = nv40_fifo_new, |
c85ee6ca | 858 | .gr = nv44_gr_new, |
7624fc01 | 859 | .mpeg = nv44_mpeg_new, |
97070f23 | 860 | .pm = nv40_pm_new, |
6f41c7c5 | 861 | .sw = nv10_sw_new, |
6cf813fb BS |
862 | }; |
863 | ||
864 | static const struct nvkm_device_chip | |
865 | nv67_chipset = { | |
866 | .name = "C67", | |
46484438 | 867 | .bios = nvkm_bios_new, |
bb23f9d7 | 868 | .bus = nv31_bus_new, |
6625f55c | 869 | .clk = nv40_clk_new, |
151abd44 | 870 | .devinit = nv1a_devinit_new, |
03c8952f | 871 | .fb = nv46_fb_new, |
2ea7249f | 872 | .gpio = nv10_gpio_new, |
49bd8da5 | 873 | .i2c = nv04_i2c_new, |
b7a2bc18 | 874 | .imem = nv40_instmem_new, |
2b700825 | 875 | .mc = nv44_mc_new, |
c9582455 | 876 | .mmu = nv44_mmu_new, |
0a34fb31 | 877 | .pci = nv4c_pci_new, |
57113c01 | 878 | .therm = nv40_therm_new, |
31649ecf | 879 | .timer = nv41_timer_new, |
437b2296 | 880 | .volt = nv40_volt_new, |
70aa8670 | 881 | .disp = nv04_disp_new, |
bd70563f | 882 | .dma = nv04_dma_new, |
13de7f46 | 883 | .fifo = nv40_fifo_new, |
c85ee6ca | 884 | .gr = nv44_gr_new, |
7624fc01 | 885 | .mpeg = nv44_mpeg_new, |
97070f23 | 886 | .pm = nv40_pm_new, |
6f41c7c5 | 887 | .sw = nv10_sw_new, |
6cf813fb BS |
888 | }; |
889 | ||
890 | static const struct nvkm_device_chip | |
891 | nv68_chipset = { | |
892 | .name = "C68", | |
46484438 | 893 | .bios = nvkm_bios_new, |
bb23f9d7 | 894 | .bus = nv31_bus_new, |
6625f55c | 895 | .clk = nv40_clk_new, |
151abd44 | 896 | .devinit = nv1a_devinit_new, |
03c8952f | 897 | .fb = nv46_fb_new, |
2ea7249f | 898 | .gpio = nv10_gpio_new, |
49bd8da5 | 899 | .i2c = nv04_i2c_new, |
b7a2bc18 | 900 | .imem = nv40_instmem_new, |
2b700825 | 901 | .mc = nv44_mc_new, |
c9582455 | 902 | .mmu = nv44_mmu_new, |
0a34fb31 | 903 | .pci = nv4c_pci_new, |
57113c01 | 904 | .therm = nv40_therm_new, |
31649ecf | 905 | .timer = nv41_timer_new, |
437b2296 | 906 | .volt = nv40_volt_new, |
70aa8670 | 907 | .disp = nv04_disp_new, |
bd70563f | 908 | .dma = nv04_dma_new, |
13de7f46 | 909 | .fifo = nv40_fifo_new, |
c85ee6ca | 910 | .gr = nv44_gr_new, |
7624fc01 | 911 | .mpeg = nv44_mpeg_new, |
97070f23 | 912 | .pm = nv40_pm_new, |
6f41c7c5 | 913 | .sw = nv10_sw_new, |
6cf813fb BS |
914 | }; |
915 | ||
916 | static const struct nvkm_device_chip | |
917 | nv84_chipset = { | |
918 | .name = "G84", | |
32932281 | 919 | .bar = g84_bar_new, |
46484438 | 920 | .bios = nvkm_bios_new, |
bb23f9d7 | 921 | .bus = nv50_bus_new, |
6625f55c | 922 | .clk = g84_clk_new, |
151abd44 | 923 | .devinit = g84_devinit_new, |
03c8952f | 924 | .fb = g84_fb_new, |
c5fcafa5 | 925 | .fuse = nv50_fuse_new, |
2ea7249f | 926 | .gpio = nv50_gpio_new, |
49bd8da5 | 927 | .i2c = nv50_i2c_new, |
b7a2bc18 | 928 | .imem = nv50_instmem_new, |
73549020 | 929 | .mc = g84_mc_new, |
c9582455 | 930 | .mmu = nv50_mmu_new, |
a4f7bd36 | 931 | .mxm = nv50_mxm_new, |
3e55b53b | 932 | .pci = g84_pci_new, |
57113c01 | 933 | .therm = g84_therm_new, |
31649ecf | 934 | .timer = nv41_timer_new, |
437b2296 | 935 | .volt = nv40_volt_new, |
98b20c9a | 936 | .bsp = g84_bsp_new, |
14d74aca | 937 | .cipher = g84_cipher_new, |
70aa8670 | 938 | .disp = g84_disp_new, |
bd70563f | 939 | .dma = nv50_dma_new, |
13de7f46 | 940 | .fifo = g84_fifo_new, |
c85ee6ca | 941 | .gr = g84_gr_new, |
7624fc01 | 942 | .mpeg = g84_mpeg_new, |
97070f23 | 943 | .pm = g84_pm_new, |
6f41c7c5 | 944 | .sw = nv50_sw_new, |
98b20c9a | 945 | .vp = g84_vp_new, |
6cf813fb BS |
946 | }; |
947 | ||
948 | static const struct nvkm_device_chip | |
949 | nv86_chipset = { | |
950 | .name = "G86", | |
32932281 | 951 | .bar = g84_bar_new, |
46484438 | 952 | .bios = nvkm_bios_new, |
bb23f9d7 | 953 | .bus = nv50_bus_new, |
6625f55c | 954 | .clk = g84_clk_new, |
151abd44 | 955 | .devinit = g84_devinit_new, |
03c8952f | 956 | .fb = g84_fb_new, |
c5fcafa5 | 957 | .fuse = nv50_fuse_new, |
2ea7249f | 958 | .gpio = nv50_gpio_new, |
49bd8da5 | 959 | .i2c = nv50_i2c_new, |
b7a2bc18 | 960 | .imem = nv50_instmem_new, |
73549020 | 961 | .mc = g84_mc_new, |
c9582455 | 962 | .mmu = nv50_mmu_new, |
a4f7bd36 | 963 | .mxm = nv50_mxm_new, |
3e55b53b | 964 | .pci = g84_pci_new, |
57113c01 | 965 | .therm = g84_therm_new, |
31649ecf | 966 | .timer = nv41_timer_new, |
437b2296 | 967 | .volt = nv40_volt_new, |
98b20c9a | 968 | .bsp = g84_bsp_new, |
14d74aca | 969 | .cipher = g84_cipher_new, |
70aa8670 | 970 | .disp = g84_disp_new, |
bd70563f | 971 | .dma = nv50_dma_new, |
13de7f46 | 972 | .fifo = g84_fifo_new, |
c85ee6ca | 973 | .gr = g84_gr_new, |
7624fc01 | 974 | .mpeg = g84_mpeg_new, |
97070f23 | 975 | .pm = g84_pm_new, |
6f41c7c5 | 976 | .sw = nv50_sw_new, |
98b20c9a | 977 | .vp = g84_vp_new, |
6cf813fb BS |
978 | }; |
979 | ||
980 | static const struct nvkm_device_chip | |
981 | nv92_chipset = { | |
982 | .name = "G92", | |
32932281 | 983 | .bar = g84_bar_new, |
46484438 | 984 | .bios = nvkm_bios_new, |
bb23f9d7 | 985 | .bus = nv50_bus_new, |
6625f55c | 986 | .clk = g84_clk_new, |
151abd44 | 987 | .devinit = g84_devinit_new, |
03c8952f | 988 | .fb = g84_fb_new, |
c5fcafa5 | 989 | .fuse = nv50_fuse_new, |
2ea7249f | 990 | .gpio = nv50_gpio_new, |
49bd8da5 | 991 | .i2c = nv50_i2c_new, |
b7a2bc18 | 992 | .imem = nv50_instmem_new, |
73549020 | 993 | .mc = g84_mc_new, |
c9582455 | 994 | .mmu = nv50_mmu_new, |
a4f7bd36 | 995 | .mxm = nv50_mxm_new, |
3e55b53b | 996 | .pci = g84_pci_new, |
57113c01 | 997 | .therm = g84_therm_new, |
31649ecf | 998 | .timer = nv41_timer_new, |
437b2296 | 999 | .volt = nv40_volt_new, |
98b20c9a | 1000 | .bsp = g84_bsp_new, |
14d74aca | 1001 | .cipher = g84_cipher_new, |
70aa8670 | 1002 | .disp = g84_disp_new, |
bd70563f | 1003 | .dma = nv50_dma_new, |
13de7f46 | 1004 | .fifo = g84_fifo_new, |
c85ee6ca | 1005 | .gr = g84_gr_new, |
7624fc01 | 1006 | .mpeg = g84_mpeg_new, |
97070f23 | 1007 | .pm = g84_pm_new, |
6f41c7c5 | 1008 | .sw = nv50_sw_new, |
98b20c9a | 1009 | .vp = g84_vp_new, |
6cf813fb BS |
1010 | }; |
1011 | ||
1012 | static const struct nvkm_device_chip | |
1013 | nv94_chipset = { | |
1014 | .name = "G94", | |
32932281 | 1015 | .bar = g84_bar_new, |
46484438 | 1016 | .bios = nvkm_bios_new, |
bb23f9d7 | 1017 | .bus = g94_bus_new, |
6625f55c | 1018 | .clk = g84_clk_new, |
151abd44 | 1019 | .devinit = g84_devinit_new, |
03c8952f | 1020 | .fb = g84_fb_new, |
c5fcafa5 | 1021 | .fuse = nv50_fuse_new, |
2ea7249f | 1022 | .gpio = g94_gpio_new, |
49bd8da5 | 1023 | .i2c = g94_i2c_new, |
b7a2bc18 | 1024 | .imem = nv50_instmem_new, |
73549020 | 1025 | .mc = g84_mc_new, |
c9582455 | 1026 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1027 | .mxm = nv50_mxm_new, |
b31505c4 | 1028 | .pci = g94_pci_new, |
57113c01 | 1029 | .therm = g84_therm_new, |
31649ecf | 1030 | .timer = nv41_timer_new, |
437b2296 | 1031 | .volt = nv40_volt_new, |
98b20c9a | 1032 | .bsp = g84_bsp_new, |
14d74aca | 1033 | .cipher = g84_cipher_new, |
70aa8670 | 1034 | .disp = g94_disp_new, |
bd70563f | 1035 | .dma = nv50_dma_new, |
13de7f46 | 1036 | .fifo = g84_fifo_new, |
c85ee6ca | 1037 | .gr = g84_gr_new, |
7624fc01 | 1038 | .mpeg = g84_mpeg_new, |
97070f23 | 1039 | .pm = g84_pm_new, |
6f41c7c5 | 1040 | .sw = nv50_sw_new, |
98b20c9a | 1041 | .vp = g84_vp_new, |
6cf813fb BS |
1042 | }; |
1043 | ||
1044 | static const struct nvkm_device_chip | |
1045 | nv96_chipset = { | |
1046 | .name = "G96", | |
0a34fb31 | 1047 | .bar = g84_bar_new, |
46484438 | 1048 | .bios = nvkm_bios_new, |
0a34fb31 | 1049 | .bus = g94_bus_new, |
6625f55c | 1050 | .clk = g84_clk_new, |
151abd44 | 1051 | .devinit = g84_devinit_new, |
03c8952f | 1052 | .fb = g84_fb_new, |
0a34fb31 BS |
1053 | .fuse = nv50_fuse_new, |
1054 | .gpio = g94_gpio_new, | |
1055 | .i2c = g94_i2c_new, | |
b7a2bc18 | 1056 | .imem = nv50_instmem_new, |
73549020 | 1057 | .mc = g84_mc_new, |
c9582455 | 1058 | .mmu = nv50_mmu_new, |
0a34fb31 | 1059 | .mxm = nv50_mxm_new, |
b31505c4 | 1060 | .pci = g94_pci_new, |
0a34fb31 BS |
1061 | .therm = g84_therm_new, |
1062 | .timer = nv41_timer_new, | |
437b2296 | 1063 | .volt = nv40_volt_new, |
0a34fb31 BS |
1064 | .bsp = g84_bsp_new, |
1065 | .cipher = g84_cipher_new, | |
1066 | .disp = g94_disp_new, | |
bd70563f | 1067 | .dma = nv50_dma_new, |
13de7f46 | 1068 | .fifo = g84_fifo_new, |
c85ee6ca | 1069 | .gr = g84_gr_new, |
7624fc01 | 1070 | .mpeg = g84_mpeg_new, |
97070f23 | 1071 | .pm = g84_pm_new, |
0a34fb31 BS |
1072 | .sw = nv50_sw_new, |
1073 | .vp = g84_vp_new, | |
6cf813fb BS |
1074 | }; |
1075 | ||
1076 | static const struct nvkm_device_chip | |
1077 | nv98_chipset = { | |
1078 | .name = "G98", | |
0a34fb31 | 1079 | .bar = g84_bar_new, |
46484438 | 1080 | .bios = nvkm_bios_new, |
0a34fb31 | 1081 | .bus = g94_bus_new, |
6625f55c | 1082 | .clk = g84_clk_new, |
151abd44 | 1083 | .devinit = g98_devinit_new, |
03c8952f | 1084 | .fb = g84_fb_new, |
0a34fb31 BS |
1085 | .fuse = nv50_fuse_new, |
1086 | .gpio = g94_gpio_new, | |
1087 | .i2c = g94_i2c_new, | |
b7a2bc18 | 1088 | .imem = nv50_instmem_new, |
0a34fb31 | 1089 | .mc = g98_mc_new, |
c9582455 | 1090 | .mmu = nv50_mmu_new, |
0a34fb31 | 1091 | .mxm = nv50_mxm_new, |
b31505c4 | 1092 | .pci = g94_pci_new, |
0a34fb31 BS |
1093 | .therm = g84_therm_new, |
1094 | .timer = nv41_timer_new, | |
437b2296 | 1095 | .volt = nv40_volt_new, |
0a34fb31 | 1096 | .disp = g94_disp_new, |
bd70563f | 1097 | .dma = nv50_dma_new, |
13de7f46 | 1098 | .fifo = g84_fifo_new, |
c85ee6ca | 1099 | .gr = g84_gr_new, |
53e60da4 | 1100 | .mspdec = g98_mspdec_new, |
53e60da4 | 1101 | .msppp = g98_msppp_new, |
0a34fb31 | 1102 | .msvld = g98_msvld_new, |
97070f23 | 1103 | .pm = g84_pm_new, |
0a34fb31 BS |
1104 | .sec = g98_sec_new, |
1105 | .sw = nv50_sw_new, | |
6cf813fb BS |
1106 | }; |
1107 | ||
1108 | static const struct nvkm_device_chip | |
1109 | nva0_chipset = { | |
1110 | .name = "GT200", | |
32932281 | 1111 | .bar = g84_bar_new, |
46484438 | 1112 | .bios = nvkm_bios_new, |
bb23f9d7 | 1113 | .bus = g94_bus_new, |
6625f55c | 1114 | .clk = g84_clk_new, |
151abd44 | 1115 | .devinit = g84_devinit_new, |
03c8952f | 1116 | .fb = g84_fb_new, |
c5fcafa5 | 1117 | .fuse = nv50_fuse_new, |
2ea7249f | 1118 | .gpio = g94_gpio_new, |
49bd8da5 | 1119 | .i2c = nv50_i2c_new, |
b7a2bc18 | 1120 | .imem = nv50_instmem_new, |
73549020 | 1121 | .mc = g84_mc_new, |
c9582455 | 1122 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1123 | .mxm = nv50_mxm_new, |
b31505c4 | 1124 | .pci = g94_pci_new, |
57113c01 | 1125 | .therm = g84_therm_new, |
31649ecf | 1126 | .timer = nv41_timer_new, |
437b2296 | 1127 | .volt = nv40_volt_new, |
98b20c9a | 1128 | .bsp = g84_bsp_new, |
14d74aca | 1129 | .cipher = g84_cipher_new, |
70aa8670 | 1130 | .disp = gt200_disp_new, |
bd70563f | 1131 | .dma = nv50_dma_new, |
13de7f46 | 1132 | .fifo = g84_fifo_new, |
c85ee6ca | 1133 | .gr = gt200_gr_new, |
7624fc01 | 1134 | .mpeg = g84_mpeg_new, |
97070f23 | 1135 | .pm = gt200_pm_new, |
6f41c7c5 | 1136 | .sw = nv50_sw_new, |
98b20c9a | 1137 | .vp = g84_vp_new, |
6cf813fb BS |
1138 | }; |
1139 | ||
1140 | static const struct nvkm_device_chip | |
1141 | nva3_chipset = { | |
1142 | .name = "GT215", | |
32932281 | 1143 | .bar = g84_bar_new, |
46484438 | 1144 | .bios = nvkm_bios_new, |
bb23f9d7 | 1145 | .bus = g94_bus_new, |
6625f55c | 1146 | .clk = gt215_clk_new, |
151abd44 | 1147 | .devinit = gt215_devinit_new, |
03c8952f | 1148 | .fb = gt215_fb_new, |
c5fcafa5 | 1149 | .fuse = nv50_fuse_new, |
2ea7249f | 1150 | .gpio = g94_gpio_new, |
49bd8da5 | 1151 | .i2c = g94_i2c_new, |
b7a2bc18 | 1152 | .imem = nv50_instmem_new, |
88c0de2c | 1153 | .mc = gt215_mc_new, |
c9582455 | 1154 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1155 | .mxm = nv50_mxm_new, |
b31505c4 | 1156 | .pci = g94_pci_new, |
e2ca4e7d | 1157 | .pmu = gt215_pmu_new, |
57113c01 | 1158 | .therm = gt215_therm_new, |
31649ecf | 1159 | .timer = nv41_timer_new, |
437b2296 | 1160 | .volt = nv40_volt_new, |
53e60da4 | 1161 | .ce[0] = gt215_ce_new, |
70aa8670 | 1162 | .disp = gt215_disp_new, |
bd70563f | 1163 | .dma = nv50_dma_new, |
13de7f46 | 1164 | .fifo = g84_fifo_new, |
c85ee6ca | 1165 | .gr = gt215_gr_new, |
7624fc01 | 1166 | .mpeg = g84_mpeg_new, |
53e60da4 BS |
1167 | .mspdec = gt215_mspdec_new, |
1168 | .msppp = gt215_msppp_new, | |
1169 | .msvld = gt215_msvld_new, | |
97070f23 | 1170 | .pm = gt215_pm_new, |
6f41c7c5 | 1171 | .sw = nv50_sw_new, |
6cf813fb BS |
1172 | }; |
1173 | ||
1174 | static const struct nvkm_device_chip | |
1175 | nva5_chipset = { | |
1176 | .name = "GT216", | |
32932281 | 1177 | .bar = g84_bar_new, |
46484438 | 1178 | .bios = nvkm_bios_new, |
bb23f9d7 | 1179 | .bus = g94_bus_new, |
6625f55c | 1180 | .clk = gt215_clk_new, |
151abd44 | 1181 | .devinit = gt215_devinit_new, |
03c8952f | 1182 | .fb = gt215_fb_new, |
c5fcafa5 | 1183 | .fuse = nv50_fuse_new, |
2ea7249f | 1184 | .gpio = g94_gpio_new, |
49bd8da5 | 1185 | .i2c = g94_i2c_new, |
b7a2bc18 | 1186 | .imem = nv50_instmem_new, |
88c0de2c | 1187 | .mc = gt215_mc_new, |
c9582455 | 1188 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1189 | .mxm = nv50_mxm_new, |
b31505c4 | 1190 | .pci = g94_pci_new, |
e2ca4e7d | 1191 | .pmu = gt215_pmu_new, |
57113c01 | 1192 | .therm = gt215_therm_new, |
31649ecf | 1193 | .timer = nv41_timer_new, |
437b2296 | 1194 | .volt = nv40_volt_new, |
53e60da4 | 1195 | .ce[0] = gt215_ce_new, |
70aa8670 | 1196 | .disp = gt215_disp_new, |
bd70563f | 1197 | .dma = nv50_dma_new, |
13de7f46 | 1198 | .fifo = g84_fifo_new, |
c85ee6ca | 1199 | .gr = gt215_gr_new, |
53e60da4 BS |
1200 | .mspdec = gt215_mspdec_new, |
1201 | .msppp = gt215_msppp_new, | |
1202 | .msvld = gt215_msvld_new, | |
97070f23 | 1203 | .pm = gt215_pm_new, |
6f41c7c5 | 1204 | .sw = nv50_sw_new, |
6cf813fb BS |
1205 | }; |
1206 | ||
1207 | static const struct nvkm_device_chip | |
1208 | nva8_chipset = { | |
1209 | .name = "GT218", | |
32932281 | 1210 | .bar = g84_bar_new, |
46484438 | 1211 | .bios = nvkm_bios_new, |
bb23f9d7 | 1212 | .bus = g94_bus_new, |
6625f55c | 1213 | .clk = gt215_clk_new, |
151abd44 | 1214 | .devinit = gt215_devinit_new, |
03c8952f | 1215 | .fb = gt215_fb_new, |
c5fcafa5 | 1216 | .fuse = nv50_fuse_new, |
2ea7249f | 1217 | .gpio = g94_gpio_new, |
49bd8da5 | 1218 | .i2c = g94_i2c_new, |
b7a2bc18 | 1219 | .imem = nv50_instmem_new, |
88c0de2c | 1220 | .mc = gt215_mc_new, |
c9582455 | 1221 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1222 | .mxm = nv50_mxm_new, |
b31505c4 | 1223 | .pci = g94_pci_new, |
e2ca4e7d | 1224 | .pmu = gt215_pmu_new, |
57113c01 | 1225 | .therm = gt215_therm_new, |
31649ecf | 1226 | .timer = nv41_timer_new, |
437b2296 | 1227 | .volt = nv40_volt_new, |
53e60da4 | 1228 | .ce[0] = gt215_ce_new, |
70aa8670 | 1229 | .disp = gt215_disp_new, |
bd70563f | 1230 | .dma = nv50_dma_new, |
13de7f46 | 1231 | .fifo = g84_fifo_new, |
c85ee6ca | 1232 | .gr = gt215_gr_new, |
53e60da4 BS |
1233 | .mspdec = gt215_mspdec_new, |
1234 | .msppp = gt215_msppp_new, | |
1235 | .msvld = gt215_msvld_new, | |
97070f23 | 1236 | .pm = gt215_pm_new, |
6f41c7c5 | 1237 | .sw = nv50_sw_new, |
6cf813fb BS |
1238 | }; |
1239 | ||
1240 | static const struct nvkm_device_chip | |
1241 | nvaa_chipset = { | |
1242 | .name = "MCP77/MCP78", | |
32932281 | 1243 | .bar = g84_bar_new, |
46484438 | 1244 | .bios = nvkm_bios_new, |
bb23f9d7 | 1245 | .bus = g94_bus_new, |
6625f55c | 1246 | .clk = mcp77_clk_new, |
151abd44 | 1247 | .devinit = g98_devinit_new, |
03c8952f | 1248 | .fb = mcp77_fb_new, |
c5fcafa5 | 1249 | .fuse = nv50_fuse_new, |
2ea7249f | 1250 | .gpio = g94_gpio_new, |
49bd8da5 | 1251 | .i2c = g94_i2c_new, |
b7a2bc18 | 1252 | .imem = nv50_instmem_new, |
54dcadd5 | 1253 | .mc = g98_mc_new, |
c9582455 | 1254 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1255 | .mxm = nv50_mxm_new, |
b31505c4 | 1256 | .pci = g94_pci_new, |
57113c01 | 1257 | .therm = g84_therm_new, |
31649ecf | 1258 | .timer = nv41_timer_new, |
437b2296 | 1259 | .volt = nv40_volt_new, |
70aa8670 | 1260 | .disp = g94_disp_new, |
bd70563f | 1261 | .dma = nv50_dma_new, |
13de7f46 | 1262 | .fifo = g84_fifo_new, |
c85ee6ca | 1263 | .gr = gt200_gr_new, |
53e60da4 BS |
1264 | .mspdec = g98_mspdec_new, |
1265 | .msppp = g98_msppp_new, | |
1266 | .msvld = g98_msvld_new, | |
97070f23 | 1267 | .pm = g84_pm_new, |
53e60da4 | 1268 | .sec = g98_sec_new, |
6f41c7c5 | 1269 | .sw = nv50_sw_new, |
6cf813fb BS |
1270 | }; |
1271 | ||
1272 | static const struct nvkm_device_chip | |
1273 | nvac_chipset = { | |
1274 | .name = "MCP79/MCP7A", | |
32932281 | 1275 | .bar = g84_bar_new, |
46484438 | 1276 | .bios = nvkm_bios_new, |
bb23f9d7 | 1277 | .bus = g94_bus_new, |
6625f55c | 1278 | .clk = mcp77_clk_new, |
151abd44 | 1279 | .devinit = g98_devinit_new, |
03c8952f | 1280 | .fb = mcp77_fb_new, |
c5fcafa5 | 1281 | .fuse = nv50_fuse_new, |
2ea7249f | 1282 | .gpio = g94_gpio_new, |
49bd8da5 | 1283 | .i2c = g94_i2c_new, |
b7a2bc18 | 1284 | .imem = nv50_instmem_new, |
54dcadd5 | 1285 | .mc = g98_mc_new, |
c9582455 | 1286 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1287 | .mxm = nv50_mxm_new, |
b31505c4 | 1288 | .pci = g94_pci_new, |
57113c01 | 1289 | .therm = g84_therm_new, |
31649ecf | 1290 | .timer = nv41_timer_new, |
437b2296 | 1291 | .volt = nv40_volt_new, |
70aa8670 | 1292 | .disp = g94_disp_new, |
bd70563f | 1293 | .dma = nv50_dma_new, |
13de7f46 | 1294 | .fifo = g84_fifo_new, |
c85ee6ca | 1295 | .gr = mcp79_gr_new, |
53e60da4 BS |
1296 | .mspdec = g98_mspdec_new, |
1297 | .msppp = g98_msppp_new, | |
1298 | .msvld = g98_msvld_new, | |
97070f23 | 1299 | .pm = g84_pm_new, |
53e60da4 | 1300 | .sec = g98_sec_new, |
6f41c7c5 | 1301 | .sw = nv50_sw_new, |
6cf813fb BS |
1302 | }; |
1303 | ||
1304 | static const struct nvkm_device_chip | |
1305 | nvaf_chipset = { | |
1306 | .name = "MCP89", | |
32932281 | 1307 | .bar = g84_bar_new, |
46484438 | 1308 | .bios = nvkm_bios_new, |
bb23f9d7 | 1309 | .bus = g94_bus_new, |
6625f55c | 1310 | .clk = gt215_clk_new, |
151abd44 | 1311 | .devinit = mcp89_devinit_new, |
03c8952f | 1312 | .fb = mcp89_fb_new, |
c5fcafa5 | 1313 | .fuse = nv50_fuse_new, |
2ea7249f | 1314 | .gpio = g94_gpio_new, |
49bd8da5 | 1315 | .i2c = g94_i2c_new, |
b7a2bc18 | 1316 | .imem = nv50_instmem_new, |
88c0de2c | 1317 | .mc = gt215_mc_new, |
c9582455 | 1318 | .mmu = nv50_mmu_new, |
a4f7bd36 | 1319 | .mxm = nv50_mxm_new, |
b31505c4 | 1320 | .pci = g94_pci_new, |
e2ca4e7d | 1321 | .pmu = gt215_pmu_new, |
57113c01 | 1322 | .therm = gt215_therm_new, |
31649ecf | 1323 | .timer = nv41_timer_new, |
437b2296 | 1324 | .volt = nv40_volt_new, |
53e60da4 | 1325 | .ce[0] = gt215_ce_new, |
70aa8670 | 1326 | .disp = gt215_disp_new, |
bd70563f | 1327 | .dma = nv50_dma_new, |
13de7f46 | 1328 | .fifo = g84_fifo_new, |
c85ee6ca | 1329 | .gr = mcp89_gr_new, |
53e60da4 BS |
1330 | .mspdec = gt215_mspdec_new, |
1331 | .msppp = gt215_msppp_new, | |
1332 | .msvld = mcp89_msvld_new, | |
97070f23 | 1333 | .pm = gt215_pm_new, |
6f41c7c5 | 1334 | .sw = nv50_sw_new, |
6cf813fb BS |
1335 | }; |
1336 | ||
1337 | static const struct nvkm_device_chip | |
1338 | nvc0_chipset = { | |
1339 | .name = "GF100", | |
32932281 | 1340 | .bar = gf100_bar_new, |
46484438 | 1341 | .bios = nvkm_bios_new, |
bb23f9d7 | 1342 | .bus = gf100_bus_new, |
6625f55c | 1343 | .clk = gf100_clk_new, |
151abd44 | 1344 | .devinit = gf100_devinit_new, |
03c8952f | 1345 | .fb = gf100_fb_new, |
c5fcafa5 | 1346 | .fuse = gf100_fuse_new, |
2ea7249f | 1347 | .gpio = g94_gpio_new, |
49bd8da5 | 1348 | .i2c = g94_i2c_new, |
551d3417 | 1349 | .ibus = gf100_ibus_new, |
b71c0892 | 1350 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1351 | .imem = nv50_instmem_new, |
70bc7182 | 1352 | .ltc = gf100_ltc_new, |
54dcadd5 | 1353 | .mc = gf100_mc_new, |
c9582455 | 1354 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1355 | .mxm = nv50_mxm_new, |
0a34fb31 | 1356 | .pci = gf100_pci_new, |
e2ca4e7d | 1357 | .pmu = gf100_pmu_new, |
57113c01 | 1358 | .therm = gt215_therm_new, |
31649ecf | 1359 | .timer = nv41_timer_new, |
437b2296 | 1360 | .volt = nv40_volt_new, |
53e60da4 BS |
1361 | .ce[0] = gf100_ce_new, |
1362 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1363 | .disp = gt215_disp_new, |
bd70563f | 1364 | .dma = gf100_dma_new, |
13de7f46 | 1365 | .fifo = gf100_fifo_new, |
c85ee6ca | 1366 | .gr = gf100_gr_new, |
53e60da4 BS |
1367 | .mspdec = gf100_mspdec_new, |
1368 | .msppp = gf100_msppp_new, | |
1369 | .msvld = gf100_msvld_new, | |
97070f23 | 1370 | .pm = gf100_pm_new, |
6f41c7c5 | 1371 | .sw = gf100_sw_new, |
6cf813fb BS |
1372 | }; |
1373 | ||
1374 | static const struct nvkm_device_chip | |
1375 | nvc1_chipset = { | |
1376 | .name = "GF108", | |
32932281 | 1377 | .bar = gf100_bar_new, |
46484438 | 1378 | .bios = nvkm_bios_new, |
bb23f9d7 | 1379 | .bus = gf100_bus_new, |
6625f55c | 1380 | .clk = gf100_clk_new, |
151abd44 | 1381 | .devinit = gf100_devinit_new, |
03c8952f | 1382 | .fb = gf100_fb_new, |
c5fcafa5 | 1383 | .fuse = gf100_fuse_new, |
2ea7249f | 1384 | .gpio = g94_gpio_new, |
49bd8da5 | 1385 | .i2c = g94_i2c_new, |
551d3417 | 1386 | .ibus = gf100_ibus_new, |
b71c0892 | 1387 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1388 | .imem = nv50_instmem_new, |
70bc7182 | 1389 | .ltc = gf100_ltc_new, |
2b700825 | 1390 | .mc = gf100_mc_new, |
c9582455 | 1391 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1392 | .mxm = nv50_mxm_new, |
bec4961e | 1393 | .pci = gf106_pci_new, |
e2ca4e7d | 1394 | .pmu = gf100_pmu_new, |
57113c01 | 1395 | .therm = gt215_therm_new, |
31649ecf | 1396 | .timer = nv41_timer_new, |
437b2296 | 1397 | .volt = nv40_volt_new, |
53e60da4 | 1398 | .ce[0] = gf100_ce_new, |
70aa8670 | 1399 | .disp = gt215_disp_new, |
bd70563f | 1400 | .dma = gf100_dma_new, |
13de7f46 | 1401 | .fifo = gf100_fifo_new, |
c85ee6ca | 1402 | .gr = gf108_gr_new, |
53e60da4 BS |
1403 | .mspdec = gf100_mspdec_new, |
1404 | .msppp = gf100_msppp_new, | |
1405 | .msvld = gf100_msvld_new, | |
97070f23 | 1406 | .pm = gf108_pm_new, |
6f41c7c5 | 1407 | .sw = gf100_sw_new, |
6cf813fb BS |
1408 | }; |
1409 | ||
1410 | static const struct nvkm_device_chip | |
1411 | nvc3_chipset = { | |
1412 | .name = "GF106", | |
32932281 | 1413 | .bar = gf100_bar_new, |
46484438 | 1414 | .bios = nvkm_bios_new, |
bb23f9d7 | 1415 | .bus = gf100_bus_new, |
6625f55c | 1416 | .clk = gf100_clk_new, |
151abd44 | 1417 | .devinit = gf100_devinit_new, |
03c8952f | 1418 | .fb = gf100_fb_new, |
c5fcafa5 | 1419 | .fuse = gf100_fuse_new, |
2ea7249f | 1420 | .gpio = g94_gpio_new, |
49bd8da5 | 1421 | .i2c = g94_i2c_new, |
551d3417 | 1422 | .ibus = gf100_ibus_new, |
b71c0892 | 1423 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1424 | .imem = nv50_instmem_new, |
70bc7182 | 1425 | .ltc = gf100_ltc_new, |
2b700825 | 1426 | .mc = gf100_mc_new, |
c9582455 | 1427 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1428 | .mxm = nv50_mxm_new, |
bec4961e | 1429 | .pci = gf106_pci_new, |
e2ca4e7d | 1430 | .pmu = gf100_pmu_new, |
57113c01 | 1431 | .therm = gt215_therm_new, |
31649ecf | 1432 | .timer = nv41_timer_new, |
437b2296 | 1433 | .volt = nv40_volt_new, |
53e60da4 | 1434 | .ce[0] = gf100_ce_new, |
70aa8670 | 1435 | .disp = gt215_disp_new, |
bd70563f | 1436 | .dma = gf100_dma_new, |
13de7f46 | 1437 | .fifo = gf100_fifo_new, |
c85ee6ca | 1438 | .gr = gf104_gr_new, |
53e60da4 BS |
1439 | .mspdec = gf100_mspdec_new, |
1440 | .msppp = gf100_msppp_new, | |
1441 | .msvld = gf100_msvld_new, | |
97070f23 | 1442 | .pm = gf100_pm_new, |
6f41c7c5 | 1443 | .sw = gf100_sw_new, |
6cf813fb BS |
1444 | }; |
1445 | ||
1446 | static const struct nvkm_device_chip | |
1447 | nvc4_chipset = { | |
1448 | .name = "GF104", | |
32932281 | 1449 | .bar = gf100_bar_new, |
46484438 | 1450 | .bios = nvkm_bios_new, |
bb23f9d7 | 1451 | .bus = gf100_bus_new, |
6625f55c | 1452 | .clk = gf100_clk_new, |
151abd44 | 1453 | .devinit = gf100_devinit_new, |
03c8952f | 1454 | .fb = gf100_fb_new, |
c5fcafa5 | 1455 | .fuse = gf100_fuse_new, |
2ea7249f | 1456 | .gpio = g94_gpio_new, |
49bd8da5 | 1457 | .i2c = g94_i2c_new, |
551d3417 | 1458 | .ibus = gf100_ibus_new, |
b71c0892 | 1459 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1460 | .imem = nv50_instmem_new, |
70bc7182 | 1461 | .ltc = gf100_ltc_new, |
54dcadd5 | 1462 | .mc = gf100_mc_new, |
c9582455 | 1463 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1464 | .mxm = nv50_mxm_new, |
0a34fb31 | 1465 | .pci = gf100_pci_new, |
e2ca4e7d | 1466 | .pmu = gf100_pmu_new, |
57113c01 | 1467 | .therm = gt215_therm_new, |
31649ecf | 1468 | .timer = nv41_timer_new, |
437b2296 | 1469 | .volt = nv40_volt_new, |
53e60da4 BS |
1470 | .ce[0] = gf100_ce_new, |
1471 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1472 | .disp = gt215_disp_new, |
bd70563f | 1473 | .dma = gf100_dma_new, |
13de7f46 | 1474 | .fifo = gf100_fifo_new, |
c85ee6ca | 1475 | .gr = gf104_gr_new, |
53e60da4 BS |
1476 | .mspdec = gf100_mspdec_new, |
1477 | .msppp = gf100_msppp_new, | |
1478 | .msvld = gf100_msvld_new, | |
97070f23 | 1479 | .pm = gf100_pm_new, |
6f41c7c5 | 1480 | .sw = gf100_sw_new, |
6cf813fb BS |
1481 | }; |
1482 | ||
1483 | static const struct nvkm_device_chip | |
1484 | nvc8_chipset = { | |
1485 | .name = "GF110", | |
32932281 | 1486 | .bar = gf100_bar_new, |
46484438 | 1487 | .bios = nvkm_bios_new, |
bb23f9d7 | 1488 | .bus = gf100_bus_new, |
6625f55c | 1489 | .clk = gf100_clk_new, |
151abd44 | 1490 | .devinit = gf100_devinit_new, |
03c8952f | 1491 | .fb = gf100_fb_new, |
c5fcafa5 | 1492 | .fuse = gf100_fuse_new, |
2ea7249f | 1493 | .gpio = g94_gpio_new, |
49bd8da5 | 1494 | .i2c = g94_i2c_new, |
551d3417 | 1495 | .ibus = gf100_ibus_new, |
b71c0892 | 1496 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1497 | .imem = nv50_instmem_new, |
70bc7182 | 1498 | .ltc = gf100_ltc_new, |
54dcadd5 | 1499 | .mc = gf100_mc_new, |
c9582455 | 1500 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1501 | .mxm = nv50_mxm_new, |
0a34fb31 | 1502 | .pci = gf100_pci_new, |
e2ca4e7d | 1503 | .pmu = gf100_pmu_new, |
57113c01 | 1504 | .therm = gt215_therm_new, |
31649ecf | 1505 | .timer = nv41_timer_new, |
437b2296 | 1506 | .volt = nv40_volt_new, |
53e60da4 BS |
1507 | .ce[0] = gf100_ce_new, |
1508 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1509 | .disp = gt215_disp_new, |
bd70563f | 1510 | .dma = gf100_dma_new, |
13de7f46 | 1511 | .fifo = gf100_fifo_new, |
c85ee6ca | 1512 | .gr = gf110_gr_new, |
53e60da4 BS |
1513 | .mspdec = gf100_mspdec_new, |
1514 | .msppp = gf100_msppp_new, | |
1515 | .msvld = gf100_msvld_new, | |
97070f23 | 1516 | .pm = gf100_pm_new, |
6f41c7c5 | 1517 | .sw = gf100_sw_new, |
6cf813fb BS |
1518 | }; |
1519 | ||
1520 | static const struct nvkm_device_chip | |
1521 | nvce_chipset = { | |
1522 | .name = "GF114", | |
32932281 | 1523 | .bar = gf100_bar_new, |
46484438 | 1524 | .bios = nvkm_bios_new, |
bb23f9d7 | 1525 | .bus = gf100_bus_new, |
6625f55c | 1526 | .clk = gf100_clk_new, |
151abd44 | 1527 | .devinit = gf100_devinit_new, |
03c8952f | 1528 | .fb = gf100_fb_new, |
c5fcafa5 | 1529 | .fuse = gf100_fuse_new, |
2ea7249f | 1530 | .gpio = g94_gpio_new, |
49bd8da5 | 1531 | .i2c = g94_i2c_new, |
551d3417 | 1532 | .ibus = gf100_ibus_new, |
b71c0892 | 1533 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1534 | .imem = nv50_instmem_new, |
70bc7182 | 1535 | .ltc = gf100_ltc_new, |
54dcadd5 | 1536 | .mc = gf100_mc_new, |
c9582455 | 1537 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1538 | .mxm = nv50_mxm_new, |
0a34fb31 | 1539 | .pci = gf100_pci_new, |
e2ca4e7d | 1540 | .pmu = gf100_pmu_new, |
57113c01 | 1541 | .therm = gt215_therm_new, |
31649ecf | 1542 | .timer = nv41_timer_new, |
437b2296 | 1543 | .volt = nv40_volt_new, |
53e60da4 BS |
1544 | .ce[0] = gf100_ce_new, |
1545 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1546 | .disp = gt215_disp_new, |
bd70563f | 1547 | .dma = gf100_dma_new, |
13de7f46 | 1548 | .fifo = gf100_fifo_new, |
c85ee6ca | 1549 | .gr = gf104_gr_new, |
53e60da4 BS |
1550 | .mspdec = gf100_mspdec_new, |
1551 | .msppp = gf100_msppp_new, | |
1552 | .msvld = gf100_msvld_new, | |
97070f23 | 1553 | .pm = gf100_pm_new, |
6f41c7c5 | 1554 | .sw = gf100_sw_new, |
6cf813fb BS |
1555 | }; |
1556 | ||
1557 | static const struct nvkm_device_chip | |
1558 | nvcf_chipset = { | |
1559 | .name = "GF116", | |
32932281 | 1560 | .bar = gf100_bar_new, |
46484438 | 1561 | .bios = nvkm_bios_new, |
bb23f9d7 | 1562 | .bus = gf100_bus_new, |
6625f55c | 1563 | .clk = gf100_clk_new, |
151abd44 | 1564 | .devinit = gf100_devinit_new, |
03c8952f | 1565 | .fb = gf100_fb_new, |
c5fcafa5 | 1566 | .fuse = gf100_fuse_new, |
2ea7249f | 1567 | .gpio = g94_gpio_new, |
49bd8da5 | 1568 | .i2c = g94_i2c_new, |
551d3417 | 1569 | .ibus = gf100_ibus_new, |
b71c0892 | 1570 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1571 | .imem = nv50_instmem_new, |
70bc7182 | 1572 | .ltc = gf100_ltc_new, |
2b700825 | 1573 | .mc = gf100_mc_new, |
c9582455 | 1574 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1575 | .mxm = nv50_mxm_new, |
bec4961e | 1576 | .pci = gf106_pci_new, |
e2ca4e7d | 1577 | .pmu = gf100_pmu_new, |
57113c01 | 1578 | .therm = gt215_therm_new, |
31649ecf | 1579 | .timer = nv41_timer_new, |
437b2296 | 1580 | .volt = nv40_volt_new, |
53e60da4 | 1581 | .ce[0] = gf100_ce_new, |
70aa8670 | 1582 | .disp = gt215_disp_new, |
bd70563f | 1583 | .dma = gf100_dma_new, |
13de7f46 | 1584 | .fifo = gf100_fifo_new, |
c85ee6ca | 1585 | .gr = gf104_gr_new, |
53e60da4 BS |
1586 | .mspdec = gf100_mspdec_new, |
1587 | .msppp = gf100_msppp_new, | |
1588 | .msvld = gf100_msvld_new, | |
97070f23 | 1589 | .pm = gf100_pm_new, |
6f41c7c5 | 1590 | .sw = gf100_sw_new, |
6cf813fb BS |
1591 | }; |
1592 | ||
1593 | static const struct nvkm_device_chip | |
1594 | nvd7_chipset = { | |
1595 | .name = "GF117", | |
32932281 | 1596 | .bar = gf100_bar_new, |
46484438 | 1597 | .bios = nvkm_bios_new, |
bb23f9d7 | 1598 | .bus = gf100_bus_new, |
6625f55c | 1599 | .clk = gf100_clk_new, |
151abd44 | 1600 | .devinit = gf100_devinit_new, |
03c8952f | 1601 | .fb = gf100_fb_new, |
c5fcafa5 | 1602 | .fuse = gf100_fuse_new, |
2ea7249f | 1603 | .gpio = gf119_gpio_new, |
49bd8da5 | 1604 | .i2c = gf117_i2c_new, |
b6afa265 | 1605 | .ibus = gf117_ibus_new, |
b71c0892 | 1606 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1607 | .imem = nv50_instmem_new, |
70bc7182 | 1608 | .ltc = gf100_ltc_new, |
2b700825 | 1609 | .mc = gf100_mc_new, |
c9582455 | 1610 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1611 | .mxm = nv50_mxm_new, |
bec4961e | 1612 | .pci = gf106_pci_new, |
57113c01 | 1613 | .therm = gf119_therm_new, |
31649ecf | 1614 | .timer = nv41_timer_new, |
53e60da4 | 1615 | .ce[0] = gf100_ce_new, |
70aa8670 | 1616 | .disp = gf119_disp_new, |
bd70563f | 1617 | .dma = gf119_dma_new, |
13de7f46 | 1618 | .fifo = gf100_fifo_new, |
c85ee6ca | 1619 | .gr = gf117_gr_new, |
53e60da4 BS |
1620 | .mspdec = gf100_mspdec_new, |
1621 | .msppp = gf100_msppp_new, | |
1622 | .msvld = gf100_msvld_new, | |
97070f23 | 1623 | .pm = gf117_pm_new, |
6f41c7c5 | 1624 | .sw = gf100_sw_new, |
6cf813fb BS |
1625 | }; |
1626 | ||
1627 | static const struct nvkm_device_chip | |
1628 | nvd9_chipset = { | |
1629 | .name = "GF119", | |
32932281 | 1630 | .bar = gf100_bar_new, |
46484438 | 1631 | .bios = nvkm_bios_new, |
bb23f9d7 | 1632 | .bus = gf100_bus_new, |
6625f55c | 1633 | .clk = gf100_clk_new, |
151abd44 | 1634 | .devinit = gf100_devinit_new, |
03c8952f | 1635 | .fb = gf100_fb_new, |
c5fcafa5 | 1636 | .fuse = gf100_fuse_new, |
2ea7249f | 1637 | .gpio = gf119_gpio_new, |
49bd8da5 | 1638 | .i2c = gf119_i2c_new, |
b6afa265 | 1639 | .ibus = gf117_ibus_new, |
b71c0892 | 1640 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1641 | .imem = nv50_instmem_new, |
70bc7182 | 1642 | .ltc = gf100_ltc_new, |
2b700825 | 1643 | .mc = gf100_mc_new, |
c9582455 | 1644 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1645 | .mxm = nv50_mxm_new, |
bec4961e | 1646 | .pci = gf106_pci_new, |
e2ca4e7d | 1647 | .pmu = gf119_pmu_new, |
57113c01 | 1648 | .therm = gf119_therm_new, |
31649ecf | 1649 | .timer = nv41_timer_new, |
437b2296 | 1650 | .volt = nv40_volt_new, |
53e60da4 | 1651 | .ce[0] = gf100_ce_new, |
70aa8670 | 1652 | .disp = gf119_disp_new, |
bd70563f | 1653 | .dma = gf119_dma_new, |
13de7f46 | 1654 | .fifo = gf100_fifo_new, |
c85ee6ca | 1655 | .gr = gf119_gr_new, |
53e60da4 BS |
1656 | .mspdec = gf100_mspdec_new, |
1657 | .msppp = gf100_msppp_new, | |
1658 | .msvld = gf100_msvld_new, | |
97070f23 | 1659 | .pm = gf117_pm_new, |
6f41c7c5 | 1660 | .sw = gf100_sw_new, |
6cf813fb BS |
1661 | }; |
1662 | ||
1663 | static const struct nvkm_device_chip | |
1664 | nve4_chipset = { | |
1665 | .name = "GK104", | |
32932281 | 1666 | .bar = gf100_bar_new, |
46484438 | 1667 | .bios = nvkm_bios_new, |
bb23f9d7 | 1668 | .bus = gf100_bus_new, |
6625f55c | 1669 | .clk = gk104_clk_new, |
151abd44 | 1670 | .devinit = gf100_devinit_new, |
03c8952f | 1671 | .fb = gk104_fb_new, |
c5fcafa5 | 1672 | .fuse = gf100_fuse_new, |
2ea7249f | 1673 | .gpio = gk104_gpio_new, |
49bd8da5 | 1674 | .i2c = gk104_i2c_new, |
551d3417 | 1675 | .ibus = gk104_ibus_new, |
b71c0892 | 1676 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1677 | .imem = nv50_instmem_new, |
70bc7182 | 1678 | .ltc = gk104_ltc_new, |
33537d6f | 1679 | .mc = gk104_mc_new, |
c9582455 | 1680 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1681 | .mxm = nv50_mxm_new, |
28c80605 | 1682 | .pci = gk104_pci_new, |
e2ca4e7d | 1683 | .pmu = gk104_pmu_new, |
57113c01 | 1684 | .therm = gf119_therm_new, |
31649ecf | 1685 | .timer = nv41_timer_new, |
fb3e9c61 | 1686 | .top = gk104_top_new, |
1531dbbb | 1687 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1688 | .ce[0] = gk104_ce_new, |
1689 | .ce[1] = gk104_ce_new, | |
1690 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1691 | .disp = gk104_disp_new, |
bd70563f | 1692 | .dma = gf119_dma_new, |
13de7f46 | 1693 | .fifo = gk104_fifo_new, |
c85ee6ca | 1694 | .gr = gk104_gr_new, |
53e60da4 BS |
1695 | .mspdec = gk104_mspdec_new, |
1696 | .msppp = gf100_msppp_new, | |
1697 | .msvld = gk104_msvld_new, | |
97070f23 | 1698 | .pm = gk104_pm_new, |
6f41c7c5 | 1699 | .sw = gf100_sw_new, |
6cf813fb BS |
1700 | }; |
1701 | ||
1702 | static const struct nvkm_device_chip | |
1703 | nve6_chipset = { | |
1704 | .name = "GK106", | |
32932281 | 1705 | .bar = gf100_bar_new, |
46484438 | 1706 | .bios = nvkm_bios_new, |
bb23f9d7 | 1707 | .bus = gf100_bus_new, |
6625f55c | 1708 | .clk = gk104_clk_new, |
151abd44 | 1709 | .devinit = gf100_devinit_new, |
03c8952f | 1710 | .fb = gk104_fb_new, |
c5fcafa5 | 1711 | .fuse = gf100_fuse_new, |
2ea7249f | 1712 | .gpio = gk104_gpio_new, |
49bd8da5 | 1713 | .i2c = gk104_i2c_new, |
551d3417 | 1714 | .ibus = gk104_ibus_new, |
b71c0892 | 1715 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1716 | .imem = nv50_instmem_new, |
70bc7182 | 1717 | .ltc = gk104_ltc_new, |
33537d6f | 1718 | .mc = gk104_mc_new, |
c9582455 | 1719 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1720 | .mxm = nv50_mxm_new, |
28c80605 | 1721 | .pci = gk104_pci_new, |
e2ca4e7d | 1722 | .pmu = gk104_pmu_new, |
57113c01 | 1723 | .therm = gf119_therm_new, |
31649ecf | 1724 | .timer = nv41_timer_new, |
fb3e9c61 | 1725 | .top = gk104_top_new, |
1531dbbb | 1726 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1727 | .ce[0] = gk104_ce_new, |
1728 | .ce[1] = gk104_ce_new, | |
1729 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1730 | .disp = gk104_disp_new, |
bd70563f | 1731 | .dma = gf119_dma_new, |
13de7f46 | 1732 | .fifo = gk104_fifo_new, |
c85ee6ca | 1733 | .gr = gk104_gr_new, |
53e60da4 BS |
1734 | .mspdec = gk104_mspdec_new, |
1735 | .msppp = gf100_msppp_new, | |
1736 | .msvld = gk104_msvld_new, | |
97070f23 | 1737 | .pm = gk104_pm_new, |
6f41c7c5 | 1738 | .sw = gf100_sw_new, |
6cf813fb BS |
1739 | }; |
1740 | ||
1741 | static const struct nvkm_device_chip | |
1742 | nve7_chipset = { | |
1743 | .name = "GK107", | |
32932281 | 1744 | .bar = gf100_bar_new, |
46484438 | 1745 | .bios = nvkm_bios_new, |
bb23f9d7 | 1746 | .bus = gf100_bus_new, |
6625f55c | 1747 | .clk = gk104_clk_new, |
151abd44 | 1748 | .devinit = gf100_devinit_new, |
03c8952f | 1749 | .fb = gk104_fb_new, |
c5fcafa5 | 1750 | .fuse = gf100_fuse_new, |
2ea7249f | 1751 | .gpio = gk104_gpio_new, |
49bd8da5 | 1752 | .i2c = gk104_i2c_new, |
551d3417 | 1753 | .ibus = gk104_ibus_new, |
b71c0892 | 1754 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1755 | .imem = nv50_instmem_new, |
70bc7182 | 1756 | .ltc = gk104_ltc_new, |
33537d6f | 1757 | .mc = gk104_mc_new, |
c9582455 | 1758 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1759 | .mxm = nv50_mxm_new, |
28c80605 | 1760 | .pci = gk104_pci_new, |
3c9aca31 | 1761 | .pmu = gk104_pmu_new, |
57113c01 | 1762 | .therm = gf119_therm_new, |
31649ecf | 1763 | .timer = nv41_timer_new, |
fb3e9c61 | 1764 | .top = gk104_top_new, |
1531dbbb | 1765 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1766 | .ce[0] = gk104_ce_new, |
1767 | .ce[1] = gk104_ce_new, | |
1768 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1769 | .disp = gk104_disp_new, |
bd70563f | 1770 | .dma = gf119_dma_new, |
13de7f46 | 1771 | .fifo = gk104_fifo_new, |
c85ee6ca | 1772 | .gr = gk104_gr_new, |
53e60da4 BS |
1773 | .mspdec = gk104_mspdec_new, |
1774 | .msppp = gf100_msppp_new, | |
1775 | .msvld = gk104_msvld_new, | |
97070f23 | 1776 | .pm = gk104_pm_new, |
6f41c7c5 | 1777 | .sw = gf100_sw_new, |
6cf813fb BS |
1778 | }; |
1779 | ||
1780 | static const struct nvkm_device_chip | |
1781 | nvea_chipset = { | |
1782 | .name = "GK20A", | |
32932281 | 1783 | .bar = gk20a_bar_new, |
bb23f9d7 | 1784 | .bus = gf100_bus_new, |
6625f55c | 1785 | .clk = gk20a_clk_new, |
03c8952f | 1786 | .fb = gk20a_fb_new, |
c5fcafa5 | 1787 | .fuse = gf100_fuse_new, |
551d3417 | 1788 | .ibus = gk20a_ibus_new, |
b7a2bc18 | 1789 | .imem = gk20a_instmem_new, |
70bc7182 | 1790 | .ltc = gk104_ltc_new, |
54dcadd5 | 1791 | .mc = gk20a_mc_new, |
c9582455 | 1792 | .mmu = gf100_mmu_new, |
e2ca4e7d | 1793 | .pmu = gk20a_pmu_new, |
31649ecf | 1794 | .timer = gk20a_timer_new, |
fb3e9c61 | 1795 | .top = gk104_top_new, |
437b2296 | 1796 | .volt = gk20a_volt_new, |
e5b31ca6 | 1797 | .ce[2] = gk104_ce_new, |
bd70563f | 1798 | .dma = gf119_dma_new, |
13de7f46 | 1799 | .fifo = gk20a_fifo_new, |
c85ee6ca | 1800 | .gr = gk20a_gr_new, |
97070f23 | 1801 | .pm = gk104_pm_new, |
6f41c7c5 | 1802 | .sw = gf100_sw_new, |
6cf813fb BS |
1803 | }; |
1804 | ||
1805 | static const struct nvkm_device_chip | |
1806 | nvf0_chipset = { | |
1807 | .name = "GK110", | |
32932281 | 1808 | .bar = gf100_bar_new, |
46484438 | 1809 | .bios = nvkm_bios_new, |
bb23f9d7 | 1810 | .bus = gf100_bus_new, |
6625f55c | 1811 | .clk = gk104_clk_new, |
151abd44 | 1812 | .devinit = gf100_devinit_new, |
03c8952f | 1813 | .fb = gk104_fb_new, |
c5fcafa5 | 1814 | .fuse = gf100_fuse_new, |
2ea7249f | 1815 | .gpio = gk104_gpio_new, |
49bd8da5 | 1816 | .i2c = gk104_i2c_new, |
551d3417 | 1817 | .ibus = gk104_ibus_new, |
b71c0892 | 1818 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1819 | .imem = nv50_instmem_new, |
70bc7182 | 1820 | .ltc = gk104_ltc_new, |
33537d6f | 1821 | .mc = gk104_mc_new, |
c9582455 | 1822 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1823 | .mxm = nv50_mxm_new, |
28c80605 | 1824 | .pci = gk104_pci_new, |
e2ca4e7d | 1825 | .pmu = gk110_pmu_new, |
57113c01 | 1826 | .therm = gf119_therm_new, |
31649ecf | 1827 | .timer = nv41_timer_new, |
fb3e9c61 | 1828 | .top = gk104_top_new, |
1531dbbb | 1829 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1830 | .ce[0] = gk104_ce_new, |
1831 | .ce[1] = gk104_ce_new, | |
1832 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1833 | .disp = gk110_disp_new, |
bd70563f | 1834 | .dma = gf119_dma_new, |
63f8c9b7 | 1835 | .fifo = gk110_fifo_new, |
c85ee6ca | 1836 | .gr = gk110_gr_new, |
53e60da4 BS |
1837 | .mspdec = gk104_mspdec_new, |
1838 | .msppp = gf100_msppp_new, | |
1839 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1840 | .sw = gf100_sw_new, |
6cf813fb BS |
1841 | }; |
1842 | ||
1843 | static const struct nvkm_device_chip | |
1844 | nvf1_chipset = { | |
1845 | .name = "GK110B", | |
32932281 | 1846 | .bar = gf100_bar_new, |
46484438 | 1847 | .bios = nvkm_bios_new, |
bb23f9d7 | 1848 | .bus = gf100_bus_new, |
6625f55c | 1849 | .clk = gk104_clk_new, |
151abd44 | 1850 | .devinit = gf100_devinit_new, |
03c8952f | 1851 | .fb = gk104_fb_new, |
c5fcafa5 | 1852 | .fuse = gf100_fuse_new, |
2ea7249f | 1853 | .gpio = gk104_gpio_new, |
49bd8da5 | 1854 | .i2c = gf119_i2c_new, |
551d3417 | 1855 | .ibus = gk104_ibus_new, |
b71c0892 | 1856 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1857 | .imem = nv50_instmem_new, |
70bc7182 | 1858 | .ltc = gk104_ltc_new, |
33537d6f | 1859 | .mc = gk104_mc_new, |
c9582455 | 1860 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1861 | .mxm = nv50_mxm_new, |
28c80605 | 1862 | .pci = gk104_pci_new, |
e2ca4e7d | 1863 | .pmu = gk110_pmu_new, |
57113c01 | 1864 | .therm = gf119_therm_new, |
31649ecf | 1865 | .timer = nv41_timer_new, |
fb3e9c61 | 1866 | .top = gk104_top_new, |
1531dbbb | 1867 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1868 | .ce[0] = gk104_ce_new, |
1869 | .ce[1] = gk104_ce_new, | |
1870 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1871 | .disp = gk110_disp_new, |
bd70563f | 1872 | .dma = gf119_dma_new, |
63f8c9b7 | 1873 | .fifo = gk110_fifo_new, |
c85ee6ca | 1874 | .gr = gk110b_gr_new, |
53e60da4 BS |
1875 | .mspdec = gk104_mspdec_new, |
1876 | .msppp = gf100_msppp_new, | |
1877 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1878 | .sw = gf100_sw_new, |
6cf813fb BS |
1879 | }; |
1880 | ||
1881 | static const struct nvkm_device_chip | |
1882 | nv106_chipset = { | |
1883 | .name = "GK208B", | |
32932281 | 1884 | .bar = gf100_bar_new, |
46484438 | 1885 | .bios = nvkm_bios_new, |
bb23f9d7 | 1886 | .bus = gf100_bus_new, |
6625f55c | 1887 | .clk = gk104_clk_new, |
151abd44 | 1888 | .devinit = gf100_devinit_new, |
03c8952f | 1889 | .fb = gk104_fb_new, |
c5fcafa5 | 1890 | .fuse = gf100_fuse_new, |
2ea7249f | 1891 | .gpio = gk104_gpio_new, |
49bd8da5 | 1892 | .i2c = gk104_i2c_new, |
551d3417 | 1893 | .ibus = gk104_ibus_new, |
b71c0892 | 1894 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1895 | .imem = nv50_instmem_new, |
70bc7182 | 1896 | .ltc = gk104_ltc_new, |
54dcadd5 | 1897 | .mc = gk20a_mc_new, |
c9582455 | 1898 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1899 | .mxm = nv50_mxm_new, |
28c80605 | 1900 | .pci = gk104_pci_new, |
e2ca4e7d | 1901 | .pmu = gk208_pmu_new, |
57113c01 | 1902 | .therm = gf119_therm_new, |
31649ecf | 1903 | .timer = nv41_timer_new, |
fb3e9c61 | 1904 | .top = gk104_top_new, |
1531dbbb | 1905 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1906 | .ce[0] = gk104_ce_new, |
1907 | .ce[1] = gk104_ce_new, | |
1908 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1909 | .disp = gk110_disp_new, |
bd70563f | 1910 | .dma = gf119_dma_new, |
13de7f46 | 1911 | .fifo = gk208_fifo_new, |
c85ee6ca | 1912 | .gr = gk208_gr_new, |
53e60da4 BS |
1913 | .mspdec = gk104_mspdec_new, |
1914 | .msppp = gf100_msppp_new, | |
1915 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1916 | .sw = gf100_sw_new, |
6cf813fb BS |
1917 | }; |
1918 | ||
1919 | static const struct nvkm_device_chip | |
1920 | nv108_chipset = { | |
1921 | .name = "GK208", | |
32932281 | 1922 | .bar = gf100_bar_new, |
46484438 | 1923 | .bios = nvkm_bios_new, |
bb23f9d7 | 1924 | .bus = gf100_bus_new, |
6625f55c | 1925 | .clk = gk104_clk_new, |
151abd44 | 1926 | .devinit = gf100_devinit_new, |
03c8952f | 1927 | .fb = gk104_fb_new, |
c5fcafa5 | 1928 | .fuse = gf100_fuse_new, |
2ea7249f | 1929 | .gpio = gk104_gpio_new, |
49bd8da5 | 1930 | .i2c = gk104_i2c_new, |
551d3417 | 1931 | .ibus = gk104_ibus_new, |
b71c0892 | 1932 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1933 | .imem = nv50_instmem_new, |
70bc7182 | 1934 | .ltc = gk104_ltc_new, |
54dcadd5 | 1935 | .mc = gk20a_mc_new, |
c9582455 | 1936 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1937 | .mxm = nv50_mxm_new, |
28c80605 | 1938 | .pci = gk104_pci_new, |
e2ca4e7d | 1939 | .pmu = gk208_pmu_new, |
57113c01 | 1940 | .therm = gf119_therm_new, |
31649ecf | 1941 | .timer = nv41_timer_new, |
fb3e9c61 | 1942 | .top = gk104_top_new, |
1531dbbb | 1943 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1944 | .ce[0] = gk104_ce_new, |
1945 | .ce[1] = gk104_ce_new, | |
1946 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1947 | .disp = gk110_disp_new, |
bd70563f | 1948 | .dma = gf119_dma_new, |
13de7f46 | 1949 | .fifo = gk208_fifo_new, |
c85ee6ca | 1950 | .gr = gk208_gr_new, |
53e60da4 BS |
1951 | .mspdec = gk104_mspdec_new, |
1952 | .msppp = gf100_msppp_new, | |
1953 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1954 | .sw = gf100_sw_new, |
6cf813fb BS |
1955 | }; |
1956 | ||
1957 | static const struct nvkm_device_chip | |
1958 | nv117_chipset = { | |
1959 | .name = "GM107", | |
32932281 | 1960 | .bar = gf100_bar_new, |
46484438 | 1961 | .bios = nvkm_bios_new, |
bb23f9d7 | 1962 | .bus = gf100_bus_new, |
6625f55c | 1963 | .clk = gk104_clk_new, |
151abd44 | 1964 | .devinit = gm107_devinit_new, |
03c8952f | 1965 | .fb = gm107_fb_new, |
c5fcafa5 | 1966 | .fuse = gm107_fuse_new, |
2ea7249f | 1967 | .gpio = gk104_gpio_new, |
49bd8da5 | 1968 | .i2c = gf119_i2c_new, |
551d3417 | 1969 | .ibus = gk104_ibus_new, |
b71c0892 | 1970 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1971 | .imem = nv50_instmem_new, |
70bc7182 | 1972 | .ltc = gm107_ltc_new, |
54dcadd5 | 1973 | .mc = gk20a_mc_new, |
c9582455 | 1974 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1975 | .mxm = nv50_mxm_new, |
28c80605 | 1976 | .pci = gk104_pci_new, |
e2ca4e7d | 1977 | .pmu = gm107_pmu_new, |
57113c01 | 1978 | .therm = gm107_therm_new, |
31649ecf | 1979 | .timer = gk20a_timer_new, |
fb3e9c61 | 1980 | .top = gk104_top_new, |
dc47700f | 1981 | .volt = gk104_volt_new, |
253a03f0 BS |
1982 | .ce[0] = gm107_ce_new, |
1983 | .ce[2] = gm107_ce_new, | |
70aa8670 | 1984 | .disp = gm107_disp_new, |
bd70563f | 1985 | .dma = gf119_dma_new, |
7c4f87c9 | 1986 | .fifo = gm107_fifo_new, |
c85ee6ca | 1987 | .gr = gm107_gr_new, |
6f41c7c5 | 1988 | .sw = gf100_sw_new, |
6cf813fb BS |
1989 | }; |
1990 | ||
f9e20294 BS |
1991 | static const struct nvkm_device_chip |
1992 | nv118_chipset = { | |
1993 | .name = "GM108", | |
1994 | .bar = gf100_bar_new, | |
1995 | .bios = nvkm_bios_new, | |
1996 | .bus = gf100_bus_new, | |
1997 | .clk = gk104_clk_new, | |
1998 | .devinit = gm107_devinit_new, | |
1999 | .fb = gm107_fb_new, | |
2000 | .fuse = gm107_fuse_new, | |
2001 | .gpio = gk104_gpio_new, | |
2002 | .i2c = gf119_i2c_new, | |
2003 | .ibus = gk104_ibus_new, | |
2004 | .iccsense = gf100_iccsense_new, | |
2005 | .imem = nv50_instmem_new, | |
2006 | .ltc = gm107_ltc_new, | |
2007 | .mc = gk20a_mc_new, | |
2008 | .mmu = gf100_mmu_new, | |
2009 | .mxm = nv50_mxm_new, | |
2010 | .pci = gk104_pci_new, | |
2011 | .pmu = gm107_pmu_new, | |
2012 | .therm = gm107_therm_new, | |
2013 | .timer = gk20a_timer_new, | |
2014 | .top = gk104_top_new, | |
2015 | .volt = gk104_volt_new, | |
2016 | .ce[0] = gm107_ce_new, | |
2017 | .ce[2] = gm107_ce_new, | |
2018 | .disp = gm107_disp_new, | |
2019 | .dma = gf119_dma_new, | |
2020 | .fifo = gm107_fifo_new, | |
2021 | .gr = gm107_gr_new, | |
2022 | .sw = gf100_sw_new, | |
2023 | }; | |
2024 | ||
2ed95a4c BS |
2025 | static const struct nvkm_device_chip |
2026 | nv120_chipset = { | |
2027 | .name = "GM200", | |
2028 | .bar = gf100_bar_new, | |
2029 | .bios = nvkm_bios_new, | |
2030 | .bus = gf100_bus_new, | |
db1eb528 | 2031 | .devinit = gm200_devinit_new, |
e976278a | 2032 | .fb = gm200_fb_new, |
2ed95a4c BS |
2033 | .fuse = gm107_fuse_new, |
2034 | .gpio = gk104_gpio_new, | |
db1eb528 BS |
2035 | .i2c = gm200_i2c_new, |
2036 | .ibus = gm200_ibus_new, | |
b71c0892 | 2037 | .iccsense = gf100_iccsense_new, |
2ed95a4c | 2038 | .imem = nv50_instmem_new, |
db1eb528 | 2039 | .ltc = gm200_ltc_new, |
2ed95a4c BS |
2040 | .mc = gk20a_mc_new, |
2041 | .mmu = gf100_mmu_new, | |
2042 | .mxm = nv50_mxm_new, | |
2043 | .pci = gk104_pci_new, | |
2044 | .pmu = gm107_pmu_new, | |
9cc45521 | 2045 | .secboot = gm200_secboot_new, |
2ed95a4c | 2046 | .timer = gk20a_timer_new, |
fb3e9c61 | 2047 | .top = gk104_top_new, |
2ed95a4c | 2048 | .volt = gk104_volt_new, |
db1eb528 BS |
2049 | .ce[0] = gm200_ce_new, |
2050 | .ce[1] = gm200_ce_new, | |
2051 | .ce[2] = gm200_ce_new, | |
2052 | .disp = gm200_disp_new, | |
2ed95a4c | 2053 | .dma = gf119_dma_new, |
db1eb528 | 2054 | .fifo = gm200_fifo_new, |
96fc422c | 2055 | .gr = gm200_gr_new, |
2ed95a4c BS |
2056 | .sw = gf100_sw_new, |
2057 | }; | |
2058 | ||
6cf813fb BS |
2059 | static const struct nvkm_device_chip |
2060 | nv124_chipset = { | |
2061 | .name = "GM204", | |
32932281 | 2062 | .bar = gf100_bar_new, |
46484438 | 2063 | .bios = nvkm_bios_new, |
bb23f9d7 | 2064 | .bus = gf100_bus_new, |
db1eb528 | 2065 | .devinit = gm200_devinit_new, |
e976278a | 2066 | .fb = gm200_fb_new, |
c5fcafa5 | 2067 | .fuse = gm107_fuse_new, |
2ea7249f | 2068 | .gpio = gk104_gpio_new, |
db1eb528 BS |
2069 | .i2c = gm200_i2c_new, |
2070 | .ibus = gm200_ibus_new, | |
b71c0892 | 2071 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 2072 | .imem = nv50_instmem_new, |
db1eb528 | 2073 | .ltc = gm200_ltc_new, |
54dcadd5 | 2074 | .mc = gk20a_mc_new, |
c9582455 | 2075 | .mmu = gf100_mmu_new, |
a4f7bd36 | 2076 | .mxm = nv50_mxm_new, |
28c80605 | 2077 | .pci = gk104_pci_new, |
e2ca4e7d | 2078 | .pmu = gm107_pmu_new, |
9cc45521 | 2079 | .secboot = gm200_secboot_new, |
31649ecf | 2080 | .timer = gk20a_timer_new, |
fb3e9c61 | 2081 | .top = gk104_top_new, |
24580d1c | 2082 | .volt = gk104_volt_new, |
db1eb528 BS |
2083 | .ce[0] = gm200_ce_new, |
2084 | .ce[1] = gm200_ce_new, | |
2085 | .ce[2] = gm200_ce_new, | |
2086 | .disp = gm200_disp_new, | |
bd70563f | 2087 | .dma = gf119_dma_new, |
db1eb528 | 2088 | .fifo = gm200_fifo_new, |
9ec28052 | 2089 | .gr = gm200_gr_new, |
6f41c7c5 | 2090 | .sw = gf100_sw_new, |
6cf813fb BS |
2091 | }; |
2092 | ||
2093 | static const struct nvkm_device_chip | |
2094 | nv126_chipset = { | |
2095 | .name = "GM206", | |
32932281 | 2096 | .bar = gf100_bar_new, |
46484438 | 2097 | .bios = nvkm_bios_new, |
bb23f9d7 | 2098 | .bus = gf100_bus_new, |
db1eb528 | 2099 | .devinit = gm200_devinit_new, |
e976278a | 2100 | .fb = gm200_fb_new, |
c5fcafa5 | 2101 | .fuse = gm107_fuse_new, |
2ea7249f | 2102 | .gpio = gk104_gpio_new, |
db1eb528 BS |
2103 | .i2c = gm200_i2c_new, |
2104 | .ibus = gm200_ibus_new, | |
b71c0892 | 2105 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 2106 | .imem = nv50_instmem_new, |
db1eb528 | 2107 | .ltc = gm200_ltc_new, |
54dcadd5 | 2108 | .mc = gk20a_mc_new, |
c9582455 | 2109 | .mmu = gf100_mmu_new, |
a4f7bd36 | 2110 | .mxm = nv50_mxm_new, |
28c80605 | 2111 | .pci = gk104_pci_new, |
e2ca4e7d | 2112 | .pmu = gm107_pmu_new, |
9cc45521 | 2113 | .secboot = gm200_secboot_new, |
31649ecf | 2114 | .timer = gk20a_timer_new, |
fb3e9c61 | 2115 | .top = gk104_top_new, |
24580d1c | 2116 | .volt = gk104_volt_new, |
db1eb528 BS |
2117 | .ce[0] = gm200_ce_new, |
2118 | .ce[1] = gm200_ce_new, | |
2119 | .ce[2] = gm200_ce_new, | |
2120 | .disp = gm200_disp_new, | |
bd70563f | 2121 | .dma = gf119_dma_new, |
db1eb528 | 2122 | .fifo = gm200_fifo_new, |
7d31cb7c | 2123 | .gr = gm200_gr_new, |
6f41c7c5 | 2124 | .sw = gf100_sw_new, |
6cf813fb BS |
2125 | }; |
2126 | ||
2127 | static const struct nvkm_device_chip | |
2128 | nv12b_chipset = { | |
2129 | .name = "GM20B", | |
32932281 | 2130 | .bar = gk20a_bar_new, |
bb23f9d7 | 2131 | .bus = gf100_bus_new, |
52829d4f | 2132 | .clk = gm20b_clk_new, |
03c8952f | 2133 | .fb = gk20a_fb_new, |
c5fcafa5 | 2134 | .fuse = gm107_fuse_new, |
551d3417 | 2135 | .ibus = gk20a_ibus_new, |
b7a2bc18 | 2136 | .imem = gk20a_instmem_new, |
db1eb528 | 2137 | .ltc = gm200_ltc_new, |
54dcadd5 | 2138 | .mc = gk20a_mc_new, |
c9582455 | 2139 | .mmu = gf100_mmu_new, |
923f1bd2 | 2140 | .secboot = gm20b_secboot_new, |
31649ecf | 2141 | .timer = gk20a_timer_new, |
fb3e9c61 | 2142 | .top = gk104_top_new, |
db1eb528 | 2143 | .ce[2] = gm200_ce_new, |
71757abf | 2144 | .volt = gm20b_volt_new, |
bd70563f | 2145 | .dma = gf119_dma_new, |
13de7f46 | 2146 | .fifo = gm20b_fifo_new, |
c85ee6ca | 2147 | .gr = gm20b_gr_new, |
6f41c7c5 | 2148 | .sw = gf100_sw_new, |
6cf813fb BS |
2149 | }; |
2150 | ||
7f53abdb BS |
2151 | static const struct nvkm_device_chip |
2152 | nv130_chipset = { | |
2153 | .name = "GP100", | |
7481d055 | 2154 | .bios = nvkm_bios_new, |
c7b511ba | 2155 | .devinit = gm200_devinit_new, |
7ff51f82 | 2156 | .fb = gp100_fb_new, |
0cbe26f0 | 2157 | .imem = nv50_instmem_new, |
be61c54c | 2158 | .mc = gp100_mc_new, |
45aa4d07 | 2159 | .pci = gp100_pci_new, |
4eeb039b | 2160 | .timer = gk20a_timer_new, |
51012a39 | 2161 | .top = gk104_top_new, |
7f53abdb BS |
2162 | }; |
2163 | ||
79ca2770 | 2164 | static int |
9719047b BS |
2165 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, |
2166 | struct nvkm_notify *notify) | |
79ca2770 BS |
2167 | { |
2168 | if (!WARN_ON(size != 0)) { | |
2169 | notify->size = 0; | |
2170 | notify->types = 1; | |
2171 | notify->index = 0; | |
2172 | return 0; | |
2173 | } | |
2174 | return -EINVAL; | |
2175 | } | |
2176 | ||
2177 | static const struct nvkm_event_func | |
9719047b BS |
2178 | nvkm_device_event_func = { |
2179 | .ctor = nvkm_device_event_ctor, | |
79ca2770 BS |
2180 | }; |
2181 | ||
6cf813fb BS |
2182 | struct nvkm_subdev * |
2183 | nvkm_device_subdev(struct nvkm_device *device, int index) | |
2184 | { | |
2185 | struct nvkm_engine *engine; | |
2186 | ||
2187 | if (device->disable_mask & (1ULL << index)) | |
2188 | return NULL; | |
2189 | ||
2190 | switch (index) { | |
68f3f702 | 2191 | #define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break |
dc06e366 MP |
2192 | _(BAR , device->bar , &device->bar->subdev); |
2193 | _(VBIOS , device->bios , &device->bios->subdev); | |
2194 | _(BUS , device->bus , &device->bus->subdev); | |
2195 | _(CLK , device->clk , &device->clk->subdev); | |
2196 | _(DEVINIT , device->devinit , &device->devinit->subdev); | |
2197 | _(FB , device->fb , &device->fb->subdev); | |
2198 | _(FUSE , device->fuse , &device->fuse->subdev); | |
2199 | _(GPIO , device->gpio , &device->gpio->subdev); | |
2200 | _(I2C , device->i2c , &device->i2c->subdev); | |
2201 | _(IBUS , device->ibus , device->ibus); | |
2202 | _(ICCSENSE, device->iccsense, &device->iccsense->subdev); | |
2203 | _(INSTMEM , device->imem , &device->imem->subdev); | |
2204 | _(LTC , device->ltc , &device->ltc->subdev); | |
2205 | _(MC , device->mc , &device->mc->subdev); | |
2206 | _(MMU , device->mmu , &device->mmu->subdev); | |
2207 | _(MXM , device->mxm , device->mxm); | |
2208 | _(PCI , device->pci , &device->pci->subdev); | |
2209 | _(PMU , device->pmu , &device->pmu->subdev); | |
2210 | _(SECBOOT , device->secboot , &device->secboot->subdev); | |
2211 | _(THERM , device->therm , &device->therm->subdev); | |
2212 | _(TIMER , device->timer , &device->timer->subdev); | |
eaebfcc3 | 2213 | _(TOP , device->top , &device->top->subdev); |
dc06e366 | 2214 | _(VOLT , device->volt , &device->volt->subdev); |
6cf813fb BS |
2215 | #undef _ |
2216 | default: | |
2217 | engine = nvkm_device_engine(device, index); | |
2218 | if (engine) | |
2219 | return &engine->subdev; | |
2220 | break; | |
2221 | } | |
2222 | return NULL; | |
2223 | } | |
2224 | ||
2225 | struct nvkm_engine * | |
2226 | nvkm_device_engine(struct nvkm_device *device, int index) | |
2227 | { | |
2228 | if (device->disable_mask & (1ULL << index)) | |
2229 | return NULL; | |
2230 | ||
2231 | switch (index) { | |
68f3f702 | 2232 | #define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break |
294af04b BS |
2233 | _(BSP , device->bsp , device->bsp); |
2234 | _(CE0 , device->ce[0] , device->ce[0]); | |
2235 | _(CE1 , device->ce[1] , device->ce[1]); | |
2236 | _(CE2 , device->ce[2] , device->ce[2]); | |
34bf50cd BS |
2237 | _(CE3 , device->ce[3] , device->ce[3]); |
2238 | _(CE4 , device->ce[4] , device->ce[4]); | |
2239 | _(CE5 , device->ce[5] , device->ce[5]); | |
294af04b BS |
2240 | _(CIPHER , device->cipher , device->cipher); |
2241 | _(DISP , device->disp , &device->disp->engine); | |
2242 | _(DMAOBJ , device->dma , &device->dma->engine); | |
2243 | _(FIFO , device->fifo , &device->fifo->engine); | |
2244 | _(GR , device->gr , &device->gr->engine); | |
2245 | _(IFB , device->ifb , device->ifb); | |
2246 | _(ME , device->me , device->me); | |
2247 | _(MPEG , device->mpeg , device->mpeg); | |
2248 | _(MSENC , device->msenc , device->msenc); | |
2249 | _(MSPDEC , device->mspdec , device->mspdec); | |
2250 | _(MSPPP , device->msppp , device->msppp); | |
2251 | _(MSVLD , device->msvld , device->msvld); | |
2252 | _(NVENC0 , device->nvenc[0], device->nvenc[0]); | |
2253 | _(NVENC1 , device->nvenc[1], device->nvenc[1]); | |
cb7b5ea9 | 2254 | _(NVENC2 , device->nvenc[2], device->nvenc[2]); |
3545b425 | 2255 | _(NVDEC , device->nvdec , device->nvdec); |
294af04b BS |
2256 | _(PM , device->pm , &device->pm->engine); |
2257 | _(SEC , device->sec , device->sec); | |
2258 | _(SW , device->sw , &device->sw->engine); | |
2259 | _(VIC , device->vic , device->vic); | |
2260 | _(VP , device->vp , device->vp); | |
6cf813fb BS |
2261 | #undef _ |
2262 | default: | |
2263 | WARN_ON(1); | |
2264 | break; | |
2265 | } | |
2266 | return NULL; | |
2267 | } | |
2268 | ||
a1e88736 BS |
2269 | int |
2270 | nvkm_device_fini(struct nvkm_device *device, bool suspend) | |
066a5d09 | 2271 | { |
6cf813fb BS |
2272 | const char *action = suspend ? "suspend" : "fini"; |
2273 | struct nvkm_subdev *subdev; | |
10caad33 | 2274 | int ret, i; |
6cf813fb BS |
2275 | s64 time; |
2276 | ||
2277 | nvdev_trace(device, "%s running...\n", action); | |
2278 | time = ktime_to_us(ktime_get()); | |
2279 | ||
2280 | nvkm_acpi_fini(device); | |
10caad33 | 2281 | |
68f3f702 | 2282 | for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { |
6cf813fb BS |
2283 | if ((subdev = nvkm_device_subdev(device, i))) { |
2284 | ret = nvkm_subdev_fini(subdev, suspend); | |
2285 | if (ret && suspend) | |
2286 | goto fail; | |
10caad33 BS |
2287 | } |
2288 | } | |
2289 | ||
7974dd1b BS |
2290 | |
2291 | if (device->func->fini) | |
2292 | device->func->fini(device, suspend); | |
6cf813fb BS |
2293 | |
2294 | time = ktime_to_us(ktime_get()) - time; | |
2295 | nvdev_trace(device, "%s completed in %lldus...\n", action, time); | |
2296 | return 0; | |
2297 | ||
10caad33 | 2298 | fail: |
6cf813fb BS |
2299 | do { |
2300 | if ((subdev = nvkm_device_subdev(device, i))) { | |
2301 | int rret = nvkm_subdev_init(subdev); | |
2302 | if (rret) | |
2303 | nvkm_fatal(subdev, "failed restart, %d\n", ret); | |
10caad33 | 2304 | } |
68f3f702 | 2305 | } while (++i < NVKM_SUBDEV_NR); |
10caad33 | 2306 | |
6cf813fb | 2307 | nvdev_trace(device, "%s failed with %d\n", action, ret); |
10caad33 | 2308 | return ret; |
066a5d09 BS |
2309 | } |
2310 | ||
6cf813fb | 2311 | static int |
7974dd1b BS |
2312 | nvkm_device_preinit(struct nvkm_device *device) |
2313 | { | |
6cf813fb BS |
2314 | struct nvkm_subdev *subdev; |
2315 | int ret, i; | |
7974dd1b BS |
2316 | s64 time; |
2317 | ||
2318 | nvdev_trace(device, "preinit running...\n"); | |
2319 | time = ktime_to_us(ktime_get()); | |
2320 | ||
2321 | if (device->func->preinit) { | |
2322 | ret = device->func->preinit(device); | |
2323 | if (ret) | |
2324 | goto fail; | |
2325 | } | |
2326 | ||
68f3f702 | 2327 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
6cf813fb BS |
2328 | if ((subdev = nvkm_device_subdev(device, i))) { |
2329 | ret = nvkm_subdev_preinit(subdev); | |
2330 | if (ret) | |
2331 | goto fail; | |
2332 | } | |
2333 | } | |
2334 | ||
8de65bd0 BS |
2335 | ret = nvkm_devinit_post(device->devinit, &device->disable_mask); |
2336 | if (ret) | |
2337 | goto fail; | |
6cf813fb | 2338 | |
7974dd1b BS |
2339 | time = ktime_to_us(ktime_get()) - time; |
2340 | nvdev_trace(device, "preinit completed in %lldus\n", time); | |
2341 | return 0; | |
2342 | ||
2343 | fail: | |
2344 | nvdev_error(device, "preinit failed with %d\n", ret); | |
2345 | return ret; | |
2346 | } | |
2347 | ||
a1e88736 BS |
2348 | int |
2349 | nvkm_device_init(struct nvkm_device *device) | |
066a5d09 | 2350 | { |
6cf813fb | 2351 | struct nvkm_subdev *subdev; |
68f3f702 | 2352 | int ret, i; |
6cf813fb | 2353 | s64 time; |
ed76a870 | 2354 | |
7974dd1b BS |
2355 | ret = nvkm_device_preinit(device); |
2356 | if (ret) | |
2357 | return ret; | |
2358 | ||
6cf813fb BS |
2359 | nvkm_device_fini(device, false); |
2360 | ||
2361 | nvdev_trace(device, "init running...\n"); | |
2362 | time = ktime_to_us(ktime_get()); | |
10caad33 | 2363 | |
2b700825 BS |
2364 | if (device->func->init) { |
2365 | ret = device->func->init(device); | |
2366 | if (ret) | |
2367 | goto fail; | |
2368 | } | |
2369 | ||
68f3f702 BS |
2370 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
2371 | if ((subdev = nvkm_device_subdev(device, i))) { | |
2372 | ret = nvkm_subdev_init(subdev); | |
2373 | if (ret) | |
2b700825 | 2374 | goto fail_subdev; |
10caad33 BS |
2375 | } |
2376 | } | |
2377 | ||
6cf813fb BS |
2378 | nvkm_acpi_init(device); |
2379 | ||
2380 | time = ktime_to_us(ktime_get()) - time; | |
2381 | nvdev_trace(device, "init completed in %lldus\n", time); | |
2382 | return 0; | |
2383 | ||
2b700825 | 2384 | fail_subdev: |
6cf813fb BS |
2385 | do { |
2386 | if ((subdev = nvkm_device_subdev(device, i))) | |
2387 | nvkm_subdev_fini(subdev, false); | |
2388 | } while (--i >= 0); | |
10caad33 | 2389 | |
2b700825 | 2390 | fail: |
0529a46a AC |
2391 | nvkm_device_fini(device, false); |
2392 | ||
6cf813fb | 2393 | nvdev_error(device, "init failed with %d\n", ret); |
10caad33 | 2394 | return ret; |
066a5d09 BS |
2395 | } |
2396 | ||
e781dc8f BS |
2397 | void |
2398 | nvkm_device_del(struct nvkm_device **pdevice) | |
2399 | { | |
2400 | struct nvkm_device *device = *pdevice; | |
0ac9d210 | 2401 | int i; |
e781dc8f | 2402 | if (device) { |
e781dc8f | 2403 | mutex_lock(&nv_devices_mutex); |
6cf813fb | 2404 | device->disable_mask = 0; |
68f3f702 | 2405 | for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { |
6cf813fb BS |
2406 | struct nvkm_subdev *subdev = |
2407 | nvkm_device_subdev(device, i); | |
2408 | nvkm_subdev_del(&subdev); | |
2409 | } | |
0ac9d210 BS |
2410 | |
2411 | nvkm_event_fini(&device->event); | |
e781dc8f BS |
2412 | |
2413 | if (device->pri) | |
2414 | iounmap(device->pri); | |
0ac9d210 | 2415 | list_del(&device->head); |
7974dd1b BS |
2416 | |
2417 | if (device->func->dtor) | |
2418 | *pdevice = device->func->dtor(device); | |
0ac9d210 | 2419 | mutex_unlock(&nv_devices_mutex); |
e781dc8f | 2420 | |
7974dd1b | 2421 | kfree(*pdevice); |
e781dc8f BS |
2422 | *pdevice = NULL; |
2423 | } | |
2424 | } | |
2425 | ||
9274f4a9 | 2426 | int |
7974dd1b BS |
2427 | nvkm_device_ctor(const struct nvkm_device_func *func, |
2428 | const struct nvkm_device_quirk *quirk, | |
26c9e8ef | 2429 | struct device *dev, enum nvkm_device_type type, u64 handle, |
7974dd1b BS |
2430 | const char *name, const char *cfg, const char *dbg, |
2431 | bool detect, bool mmio, u64 subdev_mask, | |
2432 | struct nvkm_device *device) | |
9274f4a9 | 2433 | { |
6cf813fb | 2434 | struct nvkm_subdev *subdev; |
0ac9d210 BS |
2435 | u64 mmio_base, mmio_size; |
2436 | u32 boot0, strap; | |
2437 | void __iomem *map; | |
9274f4a9 | 2438 | int ret = -EEXIST; |
0ac9d210 | 2439 | int i; |
9274f4a9 BS |
2440 | |
2441 | mutex_lock(&nv_devices_mutex); | |
7974dd1b BS |
2442 | if (nvkm_device_find_locked(handle)) |
2443 | goto done; | |
9274f4a9 | 2444 | |
7974dd1b | 2445 | device->func = func; |
7974dd1b | 2446 | device->quirk = quirk; |
26c9e8ef BS |
2447 | device->dev = dev; |
2448 | device->type = type; | |
7974dd1b | 2449 | device->handle = handle; |
9274f4a9 BS |
2450 | device->cfgopt = cfg; |
2451 | device->dbgopt = dbg; | |
7974dd1b | 2452 | device->name = name; |
0d5dd3f3 | 2453 | list_add_tail(&device->head, &nv_devices); |
68f3f702 | 2454 | device->debug = nvkm_dbgopt(device->dbgopt, "device"); |
6cf813fb | 2455 | |
9719047b | 2456 | ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); |
0ac9d210 BS |
2457 | if (ret) |
2458 | goto done; | |
2459 | ||
7e8820fe BS |
2460 | mmio_base = device->func->resource_addr(device, 0); |
2461 | mmio_size = device->func->resource_size(device, 0); | |
0ac9d210 BS |
2462 | |
2463 | /* identify the chipset, and determine classes of subdev/engines */ | |
2464 | if (detect) { | |
2465 | map = ioremap(mmio_base, 0x102000); | |
2466 | if (ret = -ENOMEM, map == NULL) | |
2467 | goto done; | |
2468 | ||
2469 | /* switch mmio to cpu's native endianness */ | |
2470 | #ifndef __BIG_ENDIAN | |
2471 | if (ioread32_native(map + 0x000004) != 0x00000000) { | |
2472 | #else | |
2473 | if (ioread32_native(map + 0x000004) == 0x00000000) { | |
2474 | #endif | |
2475 | iowrite32_native(0x01000001, map + 0x000004); | |
2476 | ioread32_native(map); | |
2477 | } | |
2478 | ||
2479 | /* read boot0 and strapping information */ | |
2480 | boot0 = ioread32_native(map + 0x000000); | |
2481 | strap = ioread32_native(map + 0x101000); | |
2482 | iounmap(map); | |
2483 | ||
2484 | /* determine chipset and derive architecture from it */ | |
2485 | if ((boot0 & 0x1f000000) > 0) { | |
2486 | device->chipset = (boot0 & 0x1ff00000) >> 20; | |
2487 | device->chiprev = (boot0 & 0x000000ff); | |
2488 | switch (device->chipset & 0x1f0) { | |
2489 | case 0x010: { | |
2490 | if (0x461 & (1 << (device->chipset & 0xf))) | |
2491 | device->card_type = NV_10; | |
2492 | else | |
2493 | device->card_type = NV_11; | |
2494 | device->chiprev = 0x00; | |
2495 | break; | |
2496 | } | |
2497 | case 0x020: device->card_type = NV_20; break; | |
2498 | case 0x030: device->card_type = NV_30; break; | |
2499 | case 0x040: | |
2500 | case 0x060: device->card_type = NV_40; break; | |
2501 | case 0x050: | |
2502 | case 0x080: | |
2503 | case 0x090: | |
2504 | case 0x0a0: device->card_type = NV_50; break; | |
2505 | case 0x0c0: | |
2506 | case 0x0d0: device->card_type = NV_C0; break; | |
2507 | case 0x0e0: | |
2508 | case 0x0f0: | |
2509 | case 0x100: device->card_type = NV_E0; break; | |
2510 | case 0x110: | |
2511 | case 0x120: device->card_type = GM100; break; | |
7f53abdb | 2512 | case 0x130: device->card_type = GP100; break; |
0ac9d210 BS |
2513 | default: |
2514 | break; | |
2515 | } | |
2516 | } else | |
2517 | if ((boot0 & 0xff00fff0) == 0x20004000) { | |
2518 | if (boot0 & 0x00f00000) | |
2519 | device->chipset = 0x05; | |
2520 | else | |
2521 | device->chipset = 0x04; | |
2522 | device->card_type = NV_04; | |
2523 | } | |
2524 | ||
68f3f702 | 2525 | switch (device->chipset) { |
6cf813fb BS |
2526 | case 0x004: device->chip = &nv4_chipset; break; |
2527 | case 0x005: device->chip = &nv5_chipset; break; | |
2528 | case 0x010: device->chip = &nv10_chipset; break; | |
2529 | case 0x011: device->chip = &nv11_chipset; break; | |
2530 | case 0x015: device->chip = &nv15_chipset; break; | |
2531 | case 0x017: device->chip = &nv17_chipset; break; | |
2532 | case 0x018: device->chip = &nv18_chipset; break; | |
2533 | case 0x01a: device->chip = &nv1a_chipset; break; | |
2534 | case 0x01f: device->chip = &nv1f_chipset; break; | |
2535 | case 0x020: device->chip = &nv20_chipset; break; | |
2536 | case 0x025: device->chip = &nv25_chipset; break; | |
2537 | case 0x028: device->chip = &nv28_chipset; break; | |
2538 | case 0x02a: device->chip = &nv2a_chipset; break; | |
2539 | case 0x030: device->chip = &nv30_chipset; break; | |
2540 | case 0x031: device->chip = &nv31_chipset; break; | |
2541 | case 0x034: device->chip = &nv34_chipset; break; | |
2542 | case 0x035: device->chip = &nv35_chipset; break; | |
2543 | case 0x036: device->chip = &nv36_chipset; break; | |
2544 | case 0x040: device->chip = &nv40_chipset; break; | |
2545 | case 0x041: device->chip = &nv41_chipset; break; | |
2546 | case 0x042: device->chip = &nv42_chipset; break; | |
2547 | case 0x043: device->chip = &nv43_chipset; break; | |
2548 | case 0x044: device->chip = &nv44_chipset; break; | |
2549 | case 0x045: device->chip = &nv45_chipset; break; | |
2550 | case 0x046: device->chip = &nv46_chipset; break; | |
2551 | case 0x047: device->chip = &nv47_chipset; break; | |
2552 | case 0x049: device->chip = &nv49_chipset; break; | |
2553 | case 0x04a: device->chip = &nv4a_chipset; break; | |
2554 | case 0x04b: device->chip = &nv4b_chipset; break; | |
2555 | case 0x04c: device->chip = &nv4c_chipset; break; | |
2556 | case 0x04e: device->chip = &nv4e_chipset; break; | |
2557 | case 0x050: device->chip = &nv50_chipset; break; | |
2558 | case 0x063: device->chip = &nv63_chipset; break; | |
2559 | case 0x067: device->chip = &nv67_chipset; break; | |
2560 | case 0x068: device->chip = &nv68_chipset; break; | |
2561 | case 0x084: device->chip = &nv84_chipset; break; | |
2562 | case 0x086: device->chip = &nv86_chipset; break; | |
2563 | case 0x092: device->chip = &nv92_chipset; break; | |
2564 | case 0x094: device->chip = &nv94_chipset; break; | |
2565 | case 0x096: device->chip = &nv96_chipset; break; | |
2566 | case 0x098: device->chip = &nv98_chipset; break; | |
2567 | case 0x0a0: device->chip = &nva0_chipset; break; | |
2568 | case 0x0a3: device->chip = &nva3_chipset; break; | |
2569 | case 0x0a5: device->chip = &nva5_chipset; break; | |
2570 | case 0x0a8: device->chip = &nva8_chipset; break; | |
2571 | case 0x0aa: device->chip = &nvaa_chipset; break; | |
2572 | case 0x0ac: device->chip = &nvac_chipset; break; | |
2573 | case 0x0af: device->chip = &nvaf_chipset; break; | |
2574 | case 0x0c0: device->chip = &nvc0_chipset; break; | |
2575 | case 0x0c1: device->chip = &nvc1_chipset; break; | |
2576 | case 0x0c3: device->chip = &nvc3_chipset; break; | |
2577 | case 0x0c4: device->chip = &nvc4_chipset; break; | |
2578 | case 0x0c8: device->chip = &nvc8_chipset; break; | |
2579 | case 0x0ce: device->chip = &nvce_chipset; break; | |
2580 | case 0x0cf: device->chip = &nvcf_chipset; break; | |
2581 | case 0x0d7: device->chip = &nvd7_chipset; break; | |
2582 | case 0x0d9: device->chip = &nvd9_chipset; break; | |
2583 | case 0x0e4: device->chip = &nve4_chipset; break; | |
2584 | case 0x0e6: device->chip = &nve6_chipset; break; | |
2585 | case 0x0e7: device->chip = &nve7_chipset; break; | |
2586 | case 0x0ea: device->chip = &nvea_chipset; break; | |
2587 | case 0x0f0: device->chip = &nvf0_chipset; break; | |
2588 | case 0x0f1: device->chip = &nvf1_chipset; break; | |
2589 | case 0x106: device->chip = &nv106_chipset; break; | |
2590 | case 0x108: device->chip = &nv108_chipset; break; | |
2591 | case 0x117: device->chip = &nv117_chipset; break; | |
f9e20294 | 2592 | case 0x118: device->chip = &nv118_chipset; break; |
2ed95a4c | 2593 | case 0x120: device->chip = &nv120_chipset; break; |
6cf813fb BS |
2594 | case 0x124: device->chip = &nv124_chipset; break; |
2595 | case 0x126: device->chip = &nv126_chipset; break; | |
2596 | case 0x12b: device->chip = &nv12b_chipset; break; | |
7f53abdb | 2597 | case 0x130: device->chip = &nv130_chipset; break; |
6cf813fb | 2598 | default: |
0ac9d210 BS |
2599 | nvdev_error(device, "unknown chipset (%08x)\n", boot0); |
2600 | goto done; | |
2601 | } | |
2602 | ||
6cf813fb BS |
2603 | nvdev_info(device, "NVIDIA %s (%08x)\n", |
2604 | device->chip->name, boot0); | |
0ac9d210 BS |
2605 | |
2606 | /* determine frequency of timing crystal */ | |
2607 | if ( device->card_type <= NV_10 || device->chipset < 0x17 || | |
2608 | (device->chipset >= 0x20 && device->chipset < 0x25)) | |
2609 | strap &= 0x00000040; | |
2610 | else | |
2611 | strap &= 0x00400040; | |
2612 | ||
2613 | switch (strap) { | |
2614 | case 0x00000000: device->crystal = 13500; break; | |
2615 | case 0x00000040: device->crystal = 14318; break; | |
2616 | case 0x00400000: device->crystal = 27000; break; | |
2617 | case 0x00400040: device->crystal = 25000; break; | |
2618 | } | |
2619 | } else { | |
6cf813fb | 2620 | device->chip = &null_chipset; |
0ac9d210 BS |
2621 | } |
2622 | ||
6cf813fb BS |
2623 | if (!device->name) |
2624 | device->name = device->chip->name; | |
2625 | ||
0ac9d210 BS |
2626 | if (mmio) { |
2627 | device->pri = ioremap(mmio_base, mmio_size); | |
2628 | if (!device->pri) { | |
2629 | nvdev_error(device, "unable to map PRI\n"); | |
1299b637 AC |
2630 | ret = -ENOMEM; |
2631 | goto done; | |
0ac9d210 BS |
2632 | } |
2633 | } | |
2634 | ||
a1e88736 | 2635 | mutex_init(&device->mutex); |
6cf813fb | 2636 | |
68f3f702 | 2637 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
6cf813fb BS |
2638 | #define _(s,m) case s: \ |
2639 | if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ | |
2640 | ret = device->chip->m(device, (s), &device->m); \ | |
2641 | if (ret) { \ | |
2642 | subdev = nvkm_device_subdev(device, (s)); \ | |
2643 | nvkm_subdev_del(&subdev); \ | |
2644 | device->m = NULL; \ | |
2645 | if (ret != -ENODEV) { \ | |
2646 | nvdev_error(device, "%s ctor failed, %d\n", \ | |
2647 | nvkm_subdev_name[s], ret); \ | |
2648 | goto done; \ | |
2649 | } \ | |
2650 | } \ | |
2651 | } \ | |
2652 | break | |
2653 | switch (i) { | |
dc06e366 MP |
2654 | _(NVKM_SUBDEV_BAR , bar); |
2655 | _(NVKM_SUBDEV_VBIOS , bios); | |
2656 | _(NVKM_SUBDEV_BUS , bus); | |
2657 | _(NVKM_SUBDEV_CLK , clk); | |
2658 | _(NVKM_SUBDEV_DEVINIT , devinit); | |
2659 | _(NVKM_SUBDEV_FB , fb); | |
2660 | _(NVKM_SUBDEV_FUSE , fuse); | |
2661 | _(NVKM_SUBDEV_GPIO , gpio); | |
2662 | _(NVKM_SUBDEV_I2C , i2c); | |
2663 | _(NVKM_SUBDEV_IBUS , ibus); | |
2664 | _(NVKM_SUBDEV_ICCSENSE, iccsense); | |
2665 | _(NVKM_SUBDEV_INSTMEM , imem); | |
2666 | _(NVKM_SUBDEV_LTC , ltc); | |
2667 | _(NVKM_SUBDEV_MC , mc); | |
2668 | _(NVKM_SUBDEV_MMU , mmu); | |
2669 | _(NVKM_SUBDEV_MXM , mxm); | |
2670 | _(NVKM_SUBDEV_PCI , pci); | |
2671 | _(NVKM_SUBDEV_PMU , pmu); | |
2672 | _(NVKM_SUBDEV_SECBOOT , secboot); | |
2673 | _(NVKM_SUBDEV_THERM , therm); | |
2674 | _(NVKM_SUBDEV_TIMER , timer); | |
eaebfcc3 | 2675 | _(NVKM_SUBDEV_TOP , top); |
dc06e366 MP |
2676 | _(NVKM_SUBDEV_VOLT , volt); |
2677 | _(NVKM_ENGINE_BSP , bsp); | |
2678 | _(NVKM_ENGINE_CE0 , ce[0]); | |
2679 | _(NVKM_ENGINE_CE1 , ce[1]); | |
2680 | _(NVKM_ENGINE_CE2 , ce[2]); | |
34bf50cd BS |
2681 | _(NVKM_ENGINE_CE3 , ce[3]); |
2682 | _(NVKM_ENGINE_CE4 , ce[4]); | |
2683 | _(NVKM_ENGINE_CE5 , ce[5]); | |
dc06e366 MP |
2684 | _(NVKM_ENGINE_CIPHER , cipher); |
2685 | _(NVKM_ENGINE_DISP , disp); | |
2686 | _(NVKM_ENGINE_DMAOBJ , dma); | |
2687 | _(NVKM_ENGINE_FIFO , fifo); | |
2688 | _(NVKM_ENGINE_GR , gr); | |
2689 | _(NVKM_ENGINE_IFB , ifb); | |
2690 | _(NVKM_ENGINE_ME , me); | |
2691 | _(NVKM_ENGINE_MPEG , mpeg); | |
2692 | _(NVKM_ENGINE_MSENC , msenc); | |
2693 | _(NVKM_ENGINE_MSPDEC , mspdec); | |
2694 | _(NVKM_ENGINE_MSPPP , msppp); | |
2695 | _(NVKM_ENGINE_MSVLD , msvld); | |
294af04b BS |
2696 | _(NVKM_ENGINE_NVENC0 , nvenc[0]); |
2697 | _(NVKM_ENGINE_NVENC1 , nvenc[1]); | |
cb7b5ea9 | 2698 | _(NVKM_ENGINE_NVENC2 , nvenc[2]); |
3545b425 | 2699 | _(NVKM_ENGINE_NVDEC , nvdec); |
dc06e366 MP |
2700 | _(NVKM_ENGINE_PM , pm); |
2701 | _(NVKM_ENGINE_SEC , sec); | |
2702 | _(NVKM_ENGINE_SW , sw); | |
2703 | _(NVKM_ENGINE_VIC , vic); | |
2704 | _(NVKM_ENGINE_VP , vp); | |
6cf813fb BS |
2705 | default: |
2706 | WARN_ON(1); | |
2707 | continue; | |
2708 | } | |
2709 | #undef _ | |
2710 | } | |
2711 | ||
2712 | ret = 0; | |
9274f4a9 BS |
2713 | done: |
2714 | mutex_unlock(&nv_devices_mutex); | |
2715 | return ret; | |
2716 | } |