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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
9719047b BS |
24 | #include "priv.h" |
25 | #include "acpi.h" | |
9274f4a9 | 26 | |
9719047b | 27 | #include <core/notify.h> |
a1bfb29a | 28 | #include <core/option.h> |
d01c3092 | 29 | |
a1bfb29a | 30 | #include <subdev/bios.h> |
b138eca6 | 31 | #include <subdev/therm.h> |
9274f4a9 BS |
32 | |
33 | static DEFINE_MUTEX(nv_devices_mutex); | |
34 | static LIST_HEAD(nv_devices); | |
35 | ||
7974dd1b BS |
36 | static struct nvkm_device * |
37 | nvkm_device_find_locked(u64 handle) | |
9274f4a9 | 38 | { |
7974dd1b | 39 | struct nvkm_device *device; |
9274f4a9 | 40 | list_for_each_entry(device, &nv_devices, head) { |
7974dd1b BS |
41 | if (device->handle == handle) |
42 | return device; | |
9274f4a9 | 43 | } |
7974dd1b BS |
44 | return NULL; |
45 | } | |
46 | ||
47 | struct nvkm_device * | |
48 | nvkm_device_find(u64 handle) | |
49 | { | |
50 | struct nvkm_device *device; | |
51 | mutex_lock(&nv_devices_mutex); | |
52 | device = nvkm_device_find_locked(handle); | |
9274f4a9 | 53 | mutex_unlock(&nv_devices_mutex); |
7974dd1b | 54 | return device; |
9274f4a9 BS |
55 | } |
56 | ||
803c1787 | 57 | int |
9719047b | 58 | nvkm_device_list(u64 *name, int size) |
803c1787 | 59 | { |
9719047b | 60 | struct nvkm_device *device; |
803c1787 BS |
61 | int nr = 0; |
62 | mutex_lock(&nv_devices_mutex); | |
63 | list_for_each_entry(device, &nv_devices, head) { | |
64 | if (nr++ < size) | |
65 | name[nr - 1] = device->handle; | |
66 | } | |
67 | mutex_unlock(&nv_devices_mutex); | |
68 | return nr; | |
69 | } | |
70 | ||
6cf813fb BS |
71 | static const struct nvkm_device_chip |
72 | null_chipset = { | |
73 | .name = "NULL", | |
46484438 | 74 | .bios = nvkm_bios_new, |
6cf813fb BS |
75 | }; |
76 | ||
77 | static const struct nvkm_device_chip | |
78 | nv4_chipset = { | |
79 | .name = "NV04", | |
46484438 | 80 | .bios = nvkm_bios_new, |
bb23f9d7 | 81 | .bus = nv04_bus_new, |
6625f55c | 82 | .clk = nv04_clk_new, |
151abd44 | 83 | .devinit = nv04_devinit_new, |
03c8952f | 84 | .fb = nv04_fb_new, |
49bd8da5 | 85 | .i2c = nv04_i2c_new, |
b7a2bc18 | 86 | .imem = nv04_instmem_new, |
54dcadd5 | 87 | .mc = nv04_mc_new, |
c9582455 | 88 | .mmu = nv04_mmu_new, |
0a34fb31 | 89 | .pci = nv04_pci_new, |
31649ecf | 90 | .timer = nv04_timer_new, |
70aa8670 | 91 | .disp = nv04_disp_new, |
bd70563f | 92 | .dma = nv04_dma_new, |
13de7f46 | 93 | .fifo = nv04_fifo_new, |
c85ee6ca | 94 | .gr = nv04_gr_new, |
6f41c7c5 | 95 | .sw = nv04_sw_new, |
6cf813fb BS |
96 | }; |
97 | ||
98 | static const struct nvkm_device_chip | |
99 | nv5_chipset = { | |
100 | .name = "NV05", | |
46484438 | 101 | .bios = nvkm_bios_new, |
bb23f9d7 | 102 | .bus = nv04_bus_new, |
6625f55c | 103 | .clk = nv04_clk_new, |
151abd44 | 104 | .devinit = nv05_devinit_new, |
03c8952f | 105 | .fb = nv04_fb_new, |
49bd8da5 | 106 | .i2c = nv04_i2c_new, |
b7a2bc18 | 107 | .imem = nv04_instmem_new, |
54dcadd5 | 108 | .mc = nv04_mc_new, |
c9582455 | 109 | .mmu = nv04_mmu_new, |
0a34fb31 | 110 | .pci = nv04_pci_new, |
31649ecf | 111 | .timer = nv04_timer_new, |
70aa8670 | 112 | .disp = nv04_disp_new, |
bd70563f | 113 | .dma = nv04_dma_new, |
13de7f46 | 114 | .fifo = nv04_fifo_new, |
c85ee6ca | 115 | .gr = nv04_gr_new, |
6f41c7c5 | 116 | .sw = nv04_sw_new, |
6cf813fb BS |
117 | }; |
118 | ||
119 | static const struct nvkm_device_chip | |
120 | nv10_chipset = { | |
121 | .name = "NV10", | |
46484438 | 122 | .bios = nvkm_bios_new, |
bb23f9d7 | 123 | .bus = nv04_bus_new, |
6625f55c | 124 | .clk = nv04_clk_new, |
151abd44 | 125 | .devinit = nv10_devinit_new, |
03c8952f | 126 | .fb = nv10_fb_new, |
2ea7249f | 127 | .gpio = nv10_gpio_new, |
49bd8da5 | 128 | .i2c = nv04_i2c_new, |
b7a2bc18 | 129 | .imem = nv04_instmem_new, |
54dcadd5 | 130 | .mc = nv04_mc_new, |
c9582455 | 131 | .mmu = nv04_mmu_new, |
0a34fb31 | 132 | .pci = nv04_pci_new, |
31649ecf | 133 | .timer = nv04_timer_new, |
70aa8670 | 134 | .disp = nv04_disp_new, |
bd70563f | 135 | .dma = nv04_dma_new, |
c85ee6ca | 136 | .gr = nv10_gr_new, |
6cf813fb BS |
137 | }; |
138 | ||
139 | static const struct nvkm_device_chip | |
140 | nv11_chipset = { | |
141 | .name = "NV11", | |
46484438 | 142 | .bios = nvkm_bios_new, |
bb23f9d7 | 143 | .bus = nv04_bus_new, |
6625f55c | 144 | .clk = nv04_clk_new, |
151abd44 | 145 | .devinit = nv10_devinit_new, |
03c8952f | 146 | .fb = nv10_fb_new, |
2ea7249f | 147 | .gpio = nv10_gpio_new, |
49bd8da5 | 148 | .i2c = nv04_i2c_new, |
b7a2bc18 | 149 | .imem = nv04_instmem_new, |
667e99ab | 150 | .mc = nv11_mc_new, |
c9582455 | 151 | .mmu = nv04_mmu_new, |
0a34fb31 | 152 | .pci = nv04_pci_new, |
31649ecf | 153 | .timer = nv04_timer_new, |
70aa8670 | 154 | .disp = nv04_disp_new, |
bd70563f | 155 | .dma = nv04_dma_new, |
13de7f46 | 156 | .fifo = nv10_fifo_new, |
c85ee6ca | 157 | .gr = nv15_gr_new, |
6f41c7c5 | 158 | .sw = nv10_sw_new, |
6cf813fb BS |
159 | }; |
160 | ||
161 | static const struct nvkm_device_chip | |
162 | nv15_chipset = { | |
163 | .name = "NV15", | |
46484438 | 164 | .bios = nvkm_bios_new, |
bb23f9d7 | 165 | .bus = nv04_bus_new, |
6625f55c | 166 | .clk = nv04_clk_new, |
151abd44 | 167 | .devinit = nv10_devinit_new, |
03c8952f | 168 | .fb = nv10_fb_new, |
2ea7249f | 169 | .gpio = nv10_gpio_new, |
49bd8da5 | 170 | .i2c = nv04_i2c_new, |
b7a2bc18 | 171 | .imem = nv04_instmem_new, |
54dcadd5 | 172 | .mc = nv04_mc_new, |
c9582455 | 173 | .mmu = nv04_mmu_new, |
0a34fb31 | 174 | .pci = nv04_pci_new, |
31649ecf | 175 | .timer = nv04_timer_new, |
70aa8670 | 176 | .disp = nv04_disp_new, |
bd70563f | 177 | .dma = nv04_dma_new, |
13de7f46 | 178 | .fifo = nv10_fifo_new, |
c85ee6ca | 179 | .gr = nv15_gr_new, |
6f41c7c5 | 180 | .sw = nv10_sw_new, |
6cf813fb BS |
181 | }; |
182 | ||
183 | static const struct nvkm_device_chip | |
184 | nv17_chipset = { | |
185 | .name = "NV17", | |
46484438 | 186 | .bios = nvkm_bios_new, |
bb23f9d7 | 187 | .bus = nv04_bus_new, |
6625f55c | 188 | .clk = nv04_clk_new, |
151abd44 | 189 | .devinit = nv10_devinit_new, |
03c8952f | 190 | .fb = nv10_fb_new, |
2ea7249f | 191 | .gpio = nv10_gpio_new, |
49bd8da5 | 192 | .i2c = nv04_i2c_new, |
b7a2bc18 | 193 | .imem = nv04_instmem_new, |
79360b7d | 194 | .mc = nv17_mc_new, |
c9582455 | 195 | .mmu = nv04_mmu_new, |
0a34fb31 | 196 | .pci = nv04_pci_new, |
31649ecf | 197 | .timer = nv04_timer_new, |
70aa8670 | 198 | .disp = nv04_disp_new, |
bd70563f | 199 | .dma = nv04_dma_new, |
13de7f46 | 200 | .fifo = nv17_fifo_new, |
c85ee6ca | 201 | .gr = nv17_gr_new, |
6f41c7c5 | 202 | .sw = nv10_sw_new, |
6cf813fb BS |
203 | }; |
204 | ||
205 | static const struct nvkm_device_chip | |
206 | nv18_chipset = { | |
207 | .name = "NV18", | |
46484438 | 208 | .bios = nvkm_bios_new, |
bb23f9d7 | 209 | .bus = nv04_bus_new, |
6625f55c | 210 | .clk = nv04_clk_new, |
151abd44 | 211 | .devinit = nv10_devinit_new, |
03c8952f | 212 | .fb = nv10_fb_new, |
2ea7249f | 213 | .gpio = nv10_gpio_new, |
49bd8da5 | 214 | .i2c = nv04_i2c_new, |
b7a2bc18 | 215 | .imem = nv04_instmem_new, |
79360b7d | 216 | .mc = nv17_mc_new, |
c9582455 | 217 | .mmu = nv04_mmu_new, |
0a34fb31 | 218 | .pci = nv04_pci_new, |
31649ecf | 219 | .timer = nv04_timer_new, |
70aa8670 | 220 | .disp = nv04_disp_new, |
bd70563f | 221 | .dma = nv04_dma_new, |
13de7f46 | 222 | .fifo = nv17_fifo_new, |
c85ee6ca | 223 | .gr = nv17_gr_new, |
6f41c7c5 | 224 | .sw = nv10_sw_new, |
6cf813fb BS |
225 | }; |
226 | ||
227 | static const struct nvkm_device_chip | |
228 | nv1a_chipset = { | |
229 | .name = "nForce", | |
46484438 | 230 | .bios = nvkm_bios_new, |
bb23f9d7 | 231 | .bus = nv04_bus_new, |
6625f55c | 232 | .clk = nv04_clk_new, |
151abd44 | 233 | .devinit = nv1a_devinit_new, |
03c8952f | 234 | .fb = nv1a_fb_new, |
2ea7249f | 235 | .gpio = nv10_gpio_new, |
49bd8da5 | 236 | .i2c = nv04_i2c_new, |
b7a2bc18 | 237 | .imem = nv04_instmem_new, |
54dcadd5 | 238 | .mc = nv04_mc_new, |
c9582455 | 239 | .mmu = nv04_mmu_new, |
0a34fb31 | 240 | .pci = nv04_pci_new, |
31649ecf | 241 | .timer = nv04_timer_new, |
70aa8670 | 242 | .disp = nv04_disp_new, |
bd70563f | 243 | .dma = nv04_dma_new, |
13de7f46 | 244 | .fifo = nv10_fifo_new, |
c85ee6ca | 245 | .gr = nv15_gr_new, |
6f41c7c5 | 246 | .sw = nv10_sw_new, |
6cf813fb BS |
247 | }; |
248 | ||
249 | static const struct nvkm_device_chip | |
250 | nv1f_chipset = { | |
251 | .name = "nForce2", | |
46484438 | 252 | .bios = nvkm_bios_new, |
bb23f9d7 | 253 | .bus = nv04_bus_new, |
6625f55c | 254 | .clk = nv04_clk_new, |
151abd44 | 255 | .devinit = nv1a_devinit_new, |
03c8952f | 256 | .fb = nv1a_fb_new, |
2ea7249f | 257 | .gpio = nv10_gpio_new, |
49bd8da5 | 258 | .i2c = nv04_i2c_new, |
b7a2bc18 | 259 | .imem = nv04_instmem_new, |
79360b7d | 260 | .mc = nv17_mc_new, |
c9582455 | 261 | .mmu = nv04_mmu_new, |
0a34fb31 | 262 | .pci = nv04_pci_new, |
31649ecf | 263 | .timer = nv04_timer_new, |
70aa8670 | 264 | .disp = nv04_disp_new, |
bd70563f | 265 | .dma = nv04_dma_new, |
13de7f46 | 266 | .fifo = nv17_fifo_new, |
c85ee6ca | 267 | .gr = nv17_gr_new, |
6f41c7c5 | 268 | .sw = nv10_sw_new, |
6cf813fb BS |
269 | }; |
270 | ||
271 | static const struct nvkm_device_chip | |
272 | nv20_chipset = { | |
273 | .name = "NV20", | |
46484438 | 274 | .bios = nvkm_bios_new, |
bb23f9d7 | 275 | .bus = nv04_bus_new, |
6625f55c | 276 | .clk = nv04_clk_new, |
151abd44 | 277 | .devinit = nv20_devinit_new, |
03c8952f | 278 | .fb = nv20_fb_new, |
2ea7249f | 279 | .gpio = nv10_gpio_new, |
49bd8da5 | 280 | .i2c = nv04_i2c_new, |
b7a2bc18 | 281 | .imem = nv04_instmem_new, |
79360b7d | 282 | .mc = nv17_mc_new, |
c9582455 | 283 | .mmu = nv04_mmu_new, |
0a34fb31 | 284 | .pci = nv04_pci_new, |
31649ecf | 285 | .timer = nv04_timer_new, |
70aa8670 | 286 | .disp = nv04_disp_new, |
bd70563f | 287 | .dma = nv04_dma_new, |
13de7f46 | 288 | .fifo = nv17_fifo_new, |
c85ee6ca | 289 | .gr = nv20_gr_new, |
6f41c7c5 | 290 | .sw = nv10_sw_new, |
6cf813fb BS |
291 | }; |
292 | ||
293 | static const struct nvkm_device_chip | |
294 | nv25_chipset = { | |
295 | .name = "NV25", | |
46484438 | 296 | .bios = nvkm_bios_new, |
bb23f9d7 | 297 | .bus = nv04_bus_new, |
6625f55c | 298 | .clk = nv04_clk_new, |
151abd44 | 299 | .devinit = nv20_devinit_new, |
03c8952f | 300 | .fb = nv25_fb_new, |
2ea7249f | 301 | .gpio = nv10_gpio_new, |
49bd8da5 | 302 | .i2c = nv04_i2c_new, |
b7a2bc18 | 303 | .imem = nv04_instmem_new, |
79360b7d | 304 | .mc = nv17_mc_new, |
c9582455 | 305 | .mmu = nv04_mmu_new, |
0a34fb31 | 306 | .pci = nv04_pci_new, |
31649ecf | 307 | .timer = nv04_timer_new, |
70aa8670 | 308 | .disp = nv04_disp_new, |
bd70563f | 309 | .dma = nv04_dma_new, |
13de7f46 | 310 | .fifo = nv17_fifo_new, |
c85ee6ca | 311 | .gr = nv25_gr_new, |
6f41c7c5 | 312 | .sw = nv10_sw_new, |
6cf813fb BS |
313 | }; |
314 | ||
315 | static const struct nvkm_device_chip | |
316 | nv28_chipset = { | |
317 | .name = "NV28", | |
46484438 | 318 | .bios = nvkm_bios_new, |
bb23f9d7 | 319 | .bus = nv04_bus_new, |
6625f55c | 320 | .clk = nv04_clk_new, |
151abd44 | 321 | .devinit = nv20_devinit_new, |
03c8952f | 322 | .fb = nv25_fb_new, |
2ea7249f | 323 | .gpio = nv10_gpio_new, |
49bd8da5 | 324 | .i2c = nv04_i2c_new, |
b7a2bc18 | 325 | .imem = nv04_instmem_new, |
79360b7d | 326 | .mc = nv17_mc_new, |
c9582455 | 327 | .mmu = nv04_mmu_new, |
0a34fb31 | 328 | .pci = nv04_pci_new, |
31649ecf | 329 | .timer = nv04_timer_new, |
70aa8670 | 330 | .disp = nv04_disp_new, |
bd70563f | 331 | .dma = nv04_dma_new, |
13de7f46 | 332 | .fifo = nv17_fifo_new, |
c85ee6ca | 333 | .gr = nv25_gr_new, |
6f41c7c5 | 334 | .sw = nv10_sw_new, |
6cf813fb BS |
335 | }; |
336 | ||
337 | static const struct nvkm_device_chip | |
338 | nv2a_chipset = { | |
339 | .name = "NV2A", | |
46484438 | 340 | .bios = nvkm_bios_new, |
bb23f9d7 | 341 | .bus = nv04_bus_new, |
6625f55c | 342 | .clk = nv04_clk_new, |
151abd44 | 343 | .devinit = nv20_devinit_new, |
03c8952f | 344 | .fb = nv25_fb_new, |
2ea7249f | 345 | .gpio = nv10_gpio_new, |
49bd8da5 | 346 | .i2c = nv04_i2c_new, |
b7a2bc18 | 347 | .imem = nv04_instmem_new, |
79360b7d | 348 | .mc = nv17_mc_new, |
c9582455 | 349 | .mmu = nv04_mmu_new, |
0a34fb31 | 350 | .pci = nv04_pci_new, |
31649ecf | 351 | .timer = nv04_timer_new, |
70aa8670 | 352 | .disp = nv04_disp_new, |
bd70563f | 353 | .dma = nv04_dma_new, |
13de7f46 | 354 | .fifo = nv17_fifo_new, |
c85ee6ca | 355 | .gr = nv2a_gr_new, |
6f41c7c5 | 356 | .sw = nv10_sw_new, |
6cf813fb BS |
357 | }; |
358 | ||
359 | static const struct nvkm_device_chip | |
360 | nv30_chipset = { | |
361 | .name = "NV30", | |
46484438 | 362 | .bios = nvkm_bios_new, |
bb23f9d7 | 363 | .bus = nv04_bus_new, |
6625f55c | 364 | .clk = nv04_clk_new, |
151abd44 | 365 | .devinit = nv20_devinit_new, |
03c8952f | 366 | .fb = nv30_fb_new, |
2ea7249f | 367 | .gpio = nv10_gpio_new, |
49bd8da5 | 368 | .i2c = nv04_i2c_new, |
b7a2bc18 | 369 | .imem = nv04_instmem_new, |
79360b7d | 370 | .mc = nv17_mc_new, |
c9582455 | 371 | .mmu = nv04_mmu_new, |
0a34fb31 | 372 | .pci = nv04_pci_new, |
31649ecf | 373 | .timer = nv04_timer_new, |
70aa8670 | 374 | .disp = nv04_disp_new, |
bd70563f | 375 | .dma = nv04_dma_new, |
13de7f46 | 376 | .fifo = nv17_fifo_new, |
c85ee6ca | 377 | .gr = nv30_gr_new, |
6f41c7c5 | 378 | .sw = nv10_sw_new, |
6cf813fb BS |
379 | }; |
380 | ||
381 | static const struct nvkm_device_chip | |
382 | nv31_chipset = { | |
383 | .name = "NV31", | |
46484438 | 384 | .bios = nvkm_bios_new, |
bb23f9d7 | 385 | .bus = nv31_bus_new, |
6625f55c | 386 | .clk = nv04_clk_new, |
151abd44 | 387 | .devinit = nv20_devinit_new, |
03c8952f | 388 | .fb = nv30_fb_new, |
2ea7249f | 389 | .gpio = nv10_gpio_new, |
49bd8da5 | 390 | .i2c = nv04_i2c_new, |
b7a2bc18 | 391 | .imem = nv04_instmem_new, |
79360b7d | 392 | .mc = nv17_mc_new, |
c9582455 | 393 | .mmu = nv04_mmu_new, |
0a34fb31 | 394 | .pci = nv04_pci_new, |
31649ecf | 395 | .timer = nv04_timer_new, |
70aa8670 | 396 | .disp = nv04_disp_new, |
bd70563f | 397 | .dma = nv04_dma_new, |
13de7f46 | 398 | .fifo = nv17_fifo_new, |
c85ee6ca | 399 | .gr = nv30_gr_new, |
7624fc01 | 400 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 401 | .sw = nv10_sw_new, |
6cf813fb BS |
402 | }; |
403 | ||
404 | static const struct nvkm_device_chip | |
405 | nv34_chipset = { | |
406 | .name = "NV34", | |
46484438 | 407 | .bios = nvkm_bios_new, |
bb23f9d7 | 408 | .bus = nv31_bus_new, |
6625f55c | 409 | .clk = nv04_clk_new, |
151abd44 | 410 | .devinit = nv10_devinit_new, |
03c8952f | 411 | .fb = nv10_fb_new, |
2ea7249f | 412 | .gpio = nv10_gpio_new, |
49bd8da5 | 413 | .i2c = nv04_i2c_new, |
b7a2bc18 | 414 | .imem = nv04_instmem_new, |
79360b7d | 415 | .mc = nv17_mc_new, |
c9582455 | 416 | .mmu = nv04_mmu_new, |
0a34fb31 | 417 | .pci = nv04_pci_new, |
31649ecf | 418 | .timer = nv04_timer_new, |
70aa8670 | 419 | .disp = nv04_disp_new, |
bd70563f | 420 | .dma = nv04_dma_new, |
13de7f46 | 421 | .fifo = nv17_fifo_new, |
c85ee6ca | 422 | .gr = nv34_gr_new, |
7624fc01 | 423 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 424 | .sw = nv10_sw_new, |
6cf813fb BS |
425 | }; |
426 | ||
427 | static const struct nvkm_device_chip | |
428 | nv35_chipset = { | |
429 | .name = "NV35", | |
46484438 | 430 | .bios = nvkm_bios_new, |
bb23f9d7 | 431 | .bus = nv04_bus_new, |
6625f55c | 432 | .clk = nv04_clk_new, |
151abd44 | 433 | .devinit = nv20_devinit_new, |
03c8952f | 434 | .fb = nv35_fb_new, |
2ea7249f | 435 | .gpio = nv10_gpio_new, |
49bd8da5 | 436 | .i2c = nv04_i2c_new, |
b7a2bc18 | 437 | .imem = nv04_instmem_new, |
79360b7d | 438 | .mc = nv17_mc_new, |
c9582455 | 439 | .mmu = nv04_mmu_new, |
0a34fb31 | 440 | .pci = nv04_pci_new, |
31649ecf | 441 | .timer = nv04_timer_new, |
70aa8670 | 442 | .disp = nv04_disp_new, |
bd70563f | 443 | .dma = nv04_dma_new, |
13de7f46 | 444 | .fifo = nv17_fifo_new, |
c85ee6ca | 445 | .gr = nv35_gr_new, |
6f41c7c5 | 446 | .sw = nv10_sw_new, |
6cf813fb BS |
447 | }; |
448 | ||
449 | static const struct nvkm_device_chip | |
450 | nv36_chipset = { | |
451 | .name = "NV36", | |
46484438 | 452 | .bios = nvkm_bios_new, |
bb23f9d7 | 453 | .bus = nv31_bus_new, |
6625f55c | 454 | .clk = nv04_clk_new, |
151abd44 | 455 | .devinit = nv20_devinit_new, |
03c8952f | 456 | .fb = nv36_fb_new, |
2ea7249f | 457 | .gpio = nv10_gpio_new, |
49bd8da5 | 458 | .i2c = nv04_i2c_new, |
b7a2bc18 | 459 | .imem = nv04_instmem_new, |
79360b7d | 460 | .mc = nv17_mc_new, |
c9582455 | 461 | .mmu = nv04_mmu_new, |
0a34fb31 | 462 | .pci = nv04_pci_new, |
31649ecf | 463 | .timer = nv04_timer_new, |
70aa8670 | 464 | .disp = nv04_disp_new, |
bd70563f | 465 | .dma = nv04_dma_new, |
13de7f46 | 466 | .fifo = nv17_fifo_new, |
c85ee6ca | 467 | .gr = nv35_gr_new, |
7624fc01 | 468 | .mpeg = nv31_mpeg_new, |
6f41c7c5 | 469 | .sw = nv10_sw_new, |
6cf813fb BS |
470 | }; |
471 | ||
472 | static const struct nvkm_device_chip | |
473 | nv40_chipset = { | |
474 | .name = "NV40", | |
46484438 | 475 | .bios = nvkm_bios_new, |
bb23f9d7 | 476 | .bus = nv31_bus_new, |
6625f55c | 477 | .clk = nv40_clk_new, |
151abd44 | 478 | .devinit = nv1a_devinit_new, |
03c8952f | 479 | .fb = nv40_fb_new, |
2ea7249f | 480 | .gpio = nv10_gpio_new, |
49bd8da5 | 481 | .i2c = nv04_i2c_new, |
b7a2bc18 | 482 | .imem = nv40_instmem_new, |
79360b7d | 483 | .mc = nv17_mc_new, |
c9582455 | 484 | .mmu = nv04_mmu_new, |
0a34fb31 | 485 | .pci = nv40_pci_new, |
57113c01 | 486 | .therm = nv40_therm_new, |
31649ecf | 487 | .timer = nv40_timer_new, |
437b2296 | 488 | .volt = nv40_volt_new, |
70aa8670 | 489 | .disp = nv04_disp_new, |
bd70563f | 490 | .dma = nv04_dma_new, |
13de7f46 | 491 | .fifo = nv40_fifo_new, |
c85ee6ca | 492 | .gr = nv40_gr_new, |
7624fc01 | 493 | .mpeg = nv40_mpeg_new, |
97070f23 | 494 | .pm = nv40_pm_new, |
6f41c7c5 | 495 | .sw = nv10_sw_new, |
6cf813fb BS |
496 | }; |
497 | ||
498 | static const struct nvkm_device_chip | |
499 | nv41_chipset = { | |
500 | .name = "NV41", | |
46484438 | 501 | .bios = nvkm_bios_new, |
bb23f9d7 | 502 | .bus = nv31_bus_new, |
6625f55c | 503 | .clk = nv40_clk_new, |
151abd44 | 504 | .devinit = nv1a_devinit_new, |
03c8952f | 505 | .fb = nv41_fb_new, |
2ea7249f | 506 | .gpio = nv10_gpio_new, |
49bd8da5 | 507 | .i2c = nv04_i2c_new, |
b7a2bc18 | 508 | .imem = nv40_instmem_new, |
79360b7d | 509 | .mc = nv17_mc_new, |
c9582455 | 510 | .mmu = nv41_mmu_new, |
0a34fb31 | 511 | .pci = nv40_pci_new, |
57113c01 | 512 | .therm = nv40_therm_new, |
31649ecf | 513 | .timer = nv41_timer_new, |
437b2296 | 514 | .volt = nv40_volt_new, |
70aa8670 | 515 | .disp = nv04_disp_new, |
bd70563f | 516 | .dma = nv04_dma_new, |
13de7f46 | 517 | .fifo = nv40_fifo_new, |
c85ee6ca | 518 | .gr = nv40_gr_new, |
7624fc01 | 519 | .mpeg = nv40_mpeg_new, |
97070f23 | 520 | .pm = nv40_pm_new, |
6f41c7c5 | 521 | .sw = nv10_sw_new, |
6cf813fb BS |
522 | }; |
523 | ||
524 | static const struct nvkm_device_chip | |
525 | nv42_chipset = { | |
526 | .name = "NV42", | |
46484438 | 527 | .bios = nvkm_bios_new, |
bb23f9d7 | 528 | .bus = nv31_bus_new, |
6625f55c | 529 | .clk = nv40_clk_new, |
151abd44 | 530 | .devinit = nv1a_devinit_new, |
03c8952f | 531 | .fb = nv41_fb_new, |
2ea7249f | 532 | .gpio = nv10_gpio_new, |
49bd8da5 | 533 | .i2c = nv04_i2c_new, |
b7a2bc18 | 534 | .imem = nv40_instmem_new, |
79360b7d | 535 | .mc = nv17_mc_new, |
c9582455 | 536 | .mmu = nv41_mmu_new, |
0a34fb31 | 537 | .pci = nv40_pci_new, |
57113c01 | 538 | .therm = nv40_therm_new, |
31649ecf | 539 | .timer = nv41_timer_new, |
437b2296 | 540 | .volt = nv40_volt_new, |
70aa8670 | 541 | .disp = nv04_disp_new, |
bd70563f | 542 | .dma = nv04_dma_new, |
13de7f46 | 543 | .fifo = nv40_fifo_new, |
c85ee6ca | 544 | .gr = nv40_gr_new, |
7624fc01 | 545 | .mpeg = nv40_mpeg_new, |
97070f23 | 546 | .pm = nv40_pm_new, |
6f41c7c5 | 547 | .sw = nv10_sw_new, |
6cf813fb BS |
548 | }; |
549 | ||
550 | static const struct nvkm_device_chip | |
551 | nv43_chipset = { | |
552 | .name = "NV43", | |
46484438 | 553 | .bios = nvkm_bios_new, |
bb23f9d7 | 554 | .bus = nv31_bus_new, |
6625f55c | 555 | .clk = nv40_clk_new, |
151abd44 | 556 | .devinit = nv1a_devinit_new, |
03c8952f | 557 | .fb = nv41_fb_new, |
2ea7249f | 558 | .gpio = nv10_gpio_new, |
49bd8da5 | 559 | .i2c = nv04_i2c_new, |
b7a2bc18 | 560 | .imem = nv40_instmem_new, |
79360b7d | 561 | .mc = nv17_mc_new, |
c9582455 | 562 | .mmu = nv41_mmu_new, |
0a34fb31 | 563 | .pci = nv40_pci_new, |
57113c01 | 564 | .therm = nv40_therm_new, |
31649ecf | 565 | .timer = nv41_timer_new, |
437b2296 | 566 | .volt = nv40_volt_new, |
70aa8670 | 567 | .disp = nv04_disp_new, |
bd70563f | 568 | .dma = nv04_dma_new, |
13de7f46 | 569 | .fifo = nv40_fifo_new, |
c85ee6ca | 570 | .gr = nv40_gr_new, |
7624fc01 | 571 | .mpeg = nv40_mpeg_new, |
97070f23 | 572 | .pm = nv40_pm_new, |
6f41c7c5 | 573 | .sw = nv10_sw_new, |
6cf813fb BS |
574 | }; |
575 | ||
576 | static const struct nvkm_device_chip | |
577 | nv44_chipset = { | |
578 | .name = "NV44", | |
46484438 | 579 | .bios = nvkm_bios_new, |
bb23f9d7 | 580 | .bus = nv31_bus_new, |
6625f55c | 581 | .clk = nv40_clk_new, |
151abd44 | 582 | .devinit = nv1a_devinit_new, |
03c8952f | 583 | .fb = nv44_fb_new, |
2ea7249f | 584 | .gpio = nv10_gpio_new, |
49bd8da5 | 585 | .i2c = nv04_i2c_new, |
b7a2bc18 | 586 | .imem = nv40_instmem_new, |
54dcadd5 | 587 | .mc = nv44_mc_new, |
c9582455 | 588 | .mmu = nv44_mmu_new, |
0a34fb31 | 589 | .pci = nv40_pci_new, |
57113c01 | 590 | .therm = nv40_therm_new, |
31649ecf | 591 | .timer = nv41_timer_new, |
437b2296 | 592 | .volt = nv40_volt_new, |
70aa8670 | 593 | .disp = nv04_disp_new, |
bd70563f | 594 | .dma = nv04_dma_new, |
13de7f46 | 595 | .fifo = nv40_fifo_new, |
c85ee6ca | 596 | .gr = nv44_gr_new, |
7624fc01 | 597 | .mpeg = nv44_mpeg_new, |
97070f23 | 598 | .pm = nv40_pm_new, |
6f41c7c5 | 599 | .sw = nv10_sw_new, |
6cf813fb BS |
600 | }; |
601 | ||
602 | static const struct nvkm_device_chip | |
603 | nv45_chipset = { | |
604 | .name = "NV45", | |
46484438 | 605 | .bios = nvkm_bios_new, |
bb23f9d7 | 606 | .bus = nv31_bus_new, |
6625f55c | 607 | .clk = nv40_clk_new, |
151abd44 | 608 | .devinit = nv1a_devinit_new, |
03c8952f | 609 | .fb = nv40_fb_new, |
2ea7249f | 610 | .gpio = nv10_gpio_new, |
49bd8da5 | 611 | .i2c = nv04_i2c_new, |
b7a2bc18 | 612 | .imem = nv40_instmem_new, |
79360b7d | 613 | .mc = nv17_mc_new, |
c9582455 | 614 | .mmu = nv04_mmu_new, |
0a34fb31 | 615 | .pci = nv40_pci_new, |
57113c01 | 616 | .therm = nv40_therm_new, |
31649ecf | 617 | .timer = nv41_timer_new, |
437b2296 | 618 | .volt = nv40_volt_new, |
70aa8670 | 619 | .disp = nv04_disp_new, |
bd70563f | 620 | .dma = nv04_dma_new, |
13de7f46 | 621 | .fifo = nv40_fifo_new, |
c85ee6ca | 622 | .gr = nv40_gr_new, |
7624fc01 | 623 | .mpeg = nv44_mpeg_new, |
97070f23 | 624 | .pm = nv40_pm_new, |
6f41c7c5 | 625 | .sw = nv10_sw_new, |
6cf813fb BS |
626 | }; |
627 | ||
628 | static const struct nvkm_device_chip | |
629 | nv46_chipset = { | |
630 | .name = "G72", | |
46484438 | 631 | .bios = nvkm_bios_new, |
bb23f9d7 | 632 | .bus = nv31_bus_new, |
6625f55c | 633 | .clk = nv40_clk_new, |
151abd44 | 634 | .devinit = nv1a_devinit_new, |
03c8952f | 635 | .fb = nv46_fb_new, |
2ea7249f | 636 | .gpio = nv10_gpio_new, |
49bd8da5 | 637 | .i2c = nv04_i2c_new, |
b7a2bc18 | 638 | .imem = nv40_instmem_new, |
54dcadd5 | 639 | .mc = nv44_mc_new, |
c9582455 | 640 | .mmu = nv44_mmu_new, |
c4266a9c | 641 | .pci = nv46_pci_new, |
57113c01 | 642 | .therm = nv40_therm_new, |
31649ecf | 643 | .timer = nv41_timer_new, |
437b2296 | 644 | .volt = nv40_volt_new, |
70aa8670 | 645 | .disp = nv04_disp_new, |
bd70563f | 646 | .dma = nv04_dma_new, |
13de7f46 | 647 | .fifo = nv40_fifo_new, |
c85ee6ca | 648 | .gr = nv44_gr_new, |
7624fc01 | 649 | .mpeg = nv44_mpeg_new, |
97070f23 | 650 | .pm = nv40_pm_new, |
6f41c7c5 | 651 | .sw = nv10_sw_new, |
6cf813fb BS |
652 | }; |
653 | ||
654 | static const struct nvkm_device_chip | |
655 | nv47_chipset = { | |
656 | .name = "G70", | |
46484438 | 657 | .bios = nvkm_bios_new, |
bb23f9d7 | 658 | .bus = nv31_bus_new, |
6625f55c | 659 | .clk = nv40_clk_new, |
151abd44 | 660 | .devinit = nv1a_devinit_new, |
03c8952f | 661 | .fb = nv47_fb_new, |
2ea7249f | 662 | .gpio = nv10_gpio_new, |
49bd8da5 | 663 | .i2c = nv04_i2c_new, |
b7a2bc18 | 664 | .imem = nv40_instmem_new, |
79360b7d | 665 | .mc = nv17_mc_new, |
c9582455 | 666 | .mmu = nv41_mmu_new, |
0a34fb31 | 667 | .pci = nv40_pci_new, |
57113c01 | 668 | .therm = nv40_therm_new, |
31649ecf | 669 | .timer = nv41_timer_new, |
437b2296 | 670 | .volt = nv40_volt_new, |
70aa8670 | 671 | .disp = nv04_disp_new, |
bd70563f | 672 | .dma = nv04_dma_new, |
13de7f46 | 673 | .fifo = nv40_fifo_new, |
c85ee6ca | 674 | .gr = nv40_gr_new, |
7624fc01 | 675 | .mpeg = nv44_mpeg_new, |
97070f23 | 676 | .pm = nv40_pm_new, |
6f41c7c5 | 677 | .sw = nv10_sw_new, |
6cf813fb BS |
678 | }; |
679 | ||
680 | static const struct nvkm_device_chip | |
681 | nv49_chipset = { | |
682 | .name = "G71", | |
46484438 | 683 | .bios = nvkm_bios_new, |
bb23f9d7 | 684 | .bus = nv31_bus_new, |
6625f55c | 685 | .clk = nv40_clk_new, |
151abd44 | 686 | .devinit = nv1a_devinit_new, |
03c8952f | 687 | .fb = nv49_fb_new, |
2ea7249f | 688 | .gpio = nv10_gpio_new, |
49bd8da5 | 689 | .i2c = nv04_i2c_new, |
b7a2bc18 | 690 | .imem = nv40_instmem_new, |
79360b7d | 691 | .mc = nv17_mc_new, |
c9582455 | 692 | .mmu = nv41_mmu_new, |
0a34fb31 | 693 | .pci = nv40_pci_new, |
57113c01 | 694 | .therm = nv40_therm_new, |
31649ecf | 695 | .timer = nv41_timer_new, |
437b2296 | 696 | .volt = nv40_volt_new, |
70aa8670 | 697 | .disp = nv04_disp_new, |
bd70563f | 698 | .dma = nv04_dma_new, |
13de7f46 | 699 | .fifo = nv40_fifo_new, |
c85ee6ca | 700 | .gr = nv40_gr_new, |
7624fc01 | 701 | .mpeg = nv44_mpeg_new, |
97070f23 | 702 | .pm = nv40_pm_new, |
6f41c7c5 | 703 | .sw = nv10_sw_new, |
6cf813fb BS |
704 | }; |
705 | ||
706 | static const struct nvkm_device_chip | |
707 | nv4a_chipset = { | |
708 | .name = "NV44A", | |
46484438 | 709 | .bios = nvkm_bios_new, |
bb23f9d7 | 710 | .bus = nv31_bus_new, |
6625f55c | 711 | .clk = nv40_clk_new, |
151abd44 | 712 | .devinit = nv1a_devinit_new, |
03c8952f | 713 | .fb = nv44_fb_new, |
2ea7249f | 714 | .gpio = nv10_gpio_new, |
49bd8da5 | 715 | .i2c = nv04_i2c_new, |
b7a2bc18 | 716 | .imem = nv40_instmem_new, |
54dcadd5 | 717 | .mc = nv44_mc_new, |
ac799aca | 718 | .mmu = nv04_mmu_new, |
0a34fb31 | 719 | .pci = nv40_pci_new, |
57113c01 | 720 | .therm = nv40_therm_new, |
31649ecf | 721 | .timer = nv41_timer_new, |
437b2296 | 722 | .volt = nv40_volt_new, |
70aa8670 | 723 | .disp = nv04_disp_new, |
bd70563f | 724 | .dma = nv04_dma_new, |
13de7f46 | 725 | .fifo = nv40_fifo_new, |
c85ee6ca | 726 | .gr = nv44_gr_new, |
7624fc01 | 727 | .mpeg = nv44_mpeg_new, |
97070f23 | 728 | .pm = nv40_pm_new, |
6f41c7c5 | 729 | .sw = nv10_sw_new, |
6cf813fb BS |
730 | }; |
731 | ||
732 | static const struct nvkm_device_chip | |
733 | nv4b_chipset = { | |
734 | .name = "G73", | |
46484438 | 735 | .bios = nvkm_bios_new, |
bb23f9d7 | 736 | .bus = nv31_bus_new, |
6625f55c | 737 | .clk = nv40_clk_new, |
151abd44 | 738 | .devinit = nv1a_devinit_new, |
03c8952f | 739 | .fb = nv49_fb_new, |
2ea7249f | 740 | .gpio = nv10_gpio_new, |
49bd8da5 | 741 | .i2c = nv04_i2c_new, |
b7a2bc18 | 742 | .imem = nv40_instmem_new, |
79360b7d | 743 | .mc = nv17_mc_new, |
c9582455 | 744 | .mmu = nv41_mmu_new, |
0a34fb31 | 745 | .pci = nv40_pci_new, |
57113c01 | 746 | .therm = nv40_therm_new, |
31649ecf | 747 | .timer = nv41_timer_new, |
437b2296 | 748 | .volt = nv40_volt_new, |
70aa8670 | 749 | .disp = nv04_disp_new, |
bd70563f | 750 | .dma = nv04_dma_new, |
13de7f46 | 751 | .fifo = nv40_fifo_new, |
c85ee6ca | 752 | .gr = nv40_gr_new, |
7624fc01 | 753 | .mpeg = nv44_mpeg_new, |
97070f23 | 754 | .pm = nv40_pm_new, |
6f41c7c5 | 755 | .sw = nv10_sw_new, |
6cf813fb BS |
756 | }; |
757 | ||
758 | static const struct nvkm_device_chip | |
759 | nv4c_chipset = { | |
760 | .name = "C61", | |
46484438 | 761 | .bios = nvkm_bios_new, |
bb23f9d7 | 762 | .bus = nv31_bus_new, |
6625f55c | 763 | .clk = nv40_clk_new, |
151abd44 | 764 | .devinit = nv1a_devinit_new, |
03c8952f | 765 | .fb = nv46_fb_new, |
2ea7249f | 766 | .gpio = nv10_gpio_new, |
49bd8da5 | 767 | .i2c = nv04_i2c_new, |
b7a2bc18 | 768 | .imem = nv40_instmem_new, |
2b700825 | 769 | .mc = nv44_mc_new, |
c9582455 | 770 | .mmu = nv44_mmu_new, |
0a34fb31 | 771 | .pci = nv4c_pci_new, |
57113c01 | 772 | .therm = nv40_therm_new, |
31649ecf | 773 | .timer = nv41_timer_new, |
437b2296 | 774 | .volt = nv40_volt_new, |
70aa8670 | 775 | .disp = nv04_disp_new, |
bd70563f | 776 | .dma = nv04_dma_new, |
13de7f46 | 777 | .fifo = nv40_fifo_new, |
c85ee6ca | 778 | .gr = nv44_gr_new, |
7624fc01 | 779 | .mpeg = nv44_mpeg_new, |
97070f23 | 780 | .pm = nv40_pm_new, |
6f41c7c5 | 781 | .sw = nv10_sw_new, |
6cf813fb BS |
782 | }; |
783 | ||
784 | static const struct nvkm_device_chip | |
785 | nv4e_chipset = { | |
786 | .name = "C51", | |
46484438 | 787 | .bios = nvkm_bios_new, |
bb23f9d7 | 788 | .bus = nv31_bus_new, |
6625f55c | 789 | .clk = nv40_clk_new, |
151abd44 | 790 | .devinit = nv1a_devinit_new, |
03c8952f | 791 | .fb = nv4e_fb_new, |
2ea7249f | 792 | .gpio = nv10_gpio_new, |
49bd8da5 | 793 | .i2c = nv4e_i2c_new, |
b7a2bc18 | 794 | .imem = nv40_instmem_new, |
2b700825 | 795 | .mc = nv44_mc_new, |
c9582455 | 796 | .mmu = nv44_mmu_new, |
0a34fb31 | 797 | .pci = nv4c_pci_new, |
57113c01 | 798 | .therm = nv40_therm_new, |
31649ecf | 799 | .timer = nv41_timer_new, |
437b2296 | 800 | .volt = nv40_volt_new, |
70aa8670 | 801 | .disp = nv04_disp_new, |
bd70563f | 802 | .dma = nv04_dma_new, |
13de7f46 | 803 | .fifo = nv40_fifo_new, |
c85ee6ca | 804 | .gr = nv44_gr_new, |
7624fc01 | 805 | .mpeg = nv44_mpeg_new, |
97070f23 | 806 | .pm = nv40_pm_new, |
6f41c7c5 | 807 | .sw = nv10_sw_new, |
6cf813fb BS |
808 | }; |
809 | ||
810 | static const struct nvkm_device_chip | |
811 | nv50_chipset = { | |
812 | .name = "G80", | |
32932281 | 813 | .bar = nv50_bar_new, |
46484438 | 814 | .bios = nvkm_bios_new, |
bb23f9d7 | 815 | .bus = nv50_bus_new, |
6625f55c | 816 | .clk = nv50_clk_new, |
151abd44 | 817 | .devinit = nv50_devinit_new, |
03c8952f | 818 | .fb = nv50_fb_new, |
c5fcafa5 | 819 | .fuse = nv50_fuse_new, |
2ea7249f | 820 | .gpio = nv50_gpio_new, |
49bd8da5 | 821 | .i2c = nv50_i2c_new, |
b7a2bc18 | 822 | .imem = nv50_instmem_new, |
54dcadd5 | 823 | .mc = nv50_mc_new, |
c9582455 | 824 | .mmu = nv50_mmu_new, |
a4f7bd36 | 825 | .mxm = nv50_mxm_new, |
c4266a9c | 826 | .pci = nv46_pci_new, |
57113c01 | 827 | .therm = nv50_therm_new, |
31649ecf | 828 | .timer = nv41_timer_new, |
437b2296 | 829 | .volt = nv40_volt_new, |
70aa8670 | 830 | .disp = nv50_disp_new, |
bd70563f | 831 | .dma = nv50_dma_new, |
13de7f46 | 832 | .fifo = nv50_fifo_new, |
c85ee6ca | 833 | .gr = nv50_gr_new, |
7624fc01 | 834 | .mpeg = nv50_mpeg_new, |
97070f23 | 835 | .pm = nv50_pm_new, |
6f41c7c5 | 836 | .sw = nv50_sw_new, |
6cf813fb BS |
837 | }; |
838 | ||
839 | static const struct nvkm_device_chip | |
840 | nv63_chipset = { | |
841 | .name = "C73", | |
46484438 | 842 | .bios = nvkm_bios_new, |
bb23f9d7 | 843 | .bus = nv31_bus_new, |
6625f55c | 844 | .clk = nv40_clk_new, |
151abd44 | 845 | .devinit = nv1a_devinit_new, |
03c8952f | 846 | .fb = nv46_fb_new, |
2ea7249f | 847 | .gpio = nv10_gpio_new, |
49bd8da5 | 848 | .i2c = nv04_i2c_new, |
b7a2bc18 | 849 | .imem = nv40_instmem_new, |
2b700825 | 850 | .mc = nv44_mc_new, |
c9582455 | 851 | .mmu = nv44_mmu_new, |
0a34fb31 | 852 | .pci = nv4c_pci_new, |
57113c01 | 853 | .therm = nv40_therm_new, |
31649ecf | 854 | .timer = nv41_timer_new, |
437b2296 | 855 | .volt = nv40_volt_new, |
70aa8670 | 856 | .disp = nv04_disp_new, |
bd70563f | 857 | .dma = nv04_dma_new, |
13de7f46 | 858 | .fifo = nv40_fifo_new, |
c85ee6ca | 859 | .gr = nv44_gr_new, |
7624fc01 | 860 | .mpeg = nv44_mpeg_new, |
97070f23 | 861 | .pm = nv40_pm_new, |
6f41c7c5 | 862 | .sw = nv10_sw_new, |
6cf813fb BS |
863 | }; |
864 | ||
865 | static const struct nvkm_device_chip | |
866 | nv67_chipset = { | |
867 | .name = "C67", | |
46484438 | 868 | .bios = nvkm_bios_new, |
bb23f9d7 | 869 | .bus = nv31_bus_new, |
6625f55c | 870 | .clk = nv40_clk_new, |
151abd44 | 871 | .devinit = nv1a_devinit_new, |
03c8952f | 872 | .fb = nv46_fb_new, |
2ea7249f | 873 | .gpio = nv10_gpio_new, |
49bd8da5 | 874 | .i2c = nv04_i2c_new, |
b7a2bc18 | 875 | .imem = nv40_instmem_new, |
2b700825 | 876 | .mc = nv44_mc_new, |
c9582455 | 877 | .mmu = nv44_mmu_new, |
0a34fb31 | 878 | .pci = nv4c_pci_new, |
57113c01 | 879 | .therm = nv40_therm_new, |
31649ecf | 880 | .timer = nv41_timer_new, |
437b2296 | 881 | .volt = nv40_volt_new, |
70aa8670 | 882 | .disp = nv04_disp_new, |
bd70563f | 883 | .dma = nv04_dma_new, |
13de7f46 | 884 | .fifo = nv40_fifo_new, |
c85ee6ca | 885 | .gr = nv44_gr_new, |
7624fc01 | 886 | .mpeg = nv44_mpeg_new, |
97070f23 | 887 | .pm = nv40_pm_new, |
6f41c7c5 | 888 | .sw = nv10_sw_new, |
6cf813fb BS |
889 | }; |
890 | ||
891 | static const struct nvkm_device_chip | |
892 | nv68_chipset = { | |
893 | .name = "C68", | |
46484438 | 894 | .bios = nvkm_bios_new, |
bb23f9d7 | 895 | .bus = nv31_bus_new, |
6625f55c | 896 | .clk = nv40_clk_new, |
151abd44 | 897 | .devinit = nv1a_devinit_new, |
03c8952f | 898 | .fb = nv46_fb_new, |
2ea7249f | 899 | .gpio = nv10_gpio_new, |
49bd8da5 | 900 | .i2c = nv04_i2c_new, |
b7a2bc18 | 901 | .imem = nv40_instmem_new, |
2b700825 | 902 | .mc = nv44_mc_new, |
c9582455 | 903 | .mmu = nv44_mmu_new, |
0a34fb31 | 904 | .pci = nv4c_pci_new, |
57113c01 | 905 | .therm = nv40_therm_new, |
31649ecf | 906 | .timer = nv41_timer_new, |
437b2296 | 907 | .volt = nv40_volt_new, |
70aa8670 | 908 | .disp = nv04_disp_new, |
bd70563f | 909 | .dma = nv04_dma_new, |
13de7f46 | 910 | .fifo = nv40_fifo_new, |
c85ee6ca | 911 | .gr = nv44_gr_new, |
7624fc01 | 912 | .mpeg = nv44_mpeg_new, |
97070f23 | 913 | .pm = nv40_pm_new, |
6f41c7c5 | 914 | .sw = nv10_sw_new, |
6cf813fb BS |
915 | }; |
916 | ||
917 | static const struct nvkm_device_chip | |
918 | nv84_chipset = { | |
919 | .name = "G84", | |
32932281 | 920 | .bar = g84_bar_new, |
46484438 | 921 | .bios = nvkm_bios_new, |
bb23f9d7 | 922 | .bus = nv50_bus_new, |
6625f55c | 923 | .clk = g84_clk_new, |
151abd44 | 924 | .devinit = g84_devinit_new, |
03c8952f | 925 | .fb = g84_fb_new, |
c5fcafa5 | 926 | .fuse = nv50_fuse_new, |
2ea7249f | 927 | .gpio = nv50_gpio_new, |
49bd8da5 | 928 | .i2c = nv50_i2c_new, |
b7a2bc18 | 929 | .imem = nv50_instmem_new, |
73549020 | 930 | .mc = g84_mc_new, |
0f43715f | 931 | .mmu = g84_mmu_new, |
a4f7bd36 | 932 | .mxm = nv50_mxm_new, |
3e55b53b | 933 | .pci = g84_pci_new, |
57113c01 | 934 | .therm = g84_therm_new, |
31649ecf | 935 | .timer = nv41_timer_new, |
437b2296 | 936 | .volt = nv40_volt_new, |
98b20c9a | 937 | .bsp = g84_bsp_new, |
14d74aca | 938 | .cipher = g84_cipher_new, |
70aa8670 | 939 | .disp = g84_disp_new, |
bd70563f | 940 | .dma = nv50_dma_new, |
13de7f46 | 941 | .fifo = g84_fifo_new, |
c85ee6ca | 942 | .gr = g84_gr_new, |
7624fc01 | 943 | .mpeg = g84_mpeg_new, |
97070f23 | 944 | .pm = g84_pm_new, |
6f41c7c5 | 945 | .sw = nv50_sw_new, |
98b20c9a | 946 | .vp = g84_vp_new, |
6cf813fb BS |
947 | }; |
948 | ||
949 | static const struct nvkm_device_chip | |
950 | nv86_chipset = { | |
951 | .name = "G86", | |
32932281 | 952 | .bar = g84_bar_new, |
46484438 | 953 | .bios = nvkm_bios_new, |
bb23f9d7 | 954 | .bus = nv50_bus_new, |
6625f55c | 955 | .clk = g84_clk_new, |
151abd44 | 956 | .devinit = g84_devinit_new, |
03c8952f | 957 | .fb = g84_fb_new, |
c5fcafa5 | 958 | .fuse = nv50_fuse_new, |
2ea7249f | 959 | .gpio = nv50_gpio_new, |
49bd8da5 | 960 | .i2c = nv50_i2c_new, |
b7a2bc18 | 961 | .imem = nv50_instmem_new, |
73549020 | 962 | .mc = g84_mc_new, |
0f43715f | 963 | .mmu = g84_mmu_new, |
a4f7bd36 | 964 | .mxm = nv50_mxm_new, |
3e55b53b | 965 | .pci = g84_pci_new, |
57113c01 | 966 | .therm = g84_therm_new, |
31649ecf | 967 | .timer = nv41_timer_new, |
437b2296 | 968 | .volt = nv40_volt_new, |
98b20c9a | 969 | .bsp = g84_bsp_new, |
14d74aca | 970 | .cipher = g84_cipher_new, |
70aa8670 | 971 | .disp = g84_disp_new, |
bd70563f | 972 | .dma = nv50_dma_new, |
13de7f46 | 973 | .fifo = g84_fifo_new, |
c85ee6ca | 974 | .gr = g84_gr_new, |
7624fc01 | 975 | .mpeg = g84_mpeg_new, |
97070f23 | 976 | .pm = g84_pm_new, |
6f41c7c5 | 977 | .sw = nv50_sw_new, |
98b20c9a | 978 | .vp = g84_vp_new, |
6cf813fb BS |
979 | }; |
980 | ||
981 | static const struct nvkm_device_chip | |
982 | nv92_chipset = { | |
983 | .name = "G92", | |
32932281 | 984 | .bar = g84_bar_new, |
46484438 | 985 | .bios = nvkm_bios_new, |
bb23f9d7 | 986 | .bus = nv50_bus_new, |
6625f55c | 987 | .clk = g84_clk_new, |
151abd44 | 988 | .devinit = g84_devinit_new, |
03c8952f | 989 | .fb = g84_fb_new, |
c5fcafa5 | 990 | .fuse = nv50_fuse_new, |
2ea7249f | 991 | .gpio = nv50_gpio_new, |
49bd8da5 | 992 | .i2c = nv50_i2c_new, |
b7a2bc18 | 993 | .imem = nv50_instmem_new, |
73549020 | 994 | .mc = g84_mc_new, |
0f43715f | 995 | .mmu = g84_mmu_new, |
a4f7bd36 | 996 | .mxm = nv50_mxm_new, |
443828fd | 997 | .pci = g92_pci_new, |
57113c01 | 998 | .therm = g84_therm_new, |
31649ecf | 999 | .timer = nv41_timer_new, |
437b2296 | 1000 | .volt = nv40_volt_new, |
98b20c9a | 1001 | .bsp = g84_bsp_new, |
14d74aca | 1002 | .cipher = g84_cipher_new, |
70aa8670 | 1003 | .disp = g84_disp_new, |
bd70563f | 1004 | .dma = nv50_dma_new, |
13de7f46 | 1005 | .fifo = g84_fifo_new, |
c85ee6ca | 1006 | .gr = g84_gr_new, |
7624fc01 | 1007 | .mpeg = g84_mpeg_new, |
97070f23 | 1008 | .pm = g84_pm_new, |
6f41c7c5 | 1009 | .sw = nv50_sw_new, |
98b20c9a | 1010 | .vp = g84_vp_new, |
6cf813fb BS |
1011 | }; |
1012 | ||
1013 | static const struct nvkm_device_chip | |
1014 | nv94_chipset = { | |
1015 | .name = "G94", | |
32932281 | 1016 | .bar = g84_bar_new, |
46484438 | 1017 | .bios = nvkm_bios_new, |
bb23f9d7 | 1018 | .bus = g94_bus_new, |
6625f55c | 1019 | .clk = g84_clk_new, |
151abd44 | 1020 | .devinit = g84_devinit_new, |
03c8952f | 1021 | .fb = g84_fb_new, |
c5fcafa5 | 1022 | .fuse = nv50_fuse_new, |
2ea7249f | 1023 | .gpio = g94_gpio_new, |
49bd8da5 | 1024 | .i2c = g94_i2c_new, |
b7a2bc18 | 1025 | .imem = nv50_instmem_new, |
73549020 | 1026 | .mc = g84_mc_new, |
0f43715f | 1027 | .mmu = g84_mmu_new, |
a4f7bd36 | 1028 | .mxm = nv50_mxm_new, |
5112abc6 | 1029 | .pci = g94_pci_new, |
57113c01 | 1030 | .therm = g84_therm_new, |
31649ecf | 1031 | .timer = nv41_timer_new, |
437b2296 | 1032 | .volt = nv40_volt_new, |
98b20c9a | 1033 | .bsp = g84_bsp_new, |
14d74aca | 1034 | .cipher = g84_cipher_new, |
70aa8670 | 1035 | .disp = g94_disp_new, |
bd70563f | 1036 | .dma = nv50_dma_new, |
13de7f46 | 1037 | .fifo = g84_fifo_new, |
c85ee6ca | 1038 | .gr = g84_gr_new, |
7624fc01 | 1039 | .mpeg = g84_mpeg_new, |
97070f23 | 1040 | .pm = g84_pm_new, |
6f41c7c5 | 1041 | .sw = nv50_sw_new, |
98b20c9a | 1042 | .vp = g84_vp_new, |
6cf813fb BS |
1043 | }; |
1044 | ||
1045 | static const struct nvkm_device_chip | |
1046 | nv96_chipset = { | |
1047 | .name = "G96", | |
0a34fb31 | 1048 | .bar = g84_bar_new, |
46484438 | 1049 | .bios = nvkm_bios_new, |
0a34fb31 | 1050 | .bus = g94_bus_new, |
6625f55c | 1051 | .clk = g84_clk_new, |
151abd44 | 1052 | .devinit = g84_devinit_new, |
03c8952f | 1053 | .fb = g84_fb_new, |
0a34fb31 BS |
1054 | .fuse = nv50_fuse_new, |
1055 | .gpio = g94_gpio_new, | |
1056 | .i2c = g94_i2c_new, | |
b7a2bc18 | 1057 | .imem = nv50_instmem_new, |
73549020 | 1058 | .mc = g84_mc_new, |
0f43715f | 1059 | .mmu = g84_mmu_new, |
0a34fb31 | 1060 | .mxm = nv50_mxm_new, |
5112abc6 | 1061 | .pci = g94_pci_new, |
0a34fb31 BS |
1062 | .therm = g84_therm_new, |
1063 | .timer = nv41_timer_new, | |
437b2296 | 1064 | .volt = nv40_volt_new, |
0a34fb31 BS |
1065 | .bsp = g84_bsp_new, |
1066 | .cipher = g84_cipher_new, | |
1067 | .disp = g94_disp_new, | |
bd70563f | 1068 | .dma = nv50_dma_new, |
13de7f46 | 1069 | .fifo = g84_fifo_new, |
c85ee6ca | 1070 | .gr = g84_gr_new, |
7624fc01 | 1071 | .mpeg = g84_mpeg_new, |
97070f23 | 1072 | .pm = g84_pm_new, |
0a34fb31 BS |
1073 | .sw = nv50_sw_new, |
1074 | .vp = g84_vp_new, | |
6cf813fb BS |
1075 | }; |
1076 | ||
1077 | static const struct nvkm_device_chip | |
1078 | nv98_chipset = { | |
1079 | .name = "G98", | |
0a34fb31 | 1080 | .bar = g84_bar_new, |
46484438 | 1081 | .bios = nvkm_bios_new, |
0a34fb31 | 1082 | .bus = g94_bus_new, |
6625f55c | 1083 | .clk = g84_clk_new, |
151abd44 | 1084 | .devinit = g98_devinit_new, |
03c8952f | 1085 | .fb = g84_fb_new, |
0a34fb31 BS |
1086 | .fuse = nv50_fuse_new, |
1087 | .gpio = g94_gpio_new, | |
1088 | .i2c = g94_i2c_new, | |
b7a2bc18 | 1089 | .imem = nv50_instmem_new, |
0a34fb31 | 1090 | .mc = g98_mc_new, |
0f43715f | 1091 | .mmu = g84_mmu_new, |
0a34fb31 | 1092 | .mxm = nv50_mxm_new, |
5112abc6 | 1093 | .pci = g94_pci_new, |
0a34fb31 BS |
1094 | .therm = g84_therm_new, |
1095 | .timer = nv41_timer_new, | |
437b2296 | 1096 | .volt = nv40_volt_new, |
0a34fb31 | 1097 | .disp = g94_disp_new, |
bd70563f | 1098 | .dma = nv50_dma_new, |
13de7f46 | 1099 | .fifo = g84_fifo_new, |
c85ee6ca | 1100 | .gr = g84_gr_new, |
53e60da4 | 1101 | .mspdec = g98_mspdec_new, |
53e60da4 | 1102 | .msppp = g98_msppp_new, |
0a34fb31 | 1103 | .msvld = g98_msvld_new, |
97070f23 | 1104 | .pm = g84_pm_new, |
0a34fb31 BS |
1105 | .sec = g98_sec_new, |
1106 | .sw = nv50_sw_new, | |
6cf813fb BS |
1107 | }; |
1108 | ||
1109 | static const struct nvkm_device_chip | |
1110 | nva0_chipset = { | |
1111 | .name = "GT200", | |
32932281 | 1112 | .bar = g84_bar_new, |
46484438 | 1113 | .bios = nvkm_bios_new, |
bb23f9d7 | 1114 | .bus = g94_bus_new, |
6625f55c | 1115 | .clk = g84_clk_new, |
151abd44 | 1116 | .devinit = g84_devinit_new, |
03c8952f | 1117 | .fb = g84_fb_new, |
c5fcafa5 | 1118 | .fuse = nv50_fuse_new, |
2ea7249f | 1119 | .gpio = g94_gpio_new, |
49bd8da5 | 1120 | .i2c = nv50_i2c_new, |
b7a2bc18 | 1121 | .imem = nv50_instmem_new, |
73549020 | 1122 | .mc = g84_mc_new, |
0f43715f | 1123 | .mmu = g84_mmu_new, |
a4f7bd36 | 1124 | .mxm = nv50_mxm_new, |
5112abc6 | 1125 | .pci = g94_pci_new, |
57113c01 | 1126 | .therm = g84_therm_new, |
31649ecf | 1127 | .timer = nv41_timer_new, |
437b2296 | 1128 | .volt = nv40_volt_new, |
98b20c9a | 1129 | .bsp = g84_bsp_new, |
14d74aca | 1130 | .cipher = g84_cipher_new, |
70aa8670 | 1131 | .disp = gt200_disp_new, |
bd70563f | 1132 | .dma = nv50_dma_new, |
13de7f46 | 1133 | .fifo = g84_fifo_new, |
c85ee6ca | 1134 | .gr = gt200_gr_new, |
7624fc01 | 1135 | .mpeg = g84_mpeg_new, |
97070f23 | 1136 | .pm = gt200_pm_new, |
6f41c7c5 | 1137 | .sw = nv50_sw_new, |
98b20c9a | 1138 | .vp = g84_vp_new, |
6cf813fb BS |
1139 | }; |
1140 | ||
1141 | static const struct nvkm_device_chip | |
1142 | nva3_chipset = { | |
1143 | .name = "GT215", | |
32932281 | 1144 | .bar = g84_bar_new, |
46484438 | 1145 | .bios = nvkm_bios_new, |
bb23f9d7 | 1146 | .bus = g94_bus_new, |
6625f55c | 1147 | .clk = gt215_clk_new, |
151abd44 | 1148 | .devinit = gt215_devinit_new, |
03c8952f | 1149 | .fb = gt215_fb_new, |
c5fcafa5 | 1150 | .fuse = nv50_fuse_new, |
2ea7249f | 1151 | .gpio = g94_gpio_new, |
49bd8da5 | 1152 | .i2c = g94_i2c_new, |
b7a2bc18 | 1153 | .imem = nv50_instmem_new, |
88c0de2c | 1154 | .mc = gt215_mc_new, |
0f43715f | 1155 | .mmu = g84_mmu_new, |
a4f7bd36 | 1156 | .mxm = nv50_mxm_new, |
5112abc6 | 1157 | .pci = g94_pci_new, |
e2ca4e7d | 1158 | .pmu = gt215_pmu_new, |
57113c01 | 1159 | .therm = gt215_therm_new, |
31649ecf | 1160 | .timer = nv41_timer_new, |
437b2296 | 1161 | .volt = nv40_volt_new, |
53e60da4 | 1162 | .ce[0] = gt215_ce_new, |
70aa8670 | 1163 | .disp = gt215_disp_new, |
bd70563f | 1164 | .dma = nv50_dma_new, |
13de7f46 | 1165 | .fifo = g84_fifo_new, |
c85ee6ca | 1166 | .gr = gt215_gr_new, |
7624fc01 | 1167 | .mpeg = g84_mpeg_new, |
53e60da4 BS |
1168 | .mspdec = gt215_mspdec_new, |
1169 | .msppp = gt215_msppp_new, | |
1170 | .msvld = gt215_msvld_new, | |
97070f23 | 1171 | .pm = gt215_pm_new, |
6f41c7c5 | 1172 | .sw = nv50_sw_new, |
6cf813fb BS |
1173 | }; |
1174 | ||
1175 | static const struct nvkm_device_chip | |
1176 | nva5_chipset = { | |
1177 | .name = "GT216", | |
32932281 | 1178 | .bar = g84_bar_new, |
46484438 | 1179 | .bios = nvkm_bios_new, |
bb23f9d7 | 1180 | .bus = g94_bus_new, |
6625f55c | 1181 | .clk = gt215_clk_new, |
151abd44 | 1182 | .devinit = gt215_devinit_new, |
03c8952f | 1183 | .fb = gt215_fb_new, |
c5fcafa5 | 1184 | .fuse = nv50_fuse_new, |
2ea7249f | 1185 | .gpio = g94_gpio_new, |
49bd8da5 | 1186 | .i2c = g94_i2c_new, |
b7a2bc18 | 1187 | .imem = nv50_instmem_new, |
88c0de2c | 1188 | .mc = gt215_mc_new, |
0f43715f | 1189 | .mmu = g84_mmu_new, |
a4f7bd36 | 1190 | .mxm = nv50_mxm_new, |
5112abc6 | 1191 | .pci = g94_pci_new, |
e2ca4e7d | 1192 | .pmu = gt215_pmu_new, |
57113c01 | 1193 | .therm = gt215_therm_new, |
31649ecf | 1194 | .timer = nv41_timer_new, |
437b2296 | 1195 | .volt = nv40_volt_new, |
53e60da4 | 1196 | .ce[0] = gt215_ce_new, |
70aa8670 | 1197 | .disp = gt215_disp_new, |
bd70563f | 1198 | .dma = nv50_dma_new, |
13de7f46 | 1199 | .fifo = g84_fifo_new, |
c85ee6ca | 1200 | .gr = gt215_gr_new, |
53e60da4 BS |
1201 | .mspdec = gt215_mspdec_new, |
1202 | .msppp = gt215_msppp_new, | |
1203 | .msvld = gt215_msvld_new, | |
97070f23 | 1204 | .pm = gt215_pm_new, |
6f41c7c5 | 1205 | .sw = nv50_sw_new, |
6cf813fb BS |
1206 | }; |
1207 | ||
1208 | static const struct nvkm_device_chip | |
1209 | nva8_chipset = { | |
1210 | .name = "GT218", | |
32932281 | 1211 | .bar = g84_bar_new, |
46484438 | 1212 | .bios = nvkm_bios_new, |
bb23f9d7 | 1213 | .bus = g94_bus_new, |
6625f55c | 1214 | .clk = gt215_clk_new, |
151abd44 | 1215 | .devinit = gt215_devinit_new, |
03c8952f | 1216 | .fb = gt215_fb_new, |
c5fcafa5 | 1217 | .fuse = nv50_fuse_new, |
2ea7249f | 1218 | .gpio = g94_gpio_new, |
49bd8da5 | 1219 | .i2c = g94_i2c_new, |
b7a2bc18 | 1220 | .imem = nv50_instmem_new, |
88c0de2c | 1221 | .mc = gt215_mc_new, |
0f43715f | 1222 | .mmu = g84_mmu_new, |
a4f7bd36 | 1223 | .mxm = nv50_mxm_new, |
5112abc6 | 1224 | .pci = g94_pci_new, |
e2ca4e7d | 1225 | .pmu = gt215_pmu_new, |
57113c01 | 1226 | .therm = gt215_therm_new, |
31649ecf | 1227 | .timer = nv41_timer_new, |
437b2296 | 1228 | .volt = nv40_volt_new, |
53e60da4 | 1229 | .ce[0] = gt215_ce_new, |
70aa8670 | 1230 | .disp = gt215_disp_new, |
bd70563f | 1231 | .dma = nv50_dma_new, |
13de7f46 | 1232 | .fifo = g84_fifo_new, |
c85ee6ca | 1233 | .gr = gt215_gr_new, |
53e60da4 BS |
1234 | .mspdec = gt215_mspdec_new, |
1235 | .msppp = gt215_msppp_new, | |
1236 | .msvld = gt215_msvld_new, | |
97070f23 | 1237 | .pm = gt215_pm_new, |
6f41c7c5 | 1238 | .sw = nv50_sw_new, |
6cf813fb BS |
1239 | }; |
1240 | ||
1241 | static const struct nvkm_device_chip | |
1242 | nvaa_chipset = { | |
1243 | .name = "MCP77/MCP78", | |
32932281 | 1244 | .bar = g84_bar_new, |
46484438 | 1245 | .bios = nvkm_bios_new, |
bb23f9d7 | 1246 | .bus = g94_bus_new, |
6625f55c | 1247 | .clk = mcp77_clk_new, |
151abd44 | 1248 | .devinit = g98_devinit_new, |
03c8952f | 1249 | .fb = mcp77_fb_new, |
c5fcafa5 | 1250 | .fuse = nv50_fuse_new, |
2ea7249f | 1251 | .gpio = g94_gpio_new, |
49bd8da5 | 1252 | .i2c = g94_i2c_new, |
b7a2bc18 | 1253 | .imem = nv50_instmem_new, |
54dcadd5 | 1254 | .mc = g98_mc_new, |
2ffa64eb | 1255 | .mmu = mcp77_mmu_new, |
a4f7bd36 | 1256 | .mxm = nv50_mxm_new, |
5112abc6 | 1257 | .pci = g94_pci_new, |
57113c01 | 1258 | .therm = g84_therm_new, |
31649ecf | 1259 | .timer = nv41_timer_new, |
437b2296 | 1260 | .volt = nv40_volt_new, |
b3c9c022 | 1261 | .disp = mcp77_disp_new, |
bd70563f | 1262 | .dma = nv50_dma_new, |
13de7f46 | 1263 | .fifo = g84_fifo_new, |
c85ee6ca | 1264 | .gr = gt200_gr_new, |
53e60da4 BS |
1265 | .mspdec = g98_mspdec_new, |
1266 | .msppp = g98_msppp_new, | |
1267 | .msvld = g98_msvld_new, | |
97070f23 | 1268 | .pm = g84_pm_new, |
53e60da4 | 1269 | .sec = g98_sec_new, |
6f41c7c5 | 1270 | .sw = nv50_sw_new, |
6cf813fb BS |
1271 | }; |
1272 | ||
1273 | static const struct nvkm_device_chip | |
1274 | nvac_chipset = { | |
1275 | .name = "MCP79/MCP7A", | |
32932281 | 1276 | .bar = g84_bar_new, |
46484438 | 1277 | .bios = nvkm_bios_new, |
bb23f9d7 | 1278 | .bus = g94_bus_new, |
6625f55c | 1279 | .clk = mcp77_clk_new, |
151abd44 | 1280 | .devinit = g98_devinit_new, |
03c8952f | 1281 | .fb = mcp77_fb_new, |
c5fcafa5 | 1282 | .fuse = nv50_fuse_new, |
2ea7249f | 1283 | .gpio = g94_gpio_new, |
49bd8da5 | 1284 | .i2c = g94_i2c_new, |
b7a2bc18 | 1285 | .imem = nv50_instmem_new, |
54dcadd5 | 1286 | .mc = g98_mc_new, |
2ffa64eb | 1287 | .mmu = mcp77_mmu_new, |
a4f7bd36 | 1288 | .mxm = nv50_mxm_new, |
5112abc6 | 1289 | .pci = g94_pci_new, |
57113c01 | 1290 | .therm = g84_therm_new, |
31649ecf | 1291 | .timer = nv41_timer_new, |
437b2296 | 1292 | .volt = nv40_volt_new, |
b3c9c022 | 1293 | .disp = mcp77_disp_new, |
bd70563f | 1294 | .dma = nv50_dma_new, |
13de7f46 | 1295 | .fifo = g84_fifo_new, |
c85ee6ca | 1296 | .gr = mcp79_gr_new, |
53e60da4 BS |
1297 | .mspdec = g98_mspdec_new, |
1298 | .msppp = g98_msppp_new, | |
1299 | .msvld = g98_msvld_new, | |
97070f23 | 1300 | .pm = g84_pm_new, |
53e60da4 | 1301 | .sec = g98_sec_new, |
6f41c7c5 | 1302 | .sw = nv50_sw_new, |
6cf813fb BS |
1303 | }; |
1304 | ||
1305 | static const struct nvkm_device_chip | |
1306 | nvaf_chipset = { | |
1307 | .name = "MCP89", | |
32932281 | 1308 | .bar = g84_bar_new, |
46484438 | 1309 | .bios = nvkm_bios_new, |
bb23f9d7 | 1310 | .bus = g94_bus_new, |
6625f55c | 1311 | .clk = gt215_clk_new, |
151abd44 | 1312 | .devinit = mcp89_devinit_new, |
03c8952f | 1313 | .fb = mcp89_fb_new, |
c5fcafa5 | 1314 | .fuse = nv50_fuse_new, |
2ea7249f | 1315 | .gpio = g94_gpio_new, |
49bd8da5 | 1316 | .i2c = g94_i2c_new, |
b7a2bc18 | 1317 | .imem = nv50_instmem_new, |
88c0de2c | 1318 | .mc = gt215_mc_new, |
0f43715f | 1319 | .mmu = g84_mmu_new, |
a4f7bd36 | 1320 | .mxm = nv50_mxm_new, |
5112abc6 | 1321 | .pci = g94_pci_new, |
e2ca4e7d | 1322 | .pmu = gt215_pmu_new, |
57113c01 | 1323 | .therm = gt215_therm_new, |
31649ecf | 1324 | .timer = nv41_timer_new, |
437b2296 | 1325 | .volt = nv40_volt_new, |
53e60da4 | 1326 | .ce[0] = gt215_ce_new, |
b3c9c022 | 1327 | .disp = mcp89_disp_new, |
bd70563f | 1328 | .dma = nv50_dma_new, |
13de7f46 | 1329 | .fifo = g84_fifo_new, |
c85ee6ca | 1330 | .gr = mcp89_gr_new, |
53e60da4 BS |
1331 | .mspdec = gt215_mspdec_new, |
1332 | .msppp = gt215_msppp_new, | |
1333 | .msvld = mcp89_msvld_new, | |
97070f23 | 1334 | .pm = gt215_pm_new, |
6f41c7c5 | 1335 | .sw = nv50_sw_new, |
6cf813fb BS |
1336 | }; |
1337 | ||
1338 | static const struct nvkm_device_chip | |
1339 | nvc0_chipset = { | |
1340 | .name = "GF100", | |
32932281 | 1341 | .bar = gf100_bar_new, |
46484438 | 1342 | .bios = nvkm_bios_new, |
bb23f9d7 | 1343 | .bus = gf100_bus_new, |
6625f55c | 1344 | .clk = gf100_clk_new, |
151abd44 | 1345 | .devinit = gf100_devinit_new, |
03c8952f | 1346 | .fb = gf100_fb_new, |
c5fcafa5 | 1347 | .fuse = gf100_fuse_new, |
2ea7249f | 1348 | .gpio = g94_gpio_new, |
49bd8da5 | 1349 | .i2c = g94_i2c_new, |
551d3417 | 1350 | .ibus = gf100_ibus_new, |
b71c0892 | 1351 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1352 | .imem = nv50_instmem_new, |
70bc7182 | 1353 | .ltc = gf100_ltc_new, |
54dcadd5 | 1354 | .mc = gf100_mc_new, |
c9582455 | 1355 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1356 | .mxm = nv50_mxm_new, |
0a34fb31 | 1357 | .pci = gf100_pci_new, |
e2ca4e7d | 1358 | .pmu = gf100_pmu_new, |
57113c01 | 1359 | .therm = gt215_therm_new, |
31649ecf | 1360 | .timer = nv41_timer_new, |
a3c950f2 | 1361 | .volt = gf100_volt_new, |
53e60da4 BS |
1362 | .ce[0] = gf100_ce_new, |
1363 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1364 | .disp = gt215_disp_new, |
bd70563f | 1365 | .dma = gf100_dma_new, |
13de7f46 | 1366 | .fifo = gf100_fifo_new, |
c85ee6ca | 1367 | .gr = gf100_gr_new, |
53e60da4 BS |
1368 | .mspdec = gf100_mspdec_new, |
1369 | .msppp = gf100_msppp_new, | |
1370 | .msvld = gf100_msvld_new, | |
97070f23 | 1371 | .pm = gf100_pm_new, |
6f41c7c5 | 1372 | .sw = gf100_sw_new, |
6cf813fb BS |
1373 | }; |
1374 | ||
1375 | static const struct nvkm_device_chip | |
1376 | nvc1_chipset = { | |
1377 | .name = "GF108", | |
32932281 | 1378 | .bar = gf100_bar_new, |
46484438 | 1379 | .bios = nvkm_bios_new, |
bb23f9d7 | 1380 | .bus = gf100_bus_new, |
6625f55c | 1381 | .clk = gf100_clk_new, |
151abd44 | 1382 | .devinit = gf100_devinit_new, |
904e703c | 1383 | .fb = gf108_fb_new, |
c5fcafa5 | 1384 | .fuse = gf100_fuse_new, |
2ea7249f | 1385 | .gpio = g94_gpio_new, |
49bd8da5 | 1386 | .i2c = g94_i2c_new, |
551d3417 | 1387 | .ibus = gf100_ibus_new, |
b71c0892 | 1388 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1389 | .imem = nv50_instmem_new, |
70bc7182 | 1390 | .ltc = gf100_ltc_new, |
2b700825 | 1391 | .mc = gf100_mc_new, |
c9582455 | 1392 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1393 | .mxm = nv50_mxm_new, |
bec4961e | 1394 | .pci = gf106_pci_new, |
e2ca4e7d | 1395 | .pmu = gf100_pmu_new, |
57113c01 | 1396 | .therm = gt215_therm_new, |
31649ecf | 1397 | .timer = nv41_timer_new, |
a3c950f2 | 1398 | .volt = gf100_volt_new, |
53e60da4 | 1399 | .ce[0] = gf100_ce_new, |
70aa8670 | 1400 | .disp = gt215_disp_new, |
bd70563f | 1401 | .dma = gf100_dma_new, |
13de7f46 | 1402 | .fifo = gf100_fifo_new, |
c85ee6ca | 1403 | .gr = gf108_gr_new, |
53e60da4 BS |
1404 | .mspdec = gf100_mspdec_new, |
1405 | .msppp = gf100_msppp_new, | |
1406 | .msvld = gf100_msvld_new, | |
97070f23 | 1407 | .pm = gf108_pm_new, |
6f41c7c5 | 1408 | .sw = gf100_sw_new, |
6cf813fb BS |
1409 | }; |
1410 | ||
1411 | static const struct nvkm_device_chip | |
1412 | nvc3_chipset = { | |
1413 | .name = "GF106", | |
32932281 | 1414 | .bar = gf100_bar_new, |
46484438 | 1415 | .bios = nvkm_bios_new, |
bb23f9d7 | 1416 | .bus = gf100_bus_new, |
6625f55c | 1417 | .clk = gf100_clk_new, |
151abd44 | 1418 | .devinit = gf100_devinit_new, |
03c8952f | 1419 | .fb = gf100_fb_new, |
c5fcafa5 | 1420 | .fuse = gf100_fuse_new, |
2ea7249f | 1421 | .gpio = g94_gpio_new, |
49bd8da5 | 1422 | .i2c = g94_i2c_new, |
551d3417 | 1423 | .ibus = gf100_ibus_new, |
b71c0892 | 1424 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1425 | .imem = nv50_instmem_new, |
70bc7182 | 1426 | .ltc = gf100_ltc_new, |
2b700825 | 1427 | .mc = gf100_mc_new, |
c9582455 | 1428 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1429 | .mxm = nv50_mxm_new, |
bec4961e | 1430 | .pci = gf106_pci_new, |
e2ca4e7d | 1431 | .pmu = gf100_pmu_new, |
57113c01 | 1432 | .therm = gt215_therm_new, |
31649ecf | 1433 | .timer = nv41_timer_new, |
a3c950f2 | 1434 | .volt = gf100_volt_new, |
53e60da4 | 1435 | .ce[0] = gf100_ce_new, |
70aa8670 | 1436 | .disp = gt215_disp_new, |
bd70563f | 1437 | .dma = gf100_dma_new, |
13de7f46 | 1438 | .fifo = gf100_fifo_new, |
c85ee6ca | 1439 | .gr = gf104_gr_new, |
53e60da4 BS |
1440 | .mspdec = gf100_mspdec_new, |
1441 | .msppp = gf100_msppp_new, | |
1442 | .msvld = gf100_msvld_new, | |
97070f23 | 1443 | .pm = gf100_pm_new, |
6f41c7c5 | 1444 | .sw = gf100_sw_new, |
6cf813fb BS |
1445 | }; |
1446 | ||
1447 | static const struct nvkm_device_chip | |
1448 | nvc4_chipset = { | |
1449 | .name = "GF104", | |
32932281 | 1450 | .bar = gf100_bar_new, |
46484438 | 1451 | .bios = nvkm_bios_new, |
bb23f9d7 | 1452 | .bus = gf100_bus_new, |
6625f55c | 1453 | .clk = gf100_clk_new, |
151abd44 | 1454 | .devinit = gf100_devinit_new, |
03c8952f | 1455 | .fb = gf100_fb_new, |
c5fcafa5 | 1456 | .fuse = gf100_fuse_new, |
2ea7249f | 1457 | .gpio = g94_gpio_new, |
49bd8da5 | 1458 | .i2c = g94_i2c_new, |
551d3417 | 1459 | .ibus = gf100_ibus_new, |
b71c0892 | 1460 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1461 | .imem = nv50_instmem_new, |
70bc7182 | 1462 | .ltc = gf100_ltc_new, |
54dcadd5 | 1463 | .mc = gf100_mc_new, |
c9582455 | 1464 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1465 | .mxm = nv50_mxm_new, |
0a34fb31 | 1466 | .pci = gf100_pci_new, |
e2ca4e7d | 1467 | .pmu = gf100_pmu_new, |
57113c01 | 1468 | .therm = gt215_therm_new, |
31649ecf | 1469 | .timer = nv41_timer_new, |
a3c950f2 | 1470 | .volt = gf100_volt_new, |
53e60da4 BS |
1471 | .ce[0] = gf100_ce_new, |
1472 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1473 | .disp = gt215_disp_new, |
bd70563f | 1474 | .dma = gf100_dma_new, |
13de7f46 | 1475 | .fifo = gf100_fifo_new, |
c85ee6ca | 1476 | .gr = gf104_gr_new, |
53e60da4 BS |
1477 | .mspdec = gf100_mspdec_new, |
1478 | .msppp = gf100_msppp_new, | |
1479 | .msvld = gf100_msvld_new, | |
97070f23 | 1480 | .pm = gf100_pm_new, |
6f41c7c5 | 1481 | .sw = gf100_sw_new, |
6cf813fb BS |
1482 | }; |
1483 | ||
1484 | static const struct nvkm_device_chip | |
1485 | nvc8_chipset = { | |
1486 | .name = "GF110", | |
32932281 | 1487 | .bar = gf100_bar_new, |
46484438 | 1488 | .bios = nvkm_bios_new, |
bb23f9d7 | 1489 | .bus = gf100_bus_new, |
6625f55c | 1490 | .clk = gf100_clk_new, |
151abd44 | 1491 | .devinit = gf100_devinit_new, |
03c8952f | 1492 | .fb = gf100_fb_new, |
c5fcafa5 | 1493 | .fuse = gf100_fuse_new, |
2ea7249f | 1494 | .gpio = g94_gpio_new, |
49bd8da5 | 1495 | .i2c = g94_i2c_new, |
551d3417 | 1496 | .ibus = gf100_ibus_new, |
b71c0892 | 1497 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1498 | .imem = nv50_instmem_new, |
70bc7182 | 1499 | .ltc = gf100_ltc_new, |
54dcadd5 | 1500 | .mc = gf100_mc_new, |
c9582455 | 1501 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1502 | .mxm = nv50_mxm_new, |
0a34fb31 | 1503 | .pci = gf100_pci_new, |
e2ca4e7d | 1504 | .pmu = gf100_pmu_new, |
57113c01 | 1505 | .therm = gt215_therm_new, |
31649ecf | 1506 | .timer = nv41_timer_new, |
a3c950f2 | 1507 | .volt = gf100_volt_new, |
53e60da4 BS |
1508 | .ce[0] = gf100_ce_new, |
1509 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1510 | .disp = gt215_disp_new, |
bd70563f | 1511 | .dma = gf100_dma_new, |
13de7f46 | 1512 | .fifo = gf100_fifo_new, |
c85ee6ca | 1513 | .gr = gf110_gr_new, |
53e60da4 BS |
1514 | .mspdec = gf100_mspdec_new, |
1515 | .msppp = gf100_msppp_new, | |
1516 | .msvld = gf100_msvld_new, | |
97070f23 | 1517 | .pm = gf100_pm_new, |
6f41c7c5 | 1518 | .sw = gf100_sw_new, |
6cf813fb BS |
1519 | }; |
1520 | ||
1521 | static const struct nvkm_device_chip | |
1522 | nvce_chipset = { | |
1523 | .name = "GF114", | |
32932281 | 1524 | .bar = gf100_bar_new, |
46484438 | 1525 | .bios = nvkm_bios_new, |
bb23f9d7 | 1526 | .bus = gf100_bus_new, |
6625f55c | 1527 | .clk = gf100_clk_new, |
151abd44 | 1528 | .devinit = gf100_devinit_new, |
03c8952f | 1529 | .fb = gf100_fb_new, |
c5fcafa5 | 1530 | .fuse = gf100_fuse_new, |
2ea7249f | 1531 | .gpio = g94_gpio_new, |
49bd8da5 | 1532 | .i2c = g94_i2c_new, |
551d3417 | 1533 | .ibus = gf100_ibus_new, |
b71c0892 | 1534 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1535 | .imem = nv50_instmem_new, |
70bc7182 | 1536 | .ltc = gf100_ltc_new, |
54dcadd5 | 1537 | .mc = gf100_mc_new, |
c9582455 | 1538 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1539 | .mxm = nv50_mxm_new, |
0a34fb31 | 1540 | .pci = gf100_pci_new, |
e2ca4e7d | 1541 | .pmu = gf100_pmu_new, |
57113c01 | 1542 | .therm = gt215_therm_new, |
31649ecf | 1543 | .timer = nv41_timer_new, |
a3c950f2 | 1544 | .volt = gf100_volt_new, |
53e60da4 BS |
1545 | .ce[0] = gf100_ce_new, |
1546 | .ce[1] = gf100_ce_new, | |
70aa8670 | 1547 | .disp = gt215_disp_new, |
bd70563f | 1548 | .dma = gf100_dma_new, |
13de7f46 | 1549 | .fifo = gf100_fifo_new, |
c85ee6ca | 1550 | .gr = gf104_gr_new, |
53e60da4 BS |
1551 | .mspdec = gf100_mspdec_new, |
1552 | .msppp = gf100_msppp_new, | |
1553 | .msvld = gf100_msvld_new, | |
97070f23 | 1554 | .pm = gf100_pm_new, |
6f41c7c5 | 1555 | .sw = gf100_sw_new, |
6cf813fb BS |
1556 | }; |
1557 | ||
1558 | static const struct nvkm_device_chip | |
1559 | nvcf_chipset = { | |
1560 | .name = "GF116", | |
32932281 | 1561 | .bar = gf100_bar_new, |
46484438 | 1562 | .bios = nvkm_bios_new, |
bb23f9d7 | 1563 | .bus = gf100_bus_new, |
6625f55c | 1564 | .clk = gf100_clk_new, |
151abd44 | 1565 | .devinit = gf100_devinit_new, |
03c8952f | 1566 | .fb = gf100_fb_new, |
c5fcafa5 | 1567 | .fuse = gf100_fuse_new, |
2ea7249f | 1568 | .gpio = g94_gpio_new, |
49bd8da5 | 1569 | .i2c = g94_i2c_new, |
551d3417 | 1570 | .ibus = gf100_ibus_new, |
b71c0892 | 1571 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1572 | .imem = nv50_instmem_new, |
70bc7182 | 1573 | .ltc = gf100_ltc_new, |
2b700825 | 1574 | .mc = gf100_mc_new, |
c9582455 | 1575 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1576 | .mxm = nv50_mxm_new, |
bec4961e | 1577 | .pci = gf106_pci_new, |
e2ca4e7d | 1578 | .pmu = gf100_pmu_new, |
57113c01 | 1579 | .therm = gt215_therm_new, |
31649ecf | 1580 | .timer = nv41_timer_new, |
a3c950f2 | 1581 | .volt = gf100_volt_new, |
53e60da4 | 1582 | .ce[0] = gf100_ce_new, |
70aa8670 | 1583 | .disp = gt215_disp_new, |
bd70563f | 1584 | .dma = gf100_dma_new, |
13de7f46 | 1585 | .fifo = gf100_fifo_new, |
c85ee6ca | 1586 | .gr = gf104_gr_new, |
53e60da4 BS |
1587 | .mspdec = gf100_mspdec_new, |
1588 | .msppp = gf100_msppp_new, | |
1589 | .msvld = gf100_msvld_new, | |
97070f23 | 1590 | .pm = gf100_pm_new, |
6f41c7c5 | 1591 | .sw = gf100_sw_new, |
6cf813fb BS |
1592 | }; |
1593 | ||
1594 | static const struct nvkm_device_chip | |
1595 | nvd7_chipset = { | |
1596 | .name = "GF117", | |
32932281 | 1597 | .bar = gf100_bar_new, |
46484438 | 1598 | .bios = nvkm_bios_new, |
bb23f9d7 | 1599 | .bus = gf100_bus_new, |
6625f55c | 1600 | .clk = gf100_clk_new, |
151abd44 | 1601 | .devinit = gf100_devinit_new, |
03c8952f | 1602 | .fb = gf100_fb_new, |
c5fcafa5 | 1603 | .fuse = gf100_fuse_new, |
2ea7249f | 1604 | .gpio = gf119_gpio_new, |
49bd8da5 | 1605 | .i2c = gf117_i2c_new, |
b6afa265 | 1606 | .ibus = gf117_ibus_new, |
b71c0892 | 1607 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1608 | .imem = nv50_instmem_new, |
70bc7182 | 1609 | .ltc = gf100_ltc_new, |
2b700825 | 1610 | .mc = gf100_mc_new, |
c9582455 | 1611 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1612 | .mxm = nv50_mxm_new, |
bec4961e | 1613 | .pci = gf106_pci_new, |
57113c01 | 1614 | .therm = gf119_therm_new, |
31649ecf | 1615 | .timer = nv41_timer_new, |
a3c950f2 | 1616 | .volt = gf100_volt_new, |
53e60da4 | 1617 | .ce[0] = gf100_ce_new, |
70aa8670 | 1618 | .disp = gf119_disp_new, |
bd70563f | 1619 | .dma = gf119_dma_new, |
13de7f46 | 1620 | .fifo = gf100_fifo_new, |
c85ee6ca | 1621 | .gr = gf117_gr_new, |
53e60da4 BS |
1622 | .mspdec = gf100_mspdec_new, |
1623 | .msppp = gf100_msppp_new, | |
1624 | .msvld = gf100_msvld_new, | |
97070f23 | 1625 | .pm = gf117_pm_new, |
6f41c7c5 | 1626 | .sw = gf100_sw_new, |
6cf813fb BS |
1627 | }; |
1628 | ||
1629 | static const struct nvkm_device_chip | |
1630 | nvd9_chipset = { | |
1631 | .name = "GF119", | |
32932281 | 1632 | .bar = gf100_bar_new, |
46484438 | 1633 | .bios = nvkm_bios_new, |
bb23f9d7 | 1634 | .bus = gf100_bus_new, |
6625f55c | 1635 | .clk = gf100_clk_new, |
151abd44 | 1636 | .devinit = gf100_devinit_new, |
03c8952f | 1637 | .fb = gf100_fb_new, |
c5fcafa5 | 1638 | .fuse = gf100_fuse_new, |
2ea7249f | 1639 | .gpio = gf119_gpio_new, |
49bd8da5 | 1640 | .i2c = gf119_i2c_new, |
b6afa265 | 1641 | .ibus = gf117_ibus_new, |
b71c0892 | 1642 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1643 | .imem = nv50_instmem_new, |
70bc7182 | 1644 | .ltc = gf100_ltc_new, |
2b700825 | 1645 | .mc = gf100_mc_new, |
c9582455 | 1646 | .mmu = gf100_mmu_new, |
a4f7bd36 | 1647 | .mxm = nv50_mxm_new, |
bec4961e | 1648 | .pci = gf106_pci_new, |
e2ca4e7d | 1649 | .pmu = gf119_pmu_new, |
57113c01 | 1650 | .therm = gf119_therm_new, |
31649ecf | 1651 | .timer = nv41_timer_new, |
a3c950f2 | 1652 | .volt = gf100_volt_new, |
53e60da4 | 1653 | .ce[0] = gf100_ce_new, |
70aa8670 | 1654 | .disp = gf119_disp_new, |
bd70563f | 1655 | .dma = gf119_dma_new, |
13de7f46 | 1656 | .fifo = gf100_fifo_new, |
c85ee6ca | 1657 | .gr = gf119_gr_new, |
53e60da4 BS |
1658 | .mspdec = gf100_mspdec_new, |
1659 | .msppp = gf100_msppp_new, | |
1660 | .msvld = gf100_msvld_new, | |
97070f23 | 1661 | .pm = gf117_pm_new, |
6f41c7c5 | 1662 | .sw = gf100_sw_new, |
6cf813fb BS |
1663 | }; |
1664 | ||
1665 | static const struct nvkm_device_chip | |
1666 | nve4_chipset = { | |
1667 | .name = "GK104", | |
32932281 | 1668 | .bar = gf100_bar_new, |
46484438 | 1669 | .bios = nvkm_bios_new, |
bb23f9d7 | 1670 | .bus = gf100_bus_new, |
6625f55c | 1671 | .clk = gk104_clk_new, |
151abd44 | 1672 | .devinit = gf100_devinit_new, |
03c8952f | 1673 | .fb = gk104_fb_new, |
c5fcafa5 | 1674 | .fuse = gf100_fuse_new, |
2ea7249f | 1675 | .gpio = gk104_gpio_new, |
49bd8da5 | 1676 | .i2c = gk104_i2c_new, |
551d3417 | 1677 | .ibus = gk104_ibus_new, |
b71c0892 | 1678 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1679 | .imem = nv50_instmem_new, |
70bc7182 | 1680 | .ltc = gk104_ltc_new, |
33537d6f | 1681 | .mc = gk104_mc_new, |
db018585 | 1682 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1683 | .mxm = nv50_mxm_new, |
28c80605 | 1684 | .pci = gk104_pci_new, |
e2ca4e7d | 1685 | .pmu = gk104_pmu_new, |
b138eca6 | 1686 | .therm = gk104_therm_new, |
31649ecf | 1687 | .timer = nv41_timer_new, |
fb3e9c61 | 1688 | .top = gk104_top_new, |
1531dbbb | 1689 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1690 | .ce[0] = gk104_ce_new, |
1691 | .ce[1] = gk104_ce_new, | |
1692 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1693 | .disp = gk104_disp_new, |
bd70563f | 1694 | .dma = gf119_dma_new, |
13de7f46 | 1695 | .fifo = gk104_fifo_new, |
c85ee6ca | 1696 | .gr = gk104_gr_new, |
53e60da4 BS |
1697 | .mspdec = gk104_mspdec_new, |
1698 | .msppp = gf100_msppp_new, | |
1699 | .msvld = gk104_msvld_new, | |
97070f23 | 1700 | .pm = gk104_pm_new, |
6f41c7c5 | 1701 | .sw = gf100_sw_new, |
6cf813fb BS |
1702 | }; |
1703 | ||
1704 | static const struct nvkm_device_chip | |
1705 | nve6_chipset = { | |
1706 | .name = "GK106", | |
32932281 | 1707 | .bar = gf100_bar_new, |
46484438 | 1708 | .bios = nvkm_bios_new, |
bb23f9d7 | 1709 | .bus = gf100_bus_new, |
6625f55c | 1710 | .clk = gk104_clk_new, |
151abd44 | 1711 | .devinit = gf100_devinit_new, |
03c8952f | 1712 | .fb = gk104_fb_new, |
c5fcafa5 | 1713 | .fuse = gf100_fuse_new, |
2ea7249f | 1714 | .gpio = gk104_gpio_new, |
49bd8da5 | 1715 | .i2c = gk104_i2c_new, |
551d3417 | 1716 | .ibus = gk104_ibus_new, |
b71c0892 | 1717 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1718 | .imem = nv50_instmem_new, |
70bc7182 | 1719 | .ltc = gk104_ltc_new, |
33537d6f | 1720 | .mc = gk104_mc_new, |
db018585 | 1721 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1722 | .mxm = nv50_mxm_new, |
28c80605 | 1723 | .pci = gk104_pci_new, |
e2ca4e7d | 1724 | .pmu = gk104_pmu_new, |
b138eca6 | 1725 | .therm = gk104_therm_new, |
31649ecf | 1726 | .timer = nv41_timer_new, |
fb3e9c61 | 1727 | .top = gk104_top_new, |
1531dbbb | 1728 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1729 | .ce[0] = gk104_ce_new, |
1730 | .ce[1] = gk104_ce_new, | |
1731 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1732 | .disp = gk104_disp_new, |
bd70563f | 1733 | .dma = gf119_dma_new, |
13de7f46 | 1734 | .fifo = gk104_fifo_new, |
c85ee6ca | 1735 | .gr = gk104_gr_new, |
53e60da4 BS |
1736 | .mspdec = gk104_mspdec_new, |
1737 | .msppp = gf100_msppp_new, | |
1738 | .msvld = gk104_msvld_new, | |
97070f23 | 1739 | .pm = gk104_pm_new, |
6f41c7c5 | 1740 | .sw = gf100_sw_new, |
6cf813fb BS |
1741 | }; |
1742 | ||
1743 | static const struct nvkm_device_chip | |
1744 | nve7_chipset = { | |
1745 | .name = "GK107", | |
32932281 | 1746 | .bar = gf100_bar_new, |
46484438 | 1747 | .bios = nvkm_bios_new, |
bb23f9d7 | 1748 | .bus = gf100_bus_new, |
6625f55c | 1749 | .clk = gk104_clk_new, |
151abd44 | 1750 | .devinit = gf100_devinit_new, |
03c8952f | 1751 | .fb = gk104_fb_new, |
c5fcafa5 | 1752 | .fuse = gf100_fuse_new, |
2ea7249f | 1753 | .gpio = gk104_gpio_new, |
49bd8da5 | 1754 | .i2c = gk104_i2c_new, |
551d3417 | 1755 | .ibus = gk104_ibus_new, |
b71c0892 | 1756 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1757 | .imem = nv50_instmem_new, |
70bc7182 | 1758 | .ltc = gk104_ltc_new, |
33537d6f | 1759 | .mc = gk104_mc_new, |
db018585 | 1760 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1761 | .mxm = nv50_mxm_new, |
28c80605 | 1762 | .pci = gk104_pci_new, |
3c9aca31 | 1763 | .pmu = gk104_pmu_new, |
b138eca6 | 1764 | .therm = gk104_therm_new, |
31649ecf | 1765 | .timer = nv41_timer_new, |
fb3e9c61 | 1766 | .top = gk104_top_new, |
1531dbbb | 1767 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1768 | .ce[0] = gk104_ce_new, |
1769 | .ce[1] = gk104_ce_new, | |
1770 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1771 | .disp = gk104_disp_new, |
bd70563f | 1772 | .dma = gf119_dma_new, |
13de7f46 | 1773 | .fifo = gk104_fifo_new, |
c85ee6ca | 1774 | .gr = gk104_gr_new, |
53e60da4 BS |
1775 | .mspdec = gk104_mspdec_new, |
1776 | .msppp = gf100_msppp_new, | |
1777 | .msvld = gk104_msvld_new, | |
97070f23 | 1778 | .pm = gk104_pm_new, |
6f41c7c5 | 1779 | .sw = gf100_sw_new, |
6cf813fb BS |
1780 | }; |
1781 | ||
1782 | static const struct nvkm_device_chip | |
1783 | nvea_chipset = { | |
1784 | .name = "GK20A", | |
32932281 | 1785 | .bar = gk20a_bar_new, |
bb23f9d7 | 1786 | .bus = gf100_bus_new, |
6625f55c | 1787 | .clk = gk20a_clk_new, |
03c8952f | 1788 | .fb = gk20a_fb_new, |
c5fcafa5 | 1789 | .fuse = gf100_fuse_new, |
551d3417 | 1790 | .ibus = gk20a_ibus_new, |
b7a2bc18 | 1791 | .imem = gk20a_instmem_new, |
70bc7182 | 1792 | .ltc = gk104_ltc_new, |
54dcadd5 | 1793 | .mc = gk20a_mc_new, |
d1f6c8d2 | 1794 | .mmu = gk20a_mmu_new, |
e2ca4e7d | 1795 | .pmu = gk20a_pmu_new, |
31649ecf | 1796 | .timer = gk20a_timer_new, |
fb3e9c61 | 1797 | .top = gk104_top_new, |
437b2296 | 1798 | .volt = gk20a_volt_new, |
e5b31ca6 | 1799 | .ce[2] = gk104_ce_new, |
bd70563f | 1800 | .dma = gf119_dma_new, |
13de7f46 | 1801 | .fifo = gk20a_fifo_new, |
c85ee6ca | 1802 | .gr = gk20a_gr_new, |
97070f23 | 1803 | .pm = gk104_pm_new, |
6f41c7c5 | 1804 | .sw = gf100_sw_new, |
6cf813fb BS |
1805 | }; |
1806 | ||
1807 | static const struct nvkm_device_chip | |
1808 | nvf0_chipset = { | |
1809 | .name = "GK110", | |
32932281 | 1810 | .bar = gf100_bar_new, |
46484438 | 1811 | .bios = nvkm_bios_new, |
bb23f9d7 | 1812 | .bus = gf100_bus_new, |
6625f55c | 1813 | .clk = gk104_clk_new, |
151abd44 | 1814 | .devinit = gf100_devinit_new, |
7d094d29 | 1815 | .fb = gk110_fb_new, |
c5fcafa5 | 1816 | .fuse = gf100_fuse_new, |
2ea7249f | 1817 | .gpio = gk104_gpio_new, |
49bd8da5 | 1818 | .i2c = gk104_i2c_new, |
551d3417 | 1819 | .ibus = gk104_ibus_new, |
b71c0892 | 1820 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1821 | .imem = nv50_instmem_new, |
70bc7182 | 1822 | .ltc = gk104_ltc_new, |
33537d6f | 1823 | .mc = gk104_mc_new, |
db018585 | 1824 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1825 | .mxm = nv50_mxm_new, |
28c80605 | 1826 | .pci = gk104_pci_new, |
e2ca4e7d | 1827 | .pmu = gk110_pmu_new, |
b138eca6 | 1828 | .therm = gk104_therm_new, |
31649ecf | 1829 | .timer = nv41_timer_new, |
fb3e9c61 | 1830 | .top = gk104_top_new, |
1531dbbb | 1831 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1832 | .ce[0] = gk104_ce_new, |
1833 | .ce[1] = gk104_ce_new, | |
1834 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1835 | .disp = gk110_disp_new, |
bd70563f | 1836 | .dma = gf119_dma_new, |
63f8c9b7 | 1837 | .fifo = gk110_fifo_new, |
c85ee6ca | 1838 | .gr = gk110_gr_new, |
53e60da4 BS |
1839 | .mspdec = gk104_mspdec_new, |
1840 | .msppp = gf100_msppp_new, | |
1841 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1842 | .sw = gf100_sw_new, |
6cf813fb BS |
1843 | }; |
1844 | ||
1845 | static const struct nvkm_device_chip | |
1846 | nvf1_chipset = { | |
1847 | .name = "GK110B", | |
32932281 | 1848 | .bar = gf100_bar_new, |
46484438 | 1849 | .bios = nvkm_bios_new, |
bb23f9d7 | 1850 | .bus = gf100_bus_new, |
6625f55c | 1851 | .clk = gk104_clk_new, |
151abd44 | 1852 | .devinit = gf100_devinit_new, |
7d094d29 | 1853 | .fb = gk110_fb_new, |
c5fcafa5 | 1854 | .fuse = gf100_fuse_new, |
2ea7249f | 1855 | .gpio = gk104_gpio_new, |
5b3800a6 | 1856 | .i2c = gk104_i2c_new, |
551d3417 | 1857 | .ibus = gk104_ibus_new, |
b71c0892 | 1858 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1859 | .imem = nv50_instmem_new, |
70bc7182 | 1860 | .ltc = gk104_ltc_new, |
33537d6f | 1861 | .mc = gk104_mc_new, |
db018585 | 1862 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1863 | .mxm = nv50_mxm_new, |
28c80605 | 1864 | .pci = gk104_pci_new, |
e2ca4e7d | 1865 | .pmu = gk110_pmu_new, |
b138eca6 | 1866 | .therm = gk104_therm_new, |
31649ecf | 1867 | .timer = nv41_timer_new, |
fb3e9c61 | 1868 | .top = gk104_top_new, |
1531dbbb | 1869 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1870 | .ce[0] = gk104_ce_new, |
1871 | .ce[1] = gk104_ce_new, | |
1872 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1873 | .disp = gk110_disp_new, |
bd70563f | 1874 | .dma = gf119_dma_new, |
63f8c9b7 | 1875 | .fifo = gk110_fifo_new, |
c85ee6ca | 1876 | .gr = gk110b_gr_new, |
53e60da4 BS |
1877 | .mspdec = gk104_mspdec_new, |
1878 | .msppp = gf100_msppp_new, | |
1879 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1880 | .sw = gf100_sw_new, |
6cf813fb BS |
1881 | }; |
1882 | ||
1883 | static const struct nvkm_device_chip | |
1884 | nv106_chipset = { | |
1885 | .name = "GK208B", | |
32932281 | 1886 | .bar = gf100_bar_new, |
46484438 | 1887 | .bios = nvkm_bios_new, |
bb23f9d7 | 1888 | .bus = gf100_bus_new, |
6625f55c | 1889 | .clk = gk104_clk_new, |
151abd44 | 1890 | .devinit = gf100_devinit_new, |
7d094d29 | 1891 | .fb = gk110_fb_new, |
c5fcafa5 | 1892 | .fuse = gf100_fuse_new, |
2ea7249f | 1893 | .gpio = gk104_gpio_new, |
49bd8da5 | 1894 | .i2c = gk104_i2c_new, |
551d3417 | 1895 | .ibus = gk104_ibus_new, |
b71c0892 | 1896 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1897 | .imem = nv50_instmem_new, |
70bc7182 | 1898 | .ltc = gk104_ltc_new, |
54dcadd5 | 1899 | .mc = gk20a_mc_new, |
db018585 | 1900 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1901 | .mxm = nv50_mxm_new, |
28c80605 | 1902 | .pci = gk104_pci_new, |
e2ca4e7d | 1903 | .pmu = gk208_pmu_new, |
b138eca6 | 1904 | .therm = gk104_therm_new, |
31649ecf | 1905 | .timer = nv41_timer_new, |
fb3e9c61 | 1906 | .top = gk104_top_new, |
1531dbbb | 1907 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1908 | .ce[0] = gk104_ce_new, |
1909 | .ce[1] = gk104_ce_new, | |
1910 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1911 | .disp = gk110_disp_new, |
bd70563f | 1912 | .dma = gf119_dma_new, |
13de7f46 | 1913 | .fifo = gk208_fifo_new, |
c85ee6ca | 1914 | .gr = gk208_gr_new, |
53e60da4 BS |
1915 | .mspdec = gk104_mspdec_new, |
1916 | .msppp = gf100_msppp_new, | |
1917 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1918 | .sw = gf100_sw_new, |
6cf813fb BS |
1919 | }; |
1920 | ||
1921 | static const struct nvkm_device_chip | |
1922 | nv108_chipset = { | |
1923 | .name = "GK208", | |
32932281 | 1924 | .bar = gf100_bar_new, |
46484438 | 1925 | .bios = nvkm_bios_new, |
bb23f9d7 | 1926 | .bus = gf100_bus_new, |
6625f55c | 1927 | .clk = gk104_clk_new, |
151abd44 | 1928 | .devinit = gf100_devinit_new, |
7d094d29 | 1929 | .fb = gk110_fb_new, |
c5fcafa5 | 1930 | .fuse = gf100_fuse_new, |
2ea7249f | 1931 | .gpio = gk104_gpio_new, |
49bd8da5 | 1932 | .i2c = gk104_i2c_new, |
551d3417 | 1933 | .ibus = gk104_ibus_new, |
b71c0892 | 1934 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1935 | .imem = nv50_instmem_new, |
70bc7182 | 1936 | .ltc = gk104_ltc_new, |
54dcadd5 | 1937 | .mc = gk20a_mc_new, |
db018585 | 1938 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1939 | .mxm = nv50_mxm_new, |
28c80605 | 1940 | .pci = gk104_pci_new, |
e2ca4e7d | 1941 | .pmu = gk208_pmu_new, |
b138eca6 | 1942 | .therm = gk104_therm_new, |
31649ecf | 1943 | .timer = nv41_timer_new, |
fb3e9c61 | 1944 | .top = gk104_top_new, |
1531dbbb | 1945 | .volt = gk104_volt_new, |
e5b31ca6 BS |
1946 | .ce[0] = gk104_ce_new, |
1947 | .ce[1] = gk104_ce_new, | |
1948 | .ce[2] = gk104_ce_new, | |
70aa8670 | 1949 | .disp = gk110_disp_new, |
bd70563f | 1950 | .dma = gf119_dma_new, |
13de7f46 | 1951 | .fifo = gk208_fifo_new, |
c85ee6ca | 1952 | .gr = gk208_gr_new, |
53e60da4 BS |
1953 | .mspdec = gk104_mspdec_new, |
1954 | .msppp = gf100_msppp_new, | |
1955 | .msvld = gk104_msvld_new, | |
6f41c7c5 | 1956 | .sw = gf100_sw_new, |
6cf813fb BS |
1957 | }; |
1958 | ||
1959 | static const struct nvkm_device_chip | |
1960 | nv117_chipset = { | |
1961 | .name = "GM107", | |
70433b90 | 1962 | .bar = gm107_bar_new, |
46484438 | 1963 | .bios = nvkm_bios_new, |
bb23f9d7 | 1964 | .bus = gf100_bus_new, |
6625f55c | 1965 | .clk = gk104_clk_new, |
151abd44 | 1966 | .devinit = gm107_devinit_new, |
03c8952f | 1967 | .fb = gm107_fb_new, |
c5fcafa5 | 1968 | .fuse = gm107_fuse_new, |
2ea7249f | 1969 | .gpio = gk104_gpio_new, |
5b3800a6 | 1970 | .i2c = gk104_i2c_new, |
551d3417 | 1971 | .ibus = gk104_ibus_new, |
b71c0892 | 1972 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 1973 | .imem = nv50_instmem_new, |
70bc7182 | 1974 | .ltc = gm107_ltc_new, |
54dcadd5 | 1975 | .mc = gk20a_mc_new, |
db018585 | 1976 | .mmu = gk104_mmu_new, |
a4f7bd36 | 1977 | .mxm = nv50_mxm_new, |
28c80605 | 1978 | .pci = gk104_pci_new, |
e2ca4e7d | 1979 | .pmu = gm107_pmu_new, |
57113c01 | 1980 | .therm = gm107_therm_new, |
31649ecf | 1981 | .timer = gk20a_timer_new, |
fb3e9c61 | 1982 | .top = gk104_top_new, |
dc47700f | 1983 | .volt = gk104_volt_new, |
253a03f0 BS |
1984 | .ce[0] = gm107_ce_new, |
1985 | .ce[2] = gm107_ce_new, | |
70aa8670 | 1986 | .disp = gm107_disp_new, |
bd70563f | 1987 | .dma = gf119_dma_new, |
7c4f87c9 | 1988 | .fifo = gm107_fifo_new, |
c85ee6ca | 1989 | .gr = gm107_gr_new, |
6f41c7c5 | 1990 | .sw = gf100_sw_new, |
6cf813fb BS |
1991 | }; |
1992 | ||
f9e20294 BS |
1993 | static const struct nvkm_device_chip |
1994 | nv118_chipset = { | |
1995 | .name = "GM108", | |
70433b90 | 1996 | .bar = gm107_bar_new, |
f9e20294 BS |
1997 | .bios = nvkm_bios_new, |
1998 | .bus = gf100_bus_new, | |
1999 | .clk = gk104_clk_new, | |
2000 | .devinit = gm107_devinit_new, | |
2001 | .fb = gm107_fb_new, | |
2002 | .fuse = gm107_fuse_new, | |
2003 | .gpio = gk104_gpio_new, | |
5b3800a6 | 2004 | .i2c = gk104_i2c_new, |
f9e20294 BS |
2005 | .ibus = gk104_ibus_new, |
2006 | .iccsense = gf100_iccsense_new, | |
2007 | .imem = nv50_instmem_new, | |
2008 | .ltc = gm107_ltc_new, | |
2009 | .mc = gk20a_mc_new, | |
db018585 | 2010 | .mmu = gk104_mmu_new, |
f9e20294 BS |
2011 | .mxm = nv50_mxm_new, |
2012 | .pci = gk104_pci_new, | |
2013 | .pmu = gm107_pmu_new, | |
2014 | .therm = gm107_therm_new, | |
2015 | .timer = gk20a_timer_new, | |
2016 | .top = gk104_top_new, | |
2017 | .volt = gk104_volt_new, | |
2018 | .ce[0] = gm107_ce_new, | |
2019 | .ce[2] = gm107_ce_new, | |
2020 | .disp = gm107_disp_new, | |
2021 | .dma = gf119_dma_new, | |
2022 | .fifo = gm107_fifo_new, | |
2023 | .gr = gm107_gr_new, | |
2024 | .sw = gf100_sw_new, | |
2025 | }; | |
2026 | ||
2ed95a4c BS |
2027 | static const struct nvkm_device_chip |
2028 | nv120_chipset = { | |
2029 | .name = "GM200", | |
70433b90 | 2030 | .bar = gm107_bar_new, |
2ed95a4c BS |
2031 | .bios = nvkm_bios_new, |
2032 | .bus = gf100_bus_new, | |
db1eb528 | 2033 | .devinit = gm200_devinit_new, |
e976278a | 2034 | .fb = gm200_fb_new, |
2ed95a4c BS |
2035 | .fuse = gm107_fuse_new, |
2036 | .gpio = gk104_gpio_new, | |
db1eb528 BS |
2037 | .i2c = gm200_i2c_new, |
2038 | .ibus = gm200_ibus_new, | |
b71c0892 | 2039 | .iccsense = gf100_iccsense_new, |
2ed95a4c | 2040 | .imem = nv50_instmem_new, |
db1eb528 | 2041 | .ltc = gm200_ltc_new, |
2ed95a4c | 2042 | .mc = gk20a_mc_new, |
e1e33c79 | 2043 | .mmu = gm200_mmu_new, |
2ed95a4c BS |
2044 | .mxm = nv50_mxm_new, |
2045 | .pci = gk104_pci_new, | |
2046 | .pmu = gm107_pmu_new, | |
9d60b9c9 | 2047 | .therm = gm200_therm_new, |
9cc45521 | 2048 | .secboot = gm200_secboot_new, |
2ed95a4c | 2049 | .timer = gk20a_timer_new, |
fb3e9c61 | 2050 | .top = gk104_top_new, |
2ed95a4c | 2051 | .volt = gk104_volt_new, |
db1eb528 BS |
2052 | .ce[0] = gm200_ce_new, |
2053 | .ce[1] = gm200_ce_new, | |
2054 | .ce[2] = gm200_ce_new, | |
2055 | .disp = gm200_disp_new, | |
2ed95a4c | 2056 | .dma = gf119_dma_new, |
db1eb528 | 2057 | .fifo = gm200_fifo_new, |
96fc422c | 2058 | .gr = gm200_gr_new, |
2ed95a4c BS |
2059 | .sw = gf100_sw_new, |
2060 | }; | |
2061 | ||
6cf813fb BS |
2062 | static const struct nvkm_device_chip |
2063 | nv124_chipset = { | |
2064 | .name = "GM204", | |
70433b90 | 2065 | .bar = gm107_bar_new, |
46484438 | 2066 | .bios = nvkm_bios_new, |
bb23f9d7 | 2067 | .bus = gf100_bus_new, |
db1eb528 | 2068 | .devinit = gm200_devinit_new, |
e976278a | 2069 | .fb = gm200_fb_new, |
c5fcafa5 | 2070 | .fuse = gm107_fuse_new, |
2ea7249f | 2071 | .gpio = gk104_gpio_new, |
db1eb528 BS |
2072 | .i2c = gm200_i2c_new, |
2073 | .ibus = gm200_ibus_new, | |
b71c0892 | 2074 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 2075 | .imem = nv50_instmem_new, |
db1eb528 | 2076 | .ltc = gm200_ltc_new, |
54dcadd5 | 2077 | .mc = gk20a_mc_new, |
e1e33c79 | 2078 | .mmu = gm200_mmu_new, |
a4f7bd36 | 2079 | .mxm = nv50_mxm_new, |
28c80605 | 2080 | .pci = gk104_pci_new, |
e2ca4e7d | 2081 | .pmu = gm107_pmu_new, |
9d60b9c9 | 2082 | .therm = gm200_therm_new, |
9cc45521 | 2083 | .secboot = gm200_secboot_new, |
31649ecf | 2084 | .timer = gk20a_timer_new, |
fb3e9c61 | 2085 | .top = gk104_top_new, |
24580d1c | 2086 | .volt = gk104_volt_new, |
db1eb528 BS |
2087 | .ce[0] = gm200_ce_new, |
2088 | .ce[1] = gm200_ce_new, | |
2089 | .ce[2] = gm200_ce_new, | |
2090 | .disp = gm200_disp_new, | |
bd70563f | 2091 | .dma = gf119_dma_new, |
db1eb528 | 2092 | .fifo = gm200_fifo_new, |
9ec28052 | 2093 | .gr = gm200_gr_new, |
6f41c7c5 | 2094 | .sw = gf100_sw_new, |
6cf813fb BS |
2095 | }; |
2096 | ||
2097 | static const struct nvkm_device_chip | |
2098 | nv126_chipset = { | |
2099 | .name = "GM206", | |
70433b90 | 2100 | .bar = gm107_bar_new, |
46484438 | 2101 | .bios = nvkm_bios_new, |
bb23f9d7 | 2102 | .bus = gf100_bus_new, |
db1eb528 | 2103 | .devinit = gm200_devinit_new, |
e976278a | 2104 | .fb = gm200_fb_new, |
c5fcafa5 | 2105 | .fuse = gm107_fuse_new, |
2ea7249f | 2106 | .gpio = gk104_gpio_new, |
db1eb528 BS |
2107 | .i2c = gm200_i2c_new, |
2108 | .ibus = gm200_ibus_new, | |
b71c0892 | 2109 | .iccsense = gf100_iccsense_new, |
b7a2bc18 | 2110 | .imem = nv50_instmem_new, |
db1eb528 | 2111 | .ltc = gm200_ltc_new, |
54dcadd5 | 2112 | .mc = gk20a_mc_new, |
e1e33c79 | 2113 | .mmu = gm200_mmu_new, |
a4f7bd36 | 2114 | .mxm = nv50_mxm_new, |
28c80605 | 2115 | .pci = gk104_pci_new, |
e2ca4e7d | 2116 | .pmu = gm107_pmu_new, |
9d60b9c9 | 2117 | .therm = gm200_therm_new, |
9cc45521 | 2118 | .secboot = gm200_secboot_new, |
31649ecf | 2119 | .timer = gk20a_timer_new, |
fb3e9c61 | 2120 | .top = gk104_top_new, |
24580d1c | 2121 | .volt = gk104_volt_new, |
db1eb528 BS |
2122 | .ce[0] = gm200_ce_new, |
2123 | .ce[1] = gm200_ce_new, | |
2124 | .ce[2] = gm200_ce_new, | |
2125 | .disp = gm200_disp_new, | |
bd70563f | 2126 | .dma = gf119_dma_new, |
db1eb528 | 2127 | .fifo = gm200_fifo_new, |
7d31cb7c | 2128 | .gr = gm200_gr_new, |
6f41c7c5 | 2129 | .sw = gf100_sw_new, |
6cf813fb BS |
2130 | }; |
2131 | ||
2132 | static const struct nvkm_device_chip | |
2133 | nv12b_chipset = { | |
2134 | .name = "GM20B", | |
70433b90 | 2135 | .bar = gm20b_bar_new, |
bb23f9d7 | 2136 | .bus = gf100_bus_new, |
52829d4f | 2137 | .clk = gm20b_clk_new, |
770b06e8 | 2138 | .fb = gm20b_fb_new, |
c5fcafa5 | 2139 | .fuse = gm107_fuse_new, |
551d3417 | 2140 | .ibus = gk20a_ibus_new, |
b7a2bc18 | 2141 | .imem = gk20a_instmem_new, |
db1eb528 | 2142 | .ltc = gm200_ltc_new, |
54dcadd5 | 2143 | .mc = gk20a_mc_new, |
cedc4d57 | 2144 | .mmu = gm20b_mmu_new, |
b1c39d80 | 2145 | .pmu = gm20b_pmu_new, |
923f1bd2 | 2146 | .secboot = gm20b_secboot_new, |
31649ecf | 2147 | .timer = gk20a_timer_new, |
fb3e9c61 | 2148 | .top = gk104_top_new, |
db1eb528 | 2149 | .ce[2] = gm200_ce_new, |
71757abf | 2150 | .volt = gm20b_volt_new, |
bd70563f | 2151 | .dma = gf119_dma_new, |
13de7f46 | 2152 | .fifo = gm20b_fifo_new, |
c85ee6ca | 2153 | .gr = gm20b_gr_new, |
6f41c7c5 | 2154 | .sw = gf100_sw_new, |
6cf813fb BS |
2155 | }; |
2156 | ||
7f53abdb BS |
2157 | static const struct nvkm_device_chip |
2158 | nv130_chipset = { | |
2159 | .name = "GP100", | |
70433b90 | 2160 | .bar = gm107_bar_new, |
7481d055 | 2161 | .bios = nvkm_bios_new, |
0e98bd34 | 2162 | .bus = gf100_bus_new, |
c7b511ba | 2163 | .devinit = gm200_devinit_new, |
d0e9351e | 2164 | .fault = gp100_fault_new, |
7ff51f82 | 2165 | .fb = gp100_fb_new, |
24b8ca86 | 2166 | .fuse = gm107_fuse_new, |
a4a58832 | 2167 | .gpio = gk104_gpio_new, |
51554014 | 2168 | .i2c = gm200_i2c_new, |
2a295e95 | 2169 | .ibus = gm200_ibus_new, |
0cbe26f0 | 2170 | .imem = nv50_instmem_new, |
a96def39 | 2171 | .ltc = gp100_ltc_new, |
be61c54c | 2172 | .mc = gp100_mc_new, |
b86a4587 | 2173 | .mmu = gp100_mmu_new, |
d3265637 | 2174 | .therm = gp100_therm_new, |
a4a4cf1b | 2175 | .secboot = gm200_secboot_new, |
45aa4d07 | 2176 | .pci = gp100_pci_new, |
41c7be69 | 2177 | .pmu = gp100_pmu_new, |
4eeb039b | 2178 | .timer = gk20a_timer_new, |
51012a39 | 2179 | .top = gk104_top_new, |
8e7e1586 BS |
2180 | .ce[0] = gp100_ce_new, |
2181 | .ce[1] = gp100_ce_new, | |
2182 | .ce[2] = gp100_ce_new, | |
2183 | .ce[3] = gp100_ce_new, | |
2184 | .ce[4] = gp100_ce_new, | |
2185 | .ce[5] = gp100_ce_new, | |
cd0f407c | 2186 | .dma = gf119_dma_new, |
f9d5cbb3 | 2187 | .disp = gp100_disp_new, |
e8ff9794 | 2188 | .fifo = gp100_fifo_new, |
52fa0866 | 2189 | .gr = gp100_gr_new, |
ac24b4df | 2190 | .sw = gf100_sw_new, |
7f53abdb BS |
2191 | }; |
2192 | ||
17ff521d BS |
2193 | static const struct nvkm_device_chip |
2194 | nv132_chipset = { | |
2195 | .name = "GP102", | |
70433b90 | 2196 | .bar = gm107_bar_new, |
17ff521d BS |
2197 | .bios = nvkm_bios_new, |
2198 | .bus = gf100_bus_new, | |
2199 | .devinit = gm200_devinit_new, | |
d0e9351e | 2200 | .fault = gp100_fault_new, |
eeea423c | 2201 | .fb = gp102_fb_new, |
17ff521d BS |
2202 | .fuse = gm107_fuse_new, |
2203 | .gpio = gk104_gpio_new, | |
2204 | .i2c = gm200_i2c_new, | |
2205 | .ibus = gm200_ibus_new, | |
2206 | .imem = nv50_instmem_new, | |
4b2c71ed | 2207 | .ltc = gp102_ltc_new, |
17ff521d | 2208 | .mc = gp100_mc_new, |
b86a4587 | 2209 | .mmu = gp100_mmu_new, |
d3265637 | 2210 | .therm = gp100_therm_new, |
36510add | 2211 | .secboot = gp102_secboot_new, |
17ff521d | 2212 | .pci = gp100_pci_new, |
d91ccec6 | 2213 | .pmu = gp102_pmu_new, |
17ff521d BS |
2214 | .timer = gk20a_timer_new, |
2215 | .top = gk104_top_new, | |
a4fa851c BS |
2216 | .ce[0] = gp102_ce_new, |
2217 | .ce[1] = gp102_ce_new, | |
2218 | .ce[2] = gp102_ce_new, | |
2219 | .ce[3] = gp102_ce_new, | |
ed828666 | 2220 | .disp = gp102_disp_new, |
17ff521d BS |
2221 | .dma = gf119_dma_new, |
2222 | .fifo = gp100_fifo_new, | |
36510add | 2223 | .gr = gp102_gr_new, |
b2c4ef70 BS |
2224 | .nvdec = gp102_nvdec_new, |
2225 | .sec2 = gp102_sec2_new, | |
36510add | 2226 | .sw = gf100_sw_new, |
17ff521d BS |
2227 | }; |
2228 | ||
cfb083f6 BS |
2229 | static const struct nvkm_device_chip |
2230 | nv134_chipset = { | |
2231 | .name = "GP104", | |
70433b90 | 2232 | .bar = gm107_bar_new, |
38849205 | 2233 | .bios = nvkm_bios_new, |
42d7a65e | 2234 | .bus = gf100_bus_new, |
047506ca | 2235 | .devinit = gm200_devinit_new, |
d0e9351e | 2236 | .fault = gp100_fault_new, |
eeea423c | 2237 | .fb = gp102_fb_new, |
7d007dd7 | 2238 | .fuse = gm107_fuse_new, |
14ae020d | 2239 | .gpio = gk104_gpio_new, |
13a66d2f | 2240 | .i2c = gm200_i2c_new, |
8c80bc6c | 2241 | .ibus = gm200_ibus_new, |
4fdbdfa8 | 2242 | .imem = nv50_instmem_new, |
4b2c71ed | 2243 | .ltc = gp102_ltc_new, |
9179b8ec | 2244 | .mc = gp100_mc_new, |
b86a4587 | 2245 | .mmu = gp100_mmu_new, |
d3265637 | 2246 | .therm = gp100_therm_new, |
36510add | 2247 | .secboot = gp102_secboot_new, |
b3446c5a | 2248 | .pci = gp100_pci_new, |
d91ccec6 | 2249 | .pmu = gp102_pmu_new, |
5f62ee6d | 2250 | .timer = gk20a_timer_new, |
445b9c21 | 2251 | .top = gk104_top_new, |
a4fa851c BS |
2252 | .ce[0] = gp102_ce_new, |
2253 | .ce[1] = gp102_ce_new, | |
2254 | .ce[2] = gp102_ce_new, | |
2255 | .ce[3] = gp102_ce_new, | |
ed828666 | 2256 | .disp = gp102_disp_new, |
15cec92f | 2257 | .dma = gf119_dma_new, |
ba3b712e | 2258 | .fifo = gp100_fifo_new, |
a5537f98 | 2259 | .gr = gp104_gr_new, |
b2c4ef70 BS |
2260 | .nvdec = gp102_nvdec_new, |
2261 | .sec2 = gp102_sec2_new, | |
36510add | 2262 | .sw = gf100_sw_new, |
cfb083f6 BS |
2263 | }; |
2264 | ||
1fe487d7 BS |
2265 | static const struct nvkm_device_chip |
2266 | nv136_chipset = { | |
2267 | .name = "GP106", | |
70433b90 | 2268 | .bar = gm107_bar_new, |
1fe487d7 BS |
2269 | .bios = nvkm_bios_new, |
2270 | .bus = gf100_bus_new, | |
2271 | .devinit = gm200_devinit_new, | |
d0e9351e | 2272 | .fault = gp100_fault_new, |
1fe487d7 BS |
2273 | .fb = gp102_fb_new, |
2274 | .fuse = gm107_fuse_new, | |
2275 | .gpio = gk104_gpio_new, | |
2276 | .i2c = gm200_i2c_new, | |
2277 | .ibus = gm200_ibus_new, | |
2278 | .imem = nv50_instmem_new, | |
4b2c71ed | 2279 | .ltc = gp102_ltc_new, |
1fe487d7 | 2280 | .mc = gp100_mc_new, |
b86a4587 | 2281 | .mmu = gp100_mmu_new, |
d3265637 | 2282 | .therm = gp100_therm_new, |
36510add | 2283 | .secboot = gp102_secboot_new, |
1fe487d7 BS |
2284 | .pci = gp100_pci_new, |
2285 | .pmu = gp102_pmu_new, | |
2286 | .timer = gk20a_timer_new, | |
2287 | .top = gk104_top_new, | |
2288 | .ce[0] = gp102_ce_new, | |
2289 | .ce[1] = gp102_ce_new, | |
2290 | .ce[2] = gp102_ce_new, | |
2291 | .ce[3] = gp102_ce_new, | |
2292 | .disp = gp102_disp_new, | |
2293 | .dma = gf119_dma_new, | |
2294 | .fifo = gp100_fifo_new, | |
a5537f98 | 2295 | .gr = gp104_gr_new, |
b2c4ef70 BS |
2296 | .nvdec = gp102_nvdec_new, |
2297 | .sec2 = gp102_sec2_new, | |
36510add | 2298 | .sw = gf100_sw_new, |
1fe487d7 BS |
2299 | }; |
2300 | ||
2ebd42bc BS |
2301 | static const struct nvkm_device_chip |
2302 | nv137_chipset = { | |
2303 | .name = "GP107", | |
70433b90 | 2304 | .bar = gm107_bar_new, |
2ebd42bc BS |
2305 | .bios = nvkm_bios_new, |
2306 | .bus = gf100_bus_new, | |
2307 | .devinit = gm200_devinit_new, | |
d0e9351e | 2308 | .fault = gp100_fault_new, |
2ebd42bc BS |
2309 | .fb = gp102_fb_new, |
2310 | .fuse = gm107_fuse_new, | |
2311 | .gpio = gk104_gpio_new, | |
2312 | .i2c = gm200_i2c_new, | |
2313 | .ibus = gm200_ibus_new, | |
2314 | .imem = nv50_instmem_new, | |
4b2c71ed | 2315 | .ltc = gp102_ltc_new, |
2ebd42bc | 2316 | .mc = gp100_mc_new, |
b86a4587 | 2317 | .mmu = gp100_mmu_new, |
d3265637 | 2318 | .therm = gp100_therm_new, |
b2c4ef70 | 2319 | .secboot = gp102_secboot_new, |
2ebd42bc BS |
2320 | .pci = gp100_pci_new, |
2321 | .pmu = gp102_pmu_new, | |
2322 | .timer = gk20a_timer_new, | |
2323 | .top = gk104_top_new, | |
2324 | .ce[0] = gp102_ce_new, | |
2325 | .ce[1] = gp102_ce_new, | |
2326 | .ce[2] = gp102_ce_new, | |
2327 | .ce[3] = gp102_ce_new, | |
2328 | .disp = gp102_disp_new, | |
2329 | .dma = gf119_dma_new, | |
2330 | .fifo = gp100_fifo_new, | |
b2c4ef70 BS |
2331 | .gr = gp107_gr_new, |
2332 | .nvdec = gp102_nvdec_new, | |
2333 | .sec2 = gp102_sec2_new, | |
2334 | .sw = gf100_sw_new, | |
2ebd42bc BS |
2335 | }; |
2336 | ||
2659b4ce IM |
2337 | static const struct nvkm_device_chip |
2338 | nv138_chipset = { | |
2339 | .name = "GP108", | |
70433b90 | 2340 | .bar = gm107_bar_new, |
2659b4ce IM |
2341 | .bios = nvkm_bios_new, |
2342 | .bus = gf100_bus_new, | |
2343 | .devinit = gm200_devinit_new, | |
d0e9351e | 2344 | .fault = gp100_fault_new, |
2659b4ce IM |
2345 | .fb = gp102_fb_new, |
2346 | .fuse = gm107_fuse_new, | |
2347 | .gpio = gk104_gpio_new, | |
2348 | .i2c = gm200_i2c_new, | |
2349 | .ibus = gm200_ibus_new, | |
2350 | .imem = nv50_instmem_new, | |
4b2c71ed | 2351 | .ltc = gp102_ltc_new, |
2659b4ce | 2352 | .mc = gp100_mc_new, |
b86a4587 | 2353 | .mmu = gp100_mmu_new, |
d3265637 | 2354 | .therm = gp100_therm_new, |
2c5ac5ba | 2355 | .secboot = gp108_secboot_new, |
2659b4ce IM |
2356 | .pci = gp100_pci_new, |
2357 | .pmu = gp102_pmu_new, | |
2358 | .timer = gk20a_timer_new, | |
2359 | .top = gk104_top_new, | |
2360 | .ce[0] = gp102_ce_new, | |
2361 | .ce[1] = gp102_ce_new, | |
2362 | .ce[2] = gp102_ce_new, | |
2363 | .ce[3] = gp102_ce_new, | |
2364 | .disp = gp102_disp_new, | |
2365 | .dma = gf119_dma_new, | |
2366 | .fifo = gp100_fifo_new, | |
2c5ac5ba BS |
2367 | .gr = gp107_gr_new, |
2368 | .nvdec = gp102_nvdec_new, | |
2369 | .sec2 = gp102_sec2_new, | |
2370 | .sw = gf100_sw_new, | |
2659b4ce IM |
2371 | }; |
2372 | ||
fa1dbc49 AC |
2373 | static const struct nvkm_device_chip |
2374 | nv13b_chipset = { | |
2375 | .name = "GP10B", | |
70433b90 | 2376 | .bar = gm20b_bar_new, |
fa1dbc49 | 2377 | .bus = gf100_bus_new, |
d0e9351e | 2378 | .fault = gp100_fault_new, |
fa1dbc49 AC |
2379 | .fb = gp10b_fb_new, |
2380 | .fuse = gm107_fuse_new, | |
2381 | .ibus = gp10b_ibus_new, | |
2382 | .imem = gk20a_instmem_new, | |
4b2c71ed | 2383 | .ltc = gp102_ltc_new, |
fa1dbc49 | 2384 | .mc = gp10b_mc_new, |
6cb0f2a3 | 2385 | .mmu = gp10b_mmu_new, |
fa1dbc49 AC |
2386 | .secboot = gp10b_secboot_new, |
2387 | .pmu = gm20b_pmu_new, | |
2388 | .timer = gk20a_timer_new, | |
2389 | .top = gk104_top_new, | |
2390 | .ce[2] = gp102_ce_new, | |
2391 | .dma = gf119_dma_new, | |
2392 | .fifo = gp10b_fifo_new, | |
2393 | .gr = gp10b_gr_new, | |
2394 | .sw = gf100_sw_new, | |
2395 | }; | |
2396 | ||
c1f856bb BS |
2397 | static const struct nvkm_device_chip |
2398 | nv140_chipset = { | |
2399 | .name = "GV100", | |
2400 | }; | |
2401 | ||
79ca2770 | 2402 | static int |
9719047b BS |
2403 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, |
2404 | struct nvkm_notify *notify) | |
79ca2770 BS |
2405 | { |
2406 | if (!WARN_ON(size != 0)) { | |
2407 | notify->size = 0; | |
2408 | notify->types = 1; | |
2409 | notify->index = 0; | |
2410 | return 0; | |
2411 | } | |
2412 | return -EINVAL; | |
2413 | } | |
2414 | ||
2415 | static const struct nvkm_event_func | |
9719047b BS |
2416 | nvkm_device_event_func = { |
2417 | .ctor = nvkm_device_event_ctor, | |
79ca2770 BS |
2418 | }; |
2419 | ||
6cf813fb BS |
2420 | struct nvkm_subdev * |
2421 | nvkm_device_subdev(struct nvkm_device *device, int index) | |
2422 | { | |
2423 | struct nvkm_engine *engine; | |
2424 | ||
2425 | if (device->disable_mask & (1ULL << index)) | |
2426 | return NULL; | |
2427 | ||
2428 | switch (index) { | |
68f3f702 | 2429 | #define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break |
dc06e366 MP |
2430 | _(BAR , device->bar , &device->bar->subdev); |
2431 | _(VBIOS , device->bios , &device->bios->subdev); | |
2432 | _(BUS , device->bus , &device->bus->subdev); | |
2433 | _(CLK , device->clk , &device->clk->subdev); | |
2434 | _(DEVINIT , device->devinit , &device->devinit->subdev); | |
1ce46689 | 2435 | _(FAULT , device->fault , &device->fault->subdev); |
dc06e366 MP |
2436 | _(FB , device->fb , &device->fb->subdev); |
2437 | _(FUSE , device->fuse , &device->fuse->subdev); | |
2438 | _(GPIO , device->gpio , &device->gpio->subdev); | |
2439 | _(I2C , device->i2c , &device->i2c->subdev); | |
2440 | _(IBUS , device->ibus , device->ibus); | |
2441 | _(ICCSENSE, device->iccsense, &device->iccsense->subdev); | |
2442 | _(INSTMEM , device->imem , &device->imem->subdev); | |
2443 | _(LTC , device->ltc , &device->ltc->subdev); | |
2444 | _(MC , device->mc , &device->mc->subdev); | |
2445 | _(MMU , device->mmu , &device->mmu->subdev); | |
2446 | _(MXM , device->mxm , device->mxm); | |
2447 | _(PCI , device->pci , &device->pci->subdev); | |
2448 | _(PMU , device->pmu , &device->pmu->subdev); | |
2449 | _(SECBOOT , device->secboot , &device->secboot->subdev); | |
2450 | _(THERM , device->therm , &device->therm->subdev); | |
2451 | _(TIMER , device->timer , &device->timer->subdev); | |
eaebfcc3 | 2452 | _(TOP , device->top , &device->top->subdev); |
dc06e366 | 2453 | _(VOLT , device->volt , &device->volt->subdev); |
6cf813fb BS |
2454 | #undef _ |
2455 | default: | |
2456 | engine = nvkm_device_engine(device, index); | |
2457 | if (engine) | |
2458 | return &engine->subdev; | |
2459 | break; | |
2460 | } | |
2461 | return NULL; | |
2462 | } | |
2463 | ||
2464 | struct nvkm_engine * | |
2465 | nvkm_device_engine(struct nvkm_device *device, int index) | |
2466 | { | |
2467 | if (device->disable_mask & (1ULL << index)) | |
2468 | return NULL; | |
2469 | ||
2470 | switch (index) { | |
68f3f702 | 2471 | #define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break |
294af04b BS |
2472 | _(BSP , device->bsp , device->bsp); |
2473 | _(CE0 , device->ce[0] , device->ce[0]); | |
2474 | _(CE1 , device->ce[1] , device->ce[1]); | |
2475 | _(CE2 , device->ce[2] , device->ce[2]); | |
34bf50cd BS |
2476 | _(CE3 , device->ce[3] , device->ce[3]); |
2477 | _(CE4 , device->ce[4] , device->ce[4]); | |
2478 | _(CE5 , device->ce[5] , device->ce[5]); | |
890c85f3 BS |
2479 | _(CE6 , device->ce[6] , device->ce[6]); |
2480 | _(CE7 , device->ce[7] , device->ce[7]); | |
2481 | _(CE8 , device->ce[8] , device->ce[8]); | |
294af04b BS |
2482 | _(CIPHER , device->cipher , device->cipher); |
2483 | _(DISP , device->disp , &device->disp->engine); | |
2484 | _(DMAOBJ , device->dma , &device->dma->engine); | |
2485 | _(FIFO , device->fifo , &device->fifo->engine); | |
2486 | _(GR , device->gr , &device->gr->engine); | |
2487 | _(IFB , device->ifb , device->ifb); | |
2488 | _(ME , device->me , device->me); | |
2489 | _(MPEG , device->mpeg , device->mpeg); | |
2490 | _(MSENC , device->msenc , device->msenc); | |
2491 | _(MSPDEC , device->mspdec , device->mspdec); | |
2492 | _(MSPPP , device->msppp , device->msppp); | |
2493 | _(MSVLD , device->msvld , device->msvld); | |
2494 | _(NVENC0 , device->nvenc[0], device->nvenc[0]); | |
2495 | _(NVENC1 , device->nvenc[1], device->nvenc[1]); | |
cb7b5ea9 | 2496 | _(NVENC2 , device->nvenc[2], device->nvenc[2]); |
16307b5d | 2497 | _(NVDEC , device->nvdec , &device->nvdec->engine); |
294af04b BS |
2498 | _(PM , device->pm , &device->pm->engine); |
2499 | _(SEC , device->sec , device->sec); | |
b62880f7 | 2500 | _(SEC2 , device->sec2 , &device->sec2->engine); |
294af04b BS |
2501 | _(SW , device->sw , &device->sw->engine); |
2502 | _(VIC , device->vic , device->vic); | |
2503 | _(VP , device->vp , device->vp); | |
6cf813fb BS |
2504 | #undef _ |
2505 | default: | |
2506 | WARN_ON(1); | |
2507 | break; | |
2508 | } | |
2509 | return NULL; | |
2510 | } | |
2511 | ||
a1e88736 BS |
2512 | int |
2513 | nvkm_device_fini(struct nvkm_device *device, bool suspend) | |
066a5d09 | 2514 | { |
6cf813fb BS |
2515 | const char *action = suspend ? "suspend" : "fini"; |
2516 | struct nvkm_subdev *subdev; | |
10caad33 | 2517 | int ret, i; |
6cf813fb BS |
2518 | s64 time; |
2519 | ||
2520 | nvdev_trace(device, "%s running...\n", action); | |
2521 | time = ktime_to_us(ktime_get()); | |
2522 | ||
2523 | nvkm_acpi_fini(device); | |
10caad33 | 2524 | |
68f3f702 | 2525 | for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { |
6cf813fb BS |
2526 | if ((subdev = nvkm_device_subdev(device, i))) { |
2527 | ret = nvkm_subdev_fini(subdev, suspend); | |
2528 | if (ret && suspend) | |
2529 | goto fail; | |
10caad33 BS |
2530 | } |
2531 | } | |
2532 | ||
b138eca6 | 2533 | nvkm_therm_clkgate_fini(device->therm, suspend); |
7974dd1b BS |
2534 | |
2535 | if (device->func->fini) | |
2536 | device->func->fini(device, suspend); | |
6cf813fb BS |
2537 | |
2538 | time = ktime_to_us(ktime_get()) - time; | |
2539 | nvdev_trace(device, "%s completed in %lldus...\n", action, time); | |
2540 | return 0; | |
2541 | ||
10caad33 | 2542 | fail: |
6cf813fb BS |
2543 | do { |
2544 | if ((subdev = nvkm_device_subdev(device, i))) { | |
2545 | int rret = nvkm_subdev_init(subdev); | |
2546 | if (rret) | |
2547 | nvkm_fatal(subdev, "failed restart, %d\n", ret); | |
10caad33 | 2548 | } |
68f3f702 | 2549 | } while (++i < NVKM_SUBDEV_NR); |
10caad33 | 2550 | |
6cf813fb | 2551 | nvdev_trace(device, "%s failed with %d\n", action, ret); |
10caad33 | 2552 | return ret; |
066a5d09 BS |
2553 | } |
2554 | ||
6cf813fb | 2555 | static int |
7974dd1b BS |
2556 | nvkm_device_preinit(struct nvkm_device *device) |
2557 | { | |
6cf813fb BS |
2558 | struct nvkm_subdev *subdev; |
2559 | int ret, i; | |
7974dd1b BS |
2560 | s64 time; |
2561 | ||
2562 | nvdev_trace(device, "preinit running...\n"); | |
2563 | time = ktime_to_us(ktime_get()); | |
2564 | ||
2565 | if (device->func->preinit) { | |
2566 | ret = device->func->preinit(device); | |
2567 | if (ret) | |
2568 | goto fail; | |
2569 | } | |
2570 | ||
68f3f702 | 2571 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
6cf813fb BS |
2572 | if ((subdev = nvkm_device_subdev(device, i))) { |
2573 | ret = nvkm_subdev_preinit(subdev); | |
2574 | if (ret) | |
2575 | goto fail; | |
2576 | } | |
2577 | } | |
2578 | ||
8de65bd0 BS |
2579 | ret = nvkm_devinit_post(device->devinit, &device->disable_mask); |
2580 | if (ret) | |
2581 | goto fail; | |
6cf813fb | 2582 | |
7974dd1b BS |
2583 | time = ktime_to_us(ktime_get()) - time; |
2584 | nvdev_trace(device, "preinit completed in %lldus\n", time); | |
2585 | return 0; | |
2586 | ||
2587 | fail: | |
2588 | nvdev_error(device, "preinit failed with %d\n", ret); | |
2589 | return ret; | |
2590 | } | |
2591 | ||
a1e88736 BS |
2592 | int |
2593 | nvkm_device_init(struct nvkm_device *device) | |
066a5d09 | 2594 | { |
6cf813fb | 2595 | struct nvkm_subdev *subdev; |
68f3f702 | 2596 | int ret, i; |
6cf813fb | 2597 | s64 time; |
ed76a870 | 2598 | |
7974dd1b BS |
2599 | ret = nvkm_device_preinit(device); |
2600 | if (ret) | |
2601 | return ret; | |
2602 | ||
6cf813fb BS |
2603 | nvkm_device_fini(device, false); |
2604 | ||
2605 | nvdev_trace(device, "init running...\n"); | |
2606 | time = ktime_to_us(ktime_get()); | |
10caad33 | 2607 | |
2b700825 BS |
2608 | if (device->func->init) { |
2609 | ret = device->func->init(device); | |
2610 | if (ret) | |
2611 | goto fail; | |
2612 | } | |
2613 | ||
68f3f702 BS |
2614 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
2615 | if ((subdev = nvkm_device_subdev(device, i))) { | |
2616 | ret = nvkm_subdev_init(subdev); | |
2617 | if (ret) | |
2b700825 | 2618 | goto fail_subdev; |
10caad33 BS |
2619 | } |
2620 | } | |
2621 | ||
6cf813fb | 2622 | nvkm_acpi_init(device); |
b138eca6 | 2623 | nvkm_therm_clkgate_enable(device->therm); |
6cf813fb BS |
2624 | |
2625 | time = ktime_to_us(ktime_get()) - time; | |
2626 | nvdev_trace(device, "init completed in %lldus\n", time); | |
2627 | return 0; | |
2628 | ||
2b700825 | 2629 | fail_subdev: |
6cf813fb BS |
2630 | do { |
2631 | if ((subdev = nvkm_device_subdev(device, i))) | |
2632 | nvkm_subdev_fini(subdev, false); | |
2633 | } while (--i >= 0); | |
10caad33 | 2634 | |
2b700825 | 2635 | fail: |
0529a46a AC |
2636 | nvkm_device_fini(device, false); |
2637 | ||
6cf813fb | 2638 | nvdev_error(device, "init failed with %d\n", ret); |
10caad33 | 2639 | return ret; |
066a5d09 BS |
2640 | } |
2641 | ||
e781dc8f BS |
2642 | void |
2643 | nvkm_device_del(struct nvkm_device **pdevice) | |
2644 | { | |
2645 | struct nvkm_device *device = *pdevice; | |
0ac9d210 | 2646 | int i; |
e781dc8f | 2647 | if (device) { |
e781dc8f | 2648 | mutex_lock(&nv_devices_mutex); |
6cf813fb | 2649 | device->disable_mask = 0; |
68f3f702 | 2650 | for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { |
6cf813fb BS |
2651 | struct nvkm_subdev *subdev = |
2652 | nvkm_device_subdev(device, i); | |
2653 | nvkm_subdev_del(&subdev); | |
2654 | } | |
0ac9d210 BS |
2655 | |
2656 | nvkm_event_fini(&device->event); | |
e781dc8f BS |
2657 | |
2658 | if (device->pri) | |
2659 | iounmap(device->pri); | |
0ac9d210 | 2660 | list_del(&device->head); |
7974dd1b BS |
2661 | |
2662 | if (device->func->dtor) | |
2663 | *pdevice = device->func->dtor(device); | |
0ac9d210 | 2664 | mutex_unlock(&nv_devices_mutex); |
e781dc8f | 2665 | |
7974dd1b | 2666 | kfree(*pdevice); |
e781dc8f BS |
2667 | *pdevice = NULL; |
2668 | } | |
2669 | } | |
2670 | ||
9274f4a9 | 2671 | int |
7974dd1b BS |
2672 | nvkm_device_ctor(const struct nvkm_device_func *func, |
2673 | const struct nvkm_device_quirk *quirk, | |
26c9e8ef | 2674 | struct device *dev, enum nvkm_device_type type, u64 handle, |
7974dd1b BS |
2675 | const char *name, const char *cfg, const char *dbg, |
2676 | bool detect, bool mmio, u64 subdev_mask, | |
2677 | struct nvkm_device *device) | |
9274f4a9 | 2678 | { |
6cf813fb | 2679 | struct nvkm_subdev *subdev; |
0ac9d210 BS |
2680 | u64 mmio_base, mmio_size; |
2681 | u32 boot0, strap; | |
2682 | void __iomem *map; | |
9274f4a9 | 2683 | int ret = -EEXIST; |
0ac9d210 | 2684 | int i; |
9274f4a9 BS |
2685 | |
2686 | mutex_lock(&nv_devices_mutex); | |
7974dd1b BS |
2687 | if (nvkm_device_find_locked(handle)) |
2688 | goto done; | |
9274f4a9 | 2689 | |
7974dd1b | 2690 | device->func = func; |
7974dd1b | 2691 | device->quirk = quirk; |
26c9e8ef BS |
2692 | device->dev = dev; |
2693 | device->type = type; | |
7974dd1b | 2694 | device->handle = handle; |
9274f4a9 BS |
2695 | device->cfgopt = cfg; |
2696 | device->dbgopt = dbg; | |
7974dd1b | 2697 | device->name = name; |
0d5dd3f3 | 2698 | list_add_tail(&device->head, &nv_devices); |
68f3f702 | 2699 | device->debug = nvkm_dbgopt(device->dbgopt, "device"); |
6cf813fb | 2700 | |
9719047b | 2701 | ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); |
0ac9d210 BS |
2702 | if (ret) |
2703 | goto done; | |
2704 | ||
7e8820fe BS |
2705 | mmio_base = device->func->resource_addr(device, 0); |
2706 | mmio_size = device->func->resource_size(device, 0); | |
0ac9d210 BS |
2707 | |
2708 | /* identify the chipset, and determine classes of subdev/engines */ | |
2709 | if (detect) { | |
2710 | map = ioremap(mmio_base, 0x102000); | |
2711 | if (ret = -ENOMEM, map == NULL) | |
2712 | goto done; | |
2713 | ||
2714 | /* switch mmio to cpu's native endianness */ | |
2715 | #ifndef __BIG_ENDIAN | |
2716 | if (ioread32_native(map + 0x000004) != 0x00000000) { | |
2717 | #else | |
2718 | if (ioread32_native(map + 0x000004) == 0x00000000) { | |
2719 | #endif | |
2720 | iowrite32_native(0x01000001, map + 0x000004); | |
2721 | ioread32_native(map); | |
2722 | } | |
2723 | ||
2724 | /* read boot0 and strapping information */ | |
2725 | boot0 = ioread32_native(map + 0x000000); | |
2726 | strap = ioread32_native(map + 0x101000); | |
2727 | iounmap(map); | |
2728 | ||
2729 | /* determine chipset and derive architecture from it */ | |
2730 | if ((boot0 & 0x1f000000) > 0) { | |
2731 | device->chipset = (boot0 & 0x1ff00000) >> 20; | |
2732 | device->chiprev = (boot0 & 0x000000ff); | |
2733 | switch (device->chipset & 0x1f0) { | |
2734 | case 0x010: { | |
2735 | if (0x461 & (1 << (device->chipset & 0xf))) | |
2736 | device->card_type = NV_10; | |
2737 | else | |
2738 | device->card_type = NV_11; | |
2739 | device->chiprev = 0x00; | |
2740 | break; | |
2741 | } | |
2742 | case 0x020: device->card_type = NV_20; break; | |
2743 | case 0x030: device->card_type = NV_30; break; | |
2744 | case 0x040: | |
2745 | case 0x060: device->card_type = NV_40; break; | |
2746 | case 0x050: | |
2747 | case 0x080: | |
2748 | case 0x090: | |
2749 | case 0x0a0: device->card_type = NV_50; break; | |
2750 | case 0x0c0: | |
2751 | case 0x0d0: device->card_type = NV_C0; break; | |
2752 | case 0x0e0: | |
2753 | case 0x0f0: | |
2754 | case 0x100: device->card_type = NV_E0; break; | |
2755 | case 0x110: | |
2756 | case 0x120: device->card_type = GM100; break; | |
7f53abdb | 2757 | case 0x130: device->card_type = GP100; break; |
c1f856bb | 2758 | case 0x140: device->card_type = GV100; break; |
0ac9d210 BS |
2759 | default: |
2760 | break; | |
2761 | } | |
2762 | } else | |
2763 | if ((boot0 & 0xff00fff0) == 0x20004000) { | |
2764 | if (boot0 & 0x00f00000) | |
2765 | device->chipset = 0x05; | |
2766 | else | |
2767 | device->chipset = 0x04; | |
2768 | device->card_type = NV_04; | |
2769 | } | |
2770 | ||
68f3f702 | 2771 | switch (device->chipset) { |
6cf813fb BS |
2772 | case 0x004: device->chip = &nv4_chipset; break; |
2773 | case 0x005: device->chip = &nv5_chipset; break; | |
2774 | case 0x010: device->chip = &nv10_chipset; break; | |
2775 | case 0x011: device->chip = &nv11_chipset; break; | |
2776 | case 0x015: device->chip = &nv15_chipset; break; | |
2777 | case 0x017: device->chip = &nv17_chipset; break; | |
2778 | case 0x018: device->chip = &nv18_chipset; break; | |
2779 | case 0x01a: device->chip = &nv1a_chipset; break; | |
2780 | case 0x01f: device->chip = &nv1f_chipset; break; | |
2781 | case 0x020: device->chip = &nv20_chipset; break; | |
2782 | case 0x025: device->chip = &nv25_chipset; break; | |
2783 | case 0x028: device->chip = &nv28_chipset; break; | |
2784 | case 0x02a: device->chip = &nv2a_chipset; break; | |
2785 | case 0x030: device->chip = &nv30_chipset; break; | |
2786 | case 0x031: device->chip = &nv31_chipset; break; | |
2787 | case 0x034: device->chip = &nv34_chipset; break; | |
2788 | case 0x035: device->chip = &nv35_chipset; break; | |
2789 | case 0x036: device->chip = &nv36_chipset; break; | |
2790 | case 0x040: device->chip = &nv40_chipset; break; | |
2791 | case 0x041: device->chip = &nv41_chipset; break; | |
2792 | case 0x042: device->chip = &nv42_chipset; break; | |
2793 | case 0x043: device->chip = &nv43_chipset; break; | |
2794 | case 0x044: device->chip = &nv44_chipset; break; | |
2795 | case 0x045: device->chip = &nv45_chipset; break; | |
2796 | case 0x046: device->chip = &nv46_chipset; break; | |
2797 | case 0x047: device->chip = &nv47_chipset; break; | |
2798 | case 0x049: device->chip = &nv49_chipset; break; | |
2799 | case 0x04a: device->chip = &nv4a_chipset; break; | |
2800 | case 0x04b: device->chip = &nv4b_chipset; break; | |
2801 | case 0x04c: device->chip = &nv4c_chipset; break; | |
2802 | case 0x04e: device->chip = &nv4e_chipset; break; | |
2803 | case 0x050: device->chip = &nv50_chipset; break; | |
2804 | case 0x063: device->chip = &nv63_chipset; break; | |
2805 | case 0x067: device->chip = &nv67_chipset; break; | |
2806 | case 0x068: device->chip = &nv68_chipset; break; | |
2807 | case 0x084: device->chip = &nv84_chipset; break; | |
2808 | case 0x086: device->chip = &nv86_chipset; break; | |
2809 | case 0x092: device->chip = &nv92_chipset; break; | |
2810 | case 0x094: device->chip = &nv94_chipset; break; | |
2811 | case 0x096: device->chip = &nv96_chipset; break; | |
2812 | case 0x098: device->chip = &nv98_chipset; break; | |
2813 | case 0x0a0: device->chip = &nva0_chipset; break; | |
2814 | case 0x0a3: device->chip = &nva3_chipset; break; | |
2815 | case 0x0a5: device->chip = &nva5_chipset; break; | |
2816 | case 0x0a8: device->chip = &nva8_chipset; break; | |
2817 | case 0x0aa: device->chip = &nvaa_chipset; break; | |
2818 | case 0x0ac: device->chip = &nvac_chipset; break; | |
2819 | case 0x0af: device->chip = &nvaf_chipset; break; | |
2820 | case 0x0c0: device->chip = &nvc0_chipset; break; | |
2821 | case 0x0c1: device->chip = &nvc1_chipset; break; | |
2822 | case 0x0c3: device->chip = &nvc3_chipset; break; | |
2823 | case 0x0c4: device->chip = &nvc4_chipset; break; | |
2824 | case 0x0c8: device->chip = &nvc8_chipset; break; | |
2825 | case 0x0ce: device->chip = &nvce_chipset; break; | |
2826 | case 0x0cf: device->chip = &nvcf_chipset; break; | |
2827 | case 0x0d7: device->chip = &nvd7_chipset; break; | |
2828 | case 0x0d9: device->chip = &nvd9_chipset; break; | |
2829 | case 0x0e4: device->chip = &nve4_chipset; break; | |
2830 | case 0x0e6: device->chip = &nve6_chipset; break; | |
2831 | case 0x0e7: device->chip = &nve7_chipset; break; | |
2832 | case 0x0ea: device->chip = &nvea_chipset; break; | |
2833 | case 0x0f0: device->chip = &nvf0_chipset; break; | |
2834 | case 0x0f1: device->chip = &nvf1_chipset; break; | |
2835 | case 0x106: device->chip = &nv106_chipset; break; | |
2836 | case 0x108: device->chip = &nv108_chipset; break; | |
2837 | case 0x117: device->chip = &nv117_chipset; break; | |
f9e20294 | 2838 | case 0x118: device->chip = &nv118_chipset; break; |
2ed95a4c | 2839 | case 0x120: device->chip = &nv120_chipset; break; |
6cf813fb BS |
2840 | case 0x124: device->chip = &nv124_chipset; break; |
2841 | case 0x126: device->chip = &nv126_chipset; break; | |
2842 | case 0x12b: device->chip = &nv12b_chipset; break; | |
7f53abdb | 2843 | case 0x130: device->chip = &nv130_chipset; break; |
17ff521d | 2844 | case 0x132: device->chip = &nv132_chipset; break; |
cfb083f6 | 2845 | case 0x134: device->chip = &nv134_chipset; break; |
1fe487d7 | 2846 | case 0x136: device->chip = &nv136_chipset; break; |
2ebd42bc | 2847 | case 0x137: device->chip = &nv137_chipset; break; |
2659b4ce | 2848 | case 0x138: device->chip = &nv138_chipset; break; |
fa1dbc49 | 2849 | case 0x13b: device->chip = &nv13b_chipset; break; |
c1f856bb | 2850 | case 0x140: device->chip = &nv140_chipset; break; |
6cf813fb | 2851 | default: |
0ac9d210 BS |
2852 | nvdev_error(device, "unknown chipset (%08x)\n", boot0); |
2853 | goto done; | |
2854 | } | |
2855 | ||
6cf813fb BS |
2856 | nvdev_info(device, "NVIDIA %s (%08x)\n", |
2857 | device->chip->name, boot0); | |
0ac9d210 BS |
2858 | |
2859 | /* determine frequency of timing crystal */ | |
2860 | if ( device->card_type <= NV_10 || device->chipset < 0x17 || | |
2861 | (device->chipset >= 0x20 && device->chipset < 0x25)) | |
2862 | strap &= 0x00000040; | |
2863 | else | |
2864 | strap &= 0x00400040; | |
2865 | ||
2866 | switch (strap) { | |
2867 | case 0x00000000: device->crystal = 13500; break; | |
2868 | case 0x00000040: device->crystal = 14318; break; | |
2869 | case 0x00400000: device->crystal = 27000; break; | |
2870 | case 0x00400040: device->crystal = 25000; break; | |
2871 | } | |
2872 | } else { | |
6cf813fb | 2873 | device->chip = &null_chipset; |
0ac9d210 BS |
2874 | } |
2875 | ||
6cf813fb BS |
2876 | if (!device->name) |
2877 | device->name = device->chip->name; | |
2878 | ||
0ac9d210 BS |
2879 | if (mmio) { |
2880 | device->pri = ioremap(mmio_base, mmio_size); | |
2881 | if (!device->pri) { | |
2882 | nvdev_error(device, "unable to map PRI\n"); | |
1299b637 AC |
2883 | ret = -ENOMEM; |
2884 | goto done; | |
0ac9d210 BS |
2885 | } |
2886 | } | |
2887 | ||
a1e88736 | 2888 | mutex_init(&device->mutex); |
6cf813fb | 2889 | |
68f3f702 | 2890 | for (i = 0; i < NVKM_SUBDEV_NR; i++) { |
6cf813fb BS |
2891 | #define _(s,m) case s: \ |
2892 | if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ | |
2893 | ret = device->chip->m(device, (s), &device->m); \ | |
2894 | if (ret) { \ | |
2895 | subdev = nvkm_device_subdev(device, (s)); \ | |
2896 | nvkm_subdev_del(&subdev); \ | |
2897 | device->m = NULL; \ | |
2898 | if (ret != -ENODEV) { \ | |
2899 | nvdev_error(device, "%s ctor failed, %d\n", \ | |
2900 | nvkm_subdev_name[s], ret); \ | |
2901 | goto done; \ | |
2902 | } \ | |
2903 | } \ | |
2904 | } \ | |
2905 | break | |
2906 | switch (i) { | |
dc06e366 MP |
2907 | _(NVKM_SUBDEV_BAR , bar); |
2908 | _(NVKM_SUBDEV_VBIOS , bios); | |
2909 | _(NVKM_SUBDEV_BUS , bus); | |
2910 | _(NVKM_SUBDEV_CLK , clk); | |
2911 | _(NVKM_SUBDEV_DEVINIT , devinit); | |
1ce46689 | 2912 | _(NVKM_SUBDEV_FAULT , fault); |
dc06e366 MP |
2913 | _(NVKM_SUBDEV_FB , fb); |
2914 | _(NVKM_SUBDEV_FUSE , fuse); | |
2915 | _(NVKM_SUBDEV_GPIO , gpio); | |
2916 | _(NVKM_SUBDEV_I2C , i2c); | |
2917 | _(NVKM_SUBDEV_IBUS , ibus); | |
2918 | _(NVKM_SUBDEV_ICCSENSE, iccsense); | |
2919 | _(NVKM_SUBDEV_INSTMEM , imem); | |
2920 | _(NVKM_SUBDEV_LTC , ltc); | |
2921 | _(NVKM_SUBDEV_MC , mc); | |
2922 | _(NVKM_SUBDEV_MMU , mmu); | |
2923 | _(NVKM_SUBDEV_MXM , mxm); | |
2924 | _(NVKM_SUBDEV_PCI , pci); | |
2925 | _(NVKM_SUBDEV_PMU , pmu); | |
2926 | _(NVKM_SUBDEV_SECBOOT , secboot); | |
2927 | _(NVKM_SUBDEV_THERM , therm); | |
2928 | _(NVKM_SUBDEV_TIMER , timer); | |
eaebfcc3 | 2929 | _(NVKM_SUBDEV_TOP , top); |
dc06e366 MP |
2930 | _(NVKM_SUBDEV_VOLT , volt); |
2931 | _(NVKM_ENGINE_BSP , bsp); | |
2932 | _(NVKM_ENGINE_CE0 , ce[0]); | |
2933 | _(NVKM_ENGINE_CE1 , ce[1]); | |
2934 | _(NVKM_ENGINE_CE2 , ce[2]); | |
34bf50cd BS |
2935 | _(NVKM_ENGINE_CE3 , ce[3]); |
2936 | _(NVKM_ENGINE_CE4 , ce[4]); | |
2937 | _(NVKM_ENGINE_CE5 , ce[5]); | |
890c85f3 BS |
2938 | _(NVKM_ENGINE_CE6 , ce[6]); |
2939 | _(NVKM_ENGINE_CE7 , ce[7]); | |
2940 | _(NVKM_ENGINE_CE8 , ce[8]); | |
dc06e366 MP |
2941 | _(NVKM_ENGINE_CIPHER , cipher); |
2942 | _(NVKM_ENGINE_DISP , disp); | |
2943 | _(NVKM_ENGINE_DMAOBJ , dma); | |
2944 | _(NVKM_ENGINE_FIFO , fifo); | |
2945 | _(NVKM_ENGINE_GR , gr); | |
2946 | _(NVKM_ENGINE_IFB , ifb); | |
2947 | _(NVKM_ENGINE_ME , me); | |
2948 | _(NVKM_ENGINE_MPEG , mpeg); | |
2949 | _(NVKM_ENGINE_MSENC , msenc); | |
2950 | _(NVKM_ENGINE_MSPDEC , mspdec); | |
2951 | _(NVKM_ENGINE_MSPPP , msppp); | |
2952 | _(NVKM_ENGINE_MSVLD , msvld); | |
294af04b BS |
2953 | _(NVKM_ENGINE_NVENC0 , nvenc[0]); |
2954 | _(NVKM_ENGINE_NVENC1 , nvenc[1]); | |
cb7b5ea9 | 2955 | _(NVKM_ENGINE_NVENC2 , nvenc[2]); |
3545b425 | 2956 | _(NVKM_ENGINE_NVDEC , nvdec); |
dc06e366 MP |
2957 | _(NVKM_ENGINE_PM , pm); |
2958 | _(NVKM_ENGINE_SEC , sec); | |
b62880f7 | 2959 | _(NVKM_ENGINE_SEC2 , sec2); |
dc06e366 MP |
2960 | _(NVKM_ENGINE_SW , sw); |
2961 | _(NVKM_ENGINE_VIC , vic); | |
2962 | _(NVKM_ENGINE_VP , vp); | |
6cf813fb BS |
2963 | default: |
2964 | WARN_ON(1); | |
2965 | continue; | |
2966 | } | |
2967 | #undef _ | |
2968 | } | |
2969 | ||
2970 | ret = 0; | |
9274f4a9 BS |
2971 | done: |
2972 | mutex_unlock(&nv_devices_mutex); | |
2973 | return ret; | |
2974 | } |