]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
drm/nouveau/tmr: convert to new-style nvkm_subdev
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / gm100.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
9719047b 24#include "priv.h"
3f204647 25
3f204647 26int
9719047b 27gm100_identify(struct nvkm_device *device)
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28{
29 switch (device->chipset) {
30 case 0x117:
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31
32#if 0
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33 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
34#endif
5b85057a 35 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
05c7145d 36 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
f84aff4e 37 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
b8bf04e1 38 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
3f204647 39 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
bd6c5cab 40 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
3f204647 41#if 0
bd6c5cab 42 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
3f204647 43#endif
bd6c5cab 44 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
3f204647 45#if 0
87c33f4e 46 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20 47 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657 48 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
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49#endif
50 break;
51 case 0x124:
7e547adc
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52#if 0
53 /* looks to be some non-trivial changes */
7e547adc 54 /* priv ring says no to 0x10eb14 writes */
7e547adc 55#endif
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56#if 0
57 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
58#endif
59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
89025bd4 60 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
7e547adc 61 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
3fed3ea9 62 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
7e547adc 63 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
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64 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
65 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
66 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
b44881e4 67#if 0
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68 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
69 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
70 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
71#endif
72 break;
73 case 0x126:
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74#if 0
75 /* looks to be some non-trivial changes */
083dba02 76 /* priv ring says no to 0x10eb14 writes */
083dba02 77#endif
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78#if 0
79 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
80#endif
5b85057a 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
5dd7fb77 82 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
f84aff4e 83 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
426b20e4 84 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
083dba02 85 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
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BS
86 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
87 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
88 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
985826bc 89#if 0
87c33f4e 90 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
e3332c20 91 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
87a87657 92 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
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93#endif
94 break;
d10ae271 95 case 0x12b:
d10ae271 96
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97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
98 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
100 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
101 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
102 break;
3f204647 103 default:
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104 return -EINVAL;
105 }
106
107 return 0;
108}