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1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
878da15a BS |
24 | #include "dport.h" |
25 | #include "outpdp.h" | |
26 | #include "nv50.h" | |
0a0afd28 BS |
27 | |
28 | #include <subdev/bios.h> | |
0a0afd28 BS |
29 | #include <subdev/bios/init.h> |
30 | #include <subdev/i2c.h> | |
31 | ||
648d4dfd | 32 | #include <nvif/class.h> |
04e7e92d | 33 | |
0a0afd28 BS |
34 | /****************************************************************************** |
35 | * link training | |
36 | *****************************************************************************/ | |
37 | struct dp_state { | |
3b52a1f9 | 38 | struct nvkm_output_dp *outp; |
0a0afd28 BS |
39 | int link_nr; |
40 | u32 link_bw; | |
41 | u8 stat[6]; | |
42 | u8 conf[4]; | |
04e7e92d BS |
43 | bool pc2; |
44 | u8 pc2stat; | |
45 | u8 pc2conf[2]; | |
0a0afd28 BS |
46 | }; |
47 | ||
48 | static int | |
49 | dp_set_link_config(struct dp_state *dp) | |
50 | { | |
3b52a1f9 | 51 | struct nvkm_output_dp *outp = dp->outp; |
f2c906fc BS |
52 | struct nvkm_disp *disp = outp->base.disp; |
53 | struct nvkm_subdev *subdev = &disp->engine.subdev; | |
54 | struct nvkm_bios *bios = subdev->device->bios; | |
0a0afd28 | 55 | struct nvbios_init init = { |
f2c906fc | 56 | .subdev = subdev, |
0a0afd28 BS |
57 | .bios = bios, |
58 | .offset = 0x0000, | |
3b52a1f9 BS |
59 | .outp = &outp->base.info, |
60 | .crtc = -1, | |
0a0afd28 BS |
61 | .execute = 1, |
62 | }; | |
63 | u32 lnkcmp; | |
64 | u8 sink[2]; | |
8df1d0c0 | 65 | int ret; |
0a0afd28 | 66 | |
f2c906fc | 67 | OUTP_DBG(&outp->base, "%d lanes at %d KB/s", dp->link_nr, dp->link_bw); |
0a0afd28 | 68 | |
0a0afd28 | 69 | /* set desired link configuration on the source */ |
3b52a1f9 BS |
70 | if ((lnkcmp = dp->outp->info.lnkcmp)) { |
71 | if (outp->version < 0x30) { | |
7f5f518f | 72 | while ((dp->link_bw / 10) < nvbios_rd16(bios, lnkcmp)) |
0a0afd28 | 73 | lnkcmp += 4; |
7f5f518f | 74 | init.offset = nvbios_rd16(bios, lnkcmp + 2); |
0a0afd28 | 75 | } else { |
7f5f518f | 76 | while ((dp->link_bw / 27000) < nvbios_rd08(bios, lnkcmp)) |
0a0afd28 | 77 | lnkcmp += 3; |
7f5f518f | 78 | init.offset = nvbios_rd16(bios, lnkcmp + 1); |
0a0afd28 BS |
79 | } |
80 | ||
81 | nvbios_exec(&init); | |
82 | } | |
83 | ||
f2c906fc BS |
84 | ret = outp->func->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, |
85 | outp->dpcd[DPCD_RC02] & | |
86 | DPCD_RC02_ENHANCED_FRAME_CAP); | |
8df1d0c0 | 87 | if (ret) { |
3b52a1f9 | 88 | if (ret < 0) |
f2c906fc | 89 | OUTP_ERR(&outp->base, "lnk_ctl failed with %d", ret); |
8df1d0c0 BS |
90 | return ret; |
91 | } | |
92 | ||
f2c906fc | 93 | outp->func->lnk_pwr(outp, dp->link_nr); |
1ecee1cd | 94 | |
8df1d0c0 BS |
95 | /* set desired link configuration on the sink */ |
96 | sink[0] = dp->link_bw / 27000; | |
97 | sink[1] = dp->link_nr; | |
3b52a1f9 | 98 | if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) |
8df1d0c0 BS |
99 | sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; |
100 | ||
2aa5eac5 | 101 | return nvkm_wraux(outp->aux, DPCD_LC00_LINK_BW_SET, sink, 2); |
0a0afd28 BS |
102 | } |
103 | ||
104 | static void | |
105 | dp_set_training_pattern(struct dp_state *dp, u8 pattern) | |
106 | { | |
3b52a1f9 | 107 | struct nvkm_output_dp *outp = dp->outp; |
0a0afd28 BS |
108 | u8 sink_tp; |
109 | ||
f2c906fc BS |
110 | OUTP_DBG(&outp->base, "training pattern %d", pattern); |
111 | outp->func->pattern(outp, pattern); | |
0a0afd28 | 112 | |
2aa5eac5 | 113 | nvkm_rdaux(outp->aux, DPCD_LC02, &sink_tp, 1); |
0a0afd28 BS |
114 | sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; |
115 | sink_tp |= pattern; | |
2aa5eac5 | 116 | nvkm_wraux(outp->aux, DPCD_LC02, &sink_tp, 1); |
0a0afd28 BS |
117 | } |
118 | ||
119 | static int | |
04e7e92d | 120 | dp_link_train_commit(struct dp_state *dp, bool pc) |
0a0afd28 | 121 | { |
3b52a1f9 | 122 | struct nvkm_output_dp *outp = dp->outp; |
04e7e92d | 123 | int ret, i; |
0a0afd28 BS |
124 | |
125 | for (i = 0; i < dp->link_nr; i++) { | |
126 | u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; | |
c33ba689 | 127 | u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3; |
0a0afd28 BS |
128 | u8 lpre = (lane & 0x0c) >> 2; |
129 | u8 lvsw = (lane & 0x03) >> 0; | |
c33ba689 BS |
130 | u8 hivs = 3 - lpre; |
131 | u8 hipe = 3; | |
132 | u8 hipc = 3; | |
133 | ||
134 | if (lpc2 >= hipc) | |
135 | lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED; | |
136 | if (lpre >= hipe) { | |
137 | lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */ | |
138 | lvsw = hivs = 3 - (lpre & 3); | |
139 | } else | |
140 | if (lvsw >= hivs) { | |
141 | lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED; | |
142 | } | |
0a0afd28 BS |
143 | |
144 | dp->conf[i] = (lpre << 3) | lvsw; | |
c33ba689 BS |
145 | dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); |
146 | ||
f2c906fc BS |
147 | OUTP_DBG(&outp->base, "config lane %d %02x %02x", |
148 | i, dp->conf[i], lpc2); | |
149 | outp->func->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3); | |
04e7e92d BS |
150 | } |
151 | ||
2aa5eac5 | 152 | ret = nvkm_wraux(outp->aux, DPCD_LC03(0), dp->conf, 4); |
04e7e92d BS |
153 | if (ret) |
154 | return ret; | |
155 | ||
156 | if (pc) { | |
2aa5eac5 | 157 | ret = nvkm_wraux(outp->aux, DPCD_LC0F, dp->pc2conf, 2); |
04e7e92d BS |
158 | if (ret) |
159 | return ret; | |
0a0afd28 BS |
160 | } |
161 | ||
04e7e92d | 162 | return 0; |
0a0afd28 BS |
163 | } |
164 | ||
165 | static int | |
04e7e92d | 166 | dp_link_train_update(struct dp_state *dp, bool pc, u32 delay) |
0a0afd28 | 167 | { |
3b52a1f9 | 168 | struct nvkm_output_dp *outp = dp->outp; |
0a0afd28 BS |
169 | int ret; |
170 | ||
3b52a1f9 BS |
171 | if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) |
172 | mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); | |
fb7c2a71 BS |
173 | else |
174 | udelay(delay); | |
0a0afd28 | 175 | |
2aa5eac5 | 176 | ret = nvkm_rdaux(outp->aux, DPCD_LS02, dp->stat, 6); |
0a0afd28 BS |
177 | if (ret) |
178 | return ret; | |
179 | ||
04e7e92d | 180 | if (pc) { |
2aa5eac5 | 181 | ret = nvkm_rdaux(outp->aux, DPCD_LS0C, &dp->pc2stat, 1); |
04e7e92d BS |
182 | if (ret) |
183 | dp->pc2stat = 0x00; | |
f2c906fc BS |
184 | OUTP_DBG(&outp->base, "status %6ph pc2 %02x", |
185 | dp->stat, dp->pc2stat); | |
04e7e92d | 186 | } else { |
f2c906fc | 187 | OUTP_DBG(&outp->base, "status %6ph", dp->stat); |
04e7e92d BS |
188 | } |
189 | ||
0a0afd28 BS |
190 | return 0; |
191 | } | |
192 | ||
193 | static int | |
194 | dp_link_train_cr(struct dp_state *dp) | |
195 | { | |
196 | bool cr_done = false, abort = false; | |
197 | int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; | |
198 | int tries = 0, i; | |
199 | ||
200 | dp_set_training_pattern(dp, 1); | |
201 | ||
202 | do { | |
04e7e92d BS |
203 | if (dp_link_train_commit(dp, false) || |
204 | dp_link_train_update(dp, false, 100)) | |
0a0afd28 BS |
205 | break; |
206 | ||
207 | cr_done = true; | |
208 | for (i = 0; i < dp->link_nr; i++) { | |
209 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; | |
210 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { | |
211 | cr_done = false; | |
212 | if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED) | |
213 | abort = true; | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
218 | if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { | |
219 | voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; | |
220 | tries = 0; | |
221 | } | |
222 | } while (!cr_done && !abort && ++tries < 5); | |
223 | ||
224 | return cr_done ? 0 : -1; | |
225 | } | |
226 | ||
227 | static int | |
228 | dp_link_train_eq(struct dp_state *dp) | |
229 | { | |
3b52a1f9 | 230 | struct nvkm_output_dp *outp = dp->outp; |
c5bd028b | 231 | bool eq_done = false, cr_done = true; |
0a0afd28 BS |
232 | int tries = 0, i; |
233 | ||
3b52a1f9 | 234 | if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) |
6e8e268b BS |
235 | dp_set_training_pattern(dp, 3); |
236 | else | |
237 | dp_set_training_pattern(dp, 2); | |
0a0afd28 BS |
238 | |
239 | do { | |
cf7c5d67 BS |
240 | if ((tries && |
241 | dp_link_train_commit(dp, dp->pc2)) || | |
242 | dp_link_train_update(dp, dp->pc2, 400)) | |
0a0afd28 BS |
243 | break; |
244 | ||
245 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); | |
246 | for (i = 0; i < dp->link_nr && eq_done; i++) { | |
247 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; | |
248 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) | |
249 | cr_done = false; | |
250 | if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || | |
251 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) | |
252 | eq_done = false; | |
253 | } | |
0a0afd28 BS |
254 | } while (!eq_done && cr_done && ++tries <= 5); |
255 | ||
256 | return eq_done ? 0 : -1; | |
257 | } | |
258 | ||
259 | static void | |
260 | dp_link_train_init(struct dp_state *dp, bool spread) | |
261 | { | |
3b52a1f9 | 262 | struct nvkm_output_dp *outp = dp->outp; |
f2c906fc BS |
263 | struct nvkm_disp *disp = outp->base.disp; |
264 | struct nvkm_subdev *subdev = &disp->engine.subdev; | |
0a0afd28 | 265 | struct nvbios_init init = { |
f2c906fc BS |
266 | .subdev = subdev, |
267 | .bios = subdev->device->bios, | |
3b52a1f9 BS |
268 | .outp = &outp->base.info, |
269 | .crtc = -1, | |
0a0afd28 BS |
270 | .execute = 1, |
271 | }; | |
272 | ||
273 | /* set desired spread */ | |
274 | if (spread) | |
3b52a1f9 | 275 | init.offset = outp->info.script[2]; |
0a0afd28 | 276 | else |
3b52a1f9 | 277 | init.offset = outp->info.script[3]; |
0a0afd28 BS |
278 | nvbios_exec(&init); |
279 | ||
280 | /* pre-train script */ | |
3b52a1f9 | 281 | init.offset = outp->info.script[0]; |
0a0afd28 BS |
282 | nvbios_exec(&init); |
283 | } | |
284 | ||
285 | static void | |
286 | dp_link_train_fini(struct dp_state *dp) | |
287 | { | |
3b52a1f9 | 288 | struct nvkm_output_dp *outp = dp->outp; |
f2c906fc BS |
289 | struct nvkm_disp *disp = outp->base.disp; |
290 | struct nvkm_subdev *subdev = &disp->engine.subdev; | |
0a0afd28 | 291 | struct nvbios_init init = { |
f2c906fc BS |
292 | .subdev = subdev, |
293 | .bios = subdev->device->bios, | |
3b52a1f9 BS |
294 | .outp = &outp->base.info, |
295 | .crtc = -1, | |
0a0afd28 BS |
296 | .execute = 1, |
297 | }; | |
298 | ||
299 | /* post-train script */ | |
3b52a1f9 | 300 | init.offset = outp->info.script[1], |
0a0afd28 BS |
301 | nvbios_exec(&init); |
302 | } | |
303 | ||
1f86ca1a BS |
304 | static const struct dp_rates { |
305 | u32 rate; | |
306 | u8 bw; | |
307 | u8 nr; | |
878da15a | 308 | } nvkm_dp_rates[] = { |
1f86ca1a BS |
309 | { 2160000, 0x14, 4 }, |
310 | { 1080000, 0x0a, 4 }, | |
311 | { 1080000, 0x14, 2 }, | |
312 | { 648000, 0x06, 4 }, | |
313 | { 540000, 0x0a, 2 }, | |
314 | { 540000, 0x14, 1 }, | |
315 | { 324000, 0x06, 2 }, | |
316 | { 270000, 0x0a, 1 }, | |
317 | { 162000, 0x06, 1 }, | |
318 | {} | |
319 | }; | |
320 | ||
55f083c3 | 321 | void |
878da15a | 322 | nvkm_dp_train(struct work_struct *w) |
0a0afd28 | 323 | { |
55f083c3 | 324 | struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); |
70aa8670 | 325 | struct nv50_disp *disp = nv50_disp(outp->base.disp); |
878da15a | 326 | const struct dp_rates *cfg = nvkm_dp_rates; |
0a0afd28 | 327 | struct dp_state _dp = { |
0a0afd28 | 328 | .outp = outp, |
0a0afd28 | 329 | }, *dp = &_dp; |
55f083c3 | 330 | u32 datarate = 0; |
95664e66 | 331 | u8 pwr; |
0a0afd28 BS |
332 | int ret; |
333 | ||
70aa8670 BS |
334 | if (!outp->base.info.location && disp->func->sor.magic) |
335 | disp->func->sor.magic(&outp->base); | |
c21e6b30 | 336 | |
fc243d7f | 337 | /* bring capabilities within encoder limits */ |
f2c906fc | 338 | if (disp->base.engine.subdev.device->chipset < 0xd0) |
3b52a1f9 BS |
339 | outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; |
340 | if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { | |
341 | outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; | |
342 | outp->dpcd[2] |= outp->base.info.dpconf.link_nr; | |
fc243d7f | 343 | } |
3b52a1f9 BS |
344 | if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) |
345 | outp->dpcd[1] = outp->base.info.dpconf.link_bw; | |
346 | dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED; | |
fc243d7f | 347 | |
1f86ca1a BS |
348 | /* restrict link config to the lowest required rate, if requested */ |
349 | if (datarate) { | |
350 | datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */ | |
351 | while (cfg[1].rate >= datarate) | |
352 | cfg++; | |
353 | } | |
354 | cfg--; | |
0a0afd28 | 355 | |
55f083c3 | 356 | /* disable link interrupt handling during link training */ |
79ca2770 | 357 | nvkm_notify_put(&outp->irq); |
55f083c3 | 358 | |
95664e66 BS |
359 | /* ensure sink is not in a low-power state */ |
360 | if (!nvkm_rdaux(outp->aux, DPCD_SC00, &pwr, 1)) { | |
361 | if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) { | |
362 | pwr &= ~DPCD_SC00_SET_POWER; | |
363 | pwr |= DPCD_SC00_SET_POWER_D0; | |
364 | nvkm_wraux(outp->aux, DPCD_SC00, &pwr, 1); | |
365 | } | |
366 | } | |
367 | ||
0a0afd28 | 368 | /* enable down-spreading and execute pre-train script from vbios */ |
3b52a1f9 | 369 | dp_link_train_init(dp, outp->dpcd[3] & 0x01); |
0a0afd28 | 370 | |
1f86ca1a BS |
371 | while (ret = -EIO, (++cfg)->rate) { |
372 | /* select next configuration supported by encoder and sink */ | |
3b52a1f9 BS |
373 | while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) || |
374 | cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE])) | |
1f86ca1a BS |
375 | cfg++; |
376 | dp->link_bw = cfg->bw * 27000; | |
377 | dp->link_nr = cfg->nr; | |
0a0afd28 BS |
378 | |
379 | /* program selected link configuration */ | |
380 | ret = dp_set_link_config(dp); | |
381 | if (ret == 0) { | |
382 | /* attempt to train the link at this configuration */ | |
383 | memset(dp->stat, 0x00, sizeof(dp->stat)); | |
384 | if (!dp_link_train_cr(dp) && | |
385 | !dp_link_train_eq(dp)) | |
386 | break; | |
387 | } else | |
8df1d0c0 BS |
388 | if (ret) { |
389 | /* dp_set_link_config() handled training, or | |
390 | * we failed to communicate with the sink. | |
391 | */ | |
0a0afd28 BS |
392 | break; |
393 | } | |
0a0afd28 BS |
394 | } |
395 | ||
55f083c3 | 396 | /* finish link training and execute post-train script from vbios */ |
0a0afd28 | 397 | dp_set_training_pattern(dp, 0); |
687d8f66 | 398 | if (ret < 0) |
f2c906fc | 399 | OUTP_ERR(&outp->base, "link training failed"); |
0a0afd28 | 400 | |
0a0afd28 | 401 | dp_link_train_fini(dp); |
55f083c3 BS |
402 | |
403 | /* signal completion and enable link interrupt handling */ | |
f2c906fc | 404 | OUTP_DBG(&outp->base, "training complete"); |
55f083c3 BS |
405 | atomic_set(&outp->lt.done, 1); |
406 | wake_up(&outp->lt.wait); | |
79ca2770 | 407 | nvkm_notify_get(&outp->irq); |
0a0afd28 | 408 | } |