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f7960736 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
f7960736 | 24 | #include "nv50.h" |
b8407c9e | 25 | #include "outpdp.h" |
f7960736 | 26 | |
878da15a BS |
27 | #include <subdev/timer.h> |
28 | ||
f7960736 | 29 | static inline u32 |
878da15a | 30 | g94_sor_soff(struct nvkm_output_dp *outp) |
f7960736 | 31 | { |
3b52a1f9 | 32 | return (ffs(outp->base.info.or) - 1) * 0x800; |
f7960736 BS |
33 | } |
34 | ||
0a0afd28 | 35 | static inline u32 |
878da15a | 36 | g94_sor_loff(struct nvkm_output_dp *outp) |
8f2abc25 | 37 | { |
878da15a | 38 | return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; |
8f2abc25 BS |
39 | } |
40 | ||
f2c906fc BS |
41 | /******************************************************************************* |
42 | * DisplayPort | |
43 | ******************************************************************************/ | |
2a893594 | 44 | u32 |
f2c906fc | 45 | g94_sor_dp_lane_map(struct nvkm_device *device, u8 lane) |
8f2abc25 | 46 | { |
2a893594 | 47 | static const u8 gm100[] = { 0, 8, 16, 24 }; |
878da15a | 48 | static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ |
2a893594 | 49 | static const u8 g94[] = { 16, 8, 0, 24 }; |
f2c906fc | 50 | if (device->chipset >= 0x110) |
2a893594 | 51 | return gm100[lane]; |
f2c906fc | 52 | if (device->chipset == 0xaf) |
878da15a BS |
53 | return mcp89[lane]; |
54 | return g94[lane]; | |
8f2abc25 BS |
55 | } |
56 | ||
0a0afd28 | 57 | static int |
878da15a | 58 | g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) |
f7960736 | 59 | { |
f2c906fc | 60 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
878da15a | 61 | const u32 loff = g94_sor_loff(outp); |
2fde1f1c | 62 | nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24); |
f7960736 BS |
63 | return 0; |
64 | } | |
65 | ||
1ecee1cd | 66 | int |
878da15a | 67 | g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) |
1ecee1cd | 68 | { |
f2c906fc | 69 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
878da15a BS |
70 | const u32 soff = g94_sor_soff(outp); |
71 | const u32 loff = g94_sor_loff(outp); | |
1ecee1cd BS |
72 | u32 mask = 0, i; |
73 | ||
74 | for (i = 0; i < nr; i++) | |
f2c906fc | 75 | mask |= 1 << (g94_sor_dp_lane_map(device, i) >> 3); |
1ecee1cd | 76 | |
2fde1f1c BS |
77 | nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); |
78 | nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000); | |
3a020b4d BS |
79 | nvkm_msec(device, 2000, |
80 | if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000)) | |
81 | break; | |
82 | ); | |
1ecee1cd BS |
83 | return 0; |
84 | } | |
85 | ||
0a0afd28 | 86 | static int |
878da15a | 87 | g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) |
f7960736 | 88 | { |
f2c906fc | 89 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
878da15a BS |
90 | const u32 soff = g94_sor_soff(outp); |
91 | const u32 loff = g94_sor_loff(outp); | |
f7960736 BS |
92 | u32 dpctrl = 0x00000000; |
93 | u32 clksor = 0x00000000; | |
f7960736 | 94 | |
3b52a1f9 BS |
95 | dpctrl |= ((1 << nr) - 1) << 16; |
96 | if (ef) | |
f7960736 | 97 | dpctrl |= 0x00004000; |
3b52a1f9 | 98 | if (bw > 0x06) |
f7960736 BS |
99 | clksor |= 0x00040000; |
100 | ||
2fde1f1c BS |
101 | nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor); |
102 | nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl); | |
f7960736 BS |
103 | return 0; |
104 | } | |
105 | ||
0a0afd28 | 106 | static int |
878da15a | 107 | g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) |
f7960736 | 108 | { |
f2c906fc | 109 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
2fde1f1c | 110 | struct nvkm_bios *bios = device->bios; |
f2c906fc | 111 | const u32 shift = g94_sor_dp_lane_map(device, ln); |
878da15a | 112 | const u32 loff = g94_sor_loff(outp); |
d7b023d8 | 113 | u32 addr, data[3]; |
f7960736 | 114 | u8 ver, hdr, cnt, len; |
0a0afd28 | 115 | struct nvbios_dpout info; |
f7960736 BS |
116 | struct nvbios_dpcfg ocfg; |
117 | ||
3b52a1f9 BS |
118 | addr = nvbios_dpout_match(bios, outp->base.info.hasht, |
119 | outp->base.info.hashm, | |
f2c906fc | 120 | &ver, &hdr, &cnt, &len, &info); |
f7960736 BS |
121 | if (!addr) |
122 | return -ENODEV; | |
123 | ||
3b52a1f9 | 124 | addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe, |
f2c906fc | 125 | &ver, &hdr, &cnt, &len, &ocfg); |
f7960736 BS |
126 | if (!addr) |
127 | return -EINVAL; | |
128 | ||
2fde1f1c BS |
129 | data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); |
130 | data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); | |
131 | data[2] = nvkm_rd32(device, 0x61c130 + loff); | |
3e1eb5cf BS |
132 | if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) |
133 | data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); | |
2fde1f1c BS |
134 | nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); |
135 | nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); | |
136 | nvkm_wr32(device, 0x61c130 + loff, data[2]); | |
f7960736 BS |
137 | return 0; |
138 | } | |
0a0afd28 | 139 | |
f2c906fc BS |
140 | static const struct nvkm_output_dp_func |
141 | g94_sor_dp_func = { | |
878da15a BS |
142 | .pattern = g94_sor_dp_pattern, |
143 | .lnk_pwr = g94_sor_dp_lnk_pwr, | |
144 | .lnk_ctl = g94_sor_dp_lnk_ctl, | |
145 | .drv_ctl = g94_sor_dp_drv_ctl, | |
b8407c9e | 146 | }; |
f2c906fc BS |
147 | |
148 | int | |
149 | g94_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, | |
150 | struct nvkm_output **poutp) | |
151 | { | |
152 | return nvkm_output_dp_new_(&g94_sor_dp_func, disp, index, dcbE, poutp); | |
153 | } |