[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / sorgf119.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "ior.h"

#include <subdev/timer.h>

void
gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 hoff = head * 0x800;
	nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 | watermark);
}

void
gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 hoff = head * 0x800;
	nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h);
	nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v);
}

void
gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 hoff = 0x800 * head;
	const u32 data = 0x80000000 | (0x00000001 * enable);
	const u32 mask = 0x8000000d;
	nvkm_mask(device, 0x616618 + hoff, mask, data);
	nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000))
			break;
	);
}

void
gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head,
		  u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 hoff = head * 0x800;

	nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
	nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn);
}

void
gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32  loff = nv50_sor_link(sor);
	const u32 shift = sor->func->dp.lanes[ln] * 8;
	u32 data[4];

	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
	data[2] = nvkm_rd32(device, 0x61c130 + loff);
	if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)
		data[2] = (data[2] & ~0x0000ff00) | (pu << 8);
	nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
	nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
	nvkm_wr32(device, 0x61c130 + loff, data[2]);
	data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
	nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
}

void
gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 soff = nv50_ior_base(sor);
	nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
}

int
gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 soff = nv50_ior_base(sor);
	const u32 loff = nv50_sor_link(sor);
	u32 dpctrl = 0x00000000;
	u32 clksor = 0x00000000;

	clksor |= sor->dp.bw << 18;
	dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
	if (sor->dp.mst)
		dpctrl |= 0x40000000;
	if (sor->dp.ef)
		dpctrl |= 0x00004000;

	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
	return 0;
}

void
gf119_sor_clock(struct nvkm_ior *sor)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const int  div = sor->asy.link == 3;
	const u32 soff = nv50_ior_base(sor);
	if (sor->asy.proto == TMDS) {
		/* NFI why, but this sets DP_LINK_BW_2_7 when using TMDS. */
		nvkm_mask(device, 0x612300 + soff, 0x007c0000, 0x0a << 18);
	}
	nvkm_mask(device, 0x612300 + soff, 0x00000707, (div << 8) | div);
}

void
gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
{
	struct nvkm_device *device = sor->disp->engine.subdev.device;
	const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20;
	u32 ctrl = nvkm_rd32(device, 0x640200 + coff);

	state->proto_evo = (ctrl & 0x00000f00) >> 8;
	switch (state->proto_evo) {
	case 0: state->proto = LVDS; state->link = 1; break;
	case 1: state->proto = TMDS; state->link = 1; break;
	case 2: state->proto = TMDS; state->link = 2; break;
	case 5: state->proto = TMDS; state->link = 3; break;
	case 8: state->proto =   DP; state->link = 1; break;
	case 9: state->proto =   DP; state->link = 2; break;
	default:
		state->proto = UNKNOWN;
		break;
	}

	state->head = ctrl & 0x0000000f;
}

int
gf119_sor_new_(const struct nvkm_ior_func *func, struct nvkm_disp *disp, int id)
{
	struct nvkm_device *device = disp->engine.subdev.device;
	if (!(nvkm_rd32(device, 0x612004) & (0x00000100 << id)))
		return 0;
	return nvkm_ior_new_(func, disp, SOR, id);
}

static const struct nvkm_ior_func
gf119_sor = {
	.state = gf119_sor_state,
	.power = nv50_sor_power,
	.clock = gf119_sor_clock,
	.hdmi = {
		.ctrl = gf119_hdmi_ctrl,
	},
	.dp = {
		.lanes = { 2, 1, 0, 3 },
		.links = gf119_sor_dp_links,
		.power = g94_sor_dp_power,
		.pattern = gf119_sor_dp_pattern,
		.drive = gf119_sor_dp_drive,
		.vcpi = gf119_sor_dp_vcpi,
		.audio = gf119_sor_dp_audio,
		.audio_sym = gf119_sor_dp_audio_sym,
		.watermark = gf119_sor_dp_watermark,
	},
	.hda = {
		.hpd = gf119_hda_hpd,
		.eld = gf119_hda_eld,
	},
};

int
gf119_sor_new(struct nvkm_disp *disp, int id)
{
	return gf119_sor_new_(&gf119_sor, disp, id);
}
Commit	Line	Data
6c5a0424 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
78f1ad6f	24	#include "ior.h"
af85389c	25
409b9e54 BS	26	#include <subdev/timer.h>
409b9e54 BS	27
8d7ef84d BS	28	void
	29	gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark)
	30	{
	31	struct nvkm_device *device = sor->disp->engine.subdev.device;
	32	const u32 hoff = head * 0x800;
	33	nvkm_mask(device, 0x616610 + hoff, 0x0800003f, 0x08000000 \| watermark);
	34	}
	35
	36	void
	37	gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
	38	{
	39	struct nvkm_device *device = sor->disp->engine.subdev.device;
	40	const u32 hoff = head * 0x800;
	41	nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, h);
	42	nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v);
	43	}
	44
409b9e54 BS	45	void
	46	gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
	47	{
	48	struct nvkm_device *device = sor->disp->engine.subdev.device;
	49	const u32 hoff = 0x800 * head;
	50	const u32 data = 0x80000000 \| (0x00000001 * enable);
	51	const u32 mask = 0x8000000d;
	52	nvkm_mask(device, 0x616618 + hoff, mask, data);
	53	nvkm_msec(device, 2000,
	54	if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000))
	55	break;
	56	);
	57	}
	58
af85389c	59	void
e8ccc96d BS	60	gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head,
e8ccc96d BS	61	u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
af85389c	62	{
e8ccc96d	63	struct nvkm_device *device = sor->disp->engine.subdev.device;
af85389c BS	64	const u32 hoff = head * 0x800;
	65
	66	nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) \| slot);
	67	nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) \| pbn);
	68	}
6c5a0424	69
7d1fede0 BS	70	void
7d1fede0 BS	71	gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
6c5a0424	72	{
7d1fede0 BS	73	struct nvkm_device *device = sor->disp->engine.subdev.device;
	74	const u32 loff = nv50_sor_link(sor);
	75	const u32 shift = sor->func->dp.lanes[ln] * 8;
	76	u32 data[4];
6c5a0424	77
2fde1f1c BS	78	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
	79	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
	80	data[2] = nvkm_rd32(device, 0x61c130 + loff);
7d1fede0 BS	81	if ((data[2] & 0x0000ff00) < (pu << 8) \|\| ln == 0)
	82	data[2] = (data[2] & ~0x0000ff00) \| (pu << 8);
	83	nvkm_wr32(device, 0x61c118 + loff, data[0] \| (dc << shift));
	84	nvkm_wr32(device, 0x61c120 + loff, data[1] \| (pe << shift));
2fde1f1c BS	85	nvkm_wr32(device, 0x61c130 + loff, data[2]);
2fde1f1c BS	86	data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
7d1fede0	87	nvkm_wr32(device, 0x61c13c + loff, data[3] \| (pc << shift));
6c5a0424	88	}
0a0afd28	89
a1de2b52 BS	90	void
a1de2b52 BS	91	gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
4cddeb9b	92	{
a1de2b52 BS	93	struct nvkm_device *device = sor->disp->engine.subdev.device;
a1de2b52 BS	94	const u32 soff = nv50_ior_base(sor);
af85389c	95	nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
af85389c	96	}
4cddeb9b	97
af85389c	98	int
7dc0bac4	99	gf119_sor_dp_links(struct nvkm_ior sor, struct nvkm_i2c_aux aux)
af85389c	100	{
7dc0bac4 BS	101	struct nvkm_device *device = sor->disp->engine.subdev.device;
	102	const u32 soff = nv50_ior_base(sor);
	103	const u32 loff = nv50_sor_link(sor);
af85389c BS	104	u32 dpctrl = 0x00000000;
	105	u32 clksor = 0x00000000;
	106
7dc0bac4 BS	107	clksor \|= sor->dp.bw << 18;
	108	dpctrl \|= ((1 << sor->dp.nr) - 1) << 16;
	109	if (sor->dp.mst)
af85389c	110	dpctrl \|= 0x40000000;
7dc0bac4	111	if (sor->dp.ef)
af85389c BS	112	dpctrl \|= 0x00004000;
	113
	114	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
	115	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
	116	return 0;
4cddeb9b BS	117	}
4cddeb9b BS	118
8d7ef84d BS	119	void
	120	gf119_sor_clock(struct nvkm_ior *sor)
	121	{
	122	struct nvkm_device *device = sor->disp->engine.subdev.device;
	123	const int div = sor->asy.link == 3;
	124	const u32 soff = nv50_ior_base(sor);
	125	if (sor->asy.proto == TMDS) {
	126	/* NFI why, but this sets DP_LINK_BW_2_7 when using TMDS. */
	127	nvkm_mask(device, 0x612300 + soff, 0x007c0000, 0x0a << 18);
	128	}
	129	nvkm_mask(device, 0x612300 + soff, 0x00000707, (div << 8) \| div);
	130	}
	131
29c0ca73 BS	132	void
	133	gf119_sor_state(struct nvkm_ior sor, struct nvkm_ior_state state)
	134	{
	135	struct nvkm_device *device = sor->disp->engine.subdev.device;
	136	const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20;
	137	u32 ctrl = nvkm_rd32(device, 0x640200 + coff);
	138
	139	state->proto_evo = (ctrl & 0x00000f00) >> 8;
	140	switch (state->proto_evo) {
	141	case 0: state->proto = LVDS; state->link = 1; break;
	142	case 1: state->proto = TMDS; state->link = 1; break;
	143	case 2: state->proto = TMDS; state->link = 2; break;
	144	case 5: state->proto = TMDS; state->link = 3; break;
	145	case 8: state->proto = DP; state->link = 1; break;
	146	case 9: state->proto = DP; state->link = 2; break;
	147	default:
	148	state->proto = UNKNOWN;
	149	break;
	150	}
	151
	152	state->head = ctrl & 0x0000000f;
	153	}
	154
7df1bb87 BS	155	int
	156	gf119_sor_new_(const struct nvkm_ior_func func, struct nvkm_disp disp, int id)
	157	{
	158	struct nvkm_device *device = disp->engine.subdev.device;
	159	if (!(nvkm_rd32(device, 0x612004) & (0x00000100 << id)))
	160	return 0;
	161	return nvkm_ior_new_(func, disp, SOR, id);
	162	}
	163
78f1ad6f BS	164	static const struct nvkm_ior_func
78f1ad6f BS	165	gf119_sor = {
29c0ca73	166	.state = gf119_sor_state,
9c5753bc	167	.power = nv50_sor_power,
8d7ef84d	168	.clock = gf119_sor_clock,
797b2fb8 BS	169	.hdmi = {
	170	.ctrl = gf119_hdmi_ctrl,
	171	},
33378104 BS	172	.dp = {
33378104 BS	173	.lanes = { 2, 1, 0, 3 },
7dc0bac4	174	.links = gf119_sor_dp_links,
a3e81117	175	.power = g94_sor_dp_power,
a1de2b52	176	.pattern = gf119_sor_dp_pattern,
1b5c7ef3	177	.drive = gf119_sor_dp_drive,
e8ccc96d	178	.vcpi = gf119_sor_dp_vcpi,
409b9e54	179	.audio = gf119_sor_dp_audio,
8d7ef84d BS	180	.audio_sym = gf119_sor_dp_audio_sym,
8d7ef84d BS	181	.watermark = gf119_sor_dp_watermark,
409b9e54 BS	182	},
	183	.hda = {
	184	.hpd = gf119_hda_hpd,
	185	.eld = gf119_hda_eld,
33378104	186	},
78f1ad6f BS	187	};
	188
	189	int
	190	gf119_sor_new(struct nvkm_disp *disp, int id)
	191	{
7df1bb87	192	return gf119_sor_new_(&gf119_sor, disp, id);
78f1ad6f	193	}