]>
Commit | Line | Data |
---|---|---|
6c5a0424 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
78f1ad6f | 24 | #include "ior.h" |
6c5a0424 | 25 | #include "nv50.h" |
af85389c BS |
26 | |
27 | void | |
28 | gf119_sor_dp_vcpi(struct nvkm_output_dp *outp, int head, u8 slot, | |
29 | u8 slot_nr, u16 pbn, u16 aligned) | |
30 | { | |
31 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; | |
32 | const u32 hoff = head * 0x800; | |
33 | ||
34 | nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot); | |
35 | nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn); | |
36 | } | |
6c5a0424 | 37 | |
0a0afd28 | 38 | static inline u32 |
2a7909c0 | 39 | gf119_sor_soff(struct nvkm_output_dp *outp) |
0a0afd28 | 40 | { |
3b52a1f9 | 41 | return (ffs(outp->base.info.or) - 1) * 0x800; |
0a0afd28 BS |
42 | } |
43 | ||
44 | static inline u32 | |
2a7909c0 | 45 | gf119_sor_loff(struct nvkm_output_dp *outp) |
0a0afd28 | 46 | { |
2a7909c0 | 47 | return gf119_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; |
0a0afd28 BS |
48 | } |
49 | ||
4691409b | 50 | int |
2a7909c0 | 51 | gf119_sor_dp_drv_ctl(struct nvkm_output_dp *outp, |
878da15a | 52 | int ln, int vs, int pe, int pc) |
6c5a0424 | 53 | { |
f2c906fc | 54 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; |
2fde1f1c | 55 | struct nvkm_bios *bios = device->bios; |
f2c906fc | 56 | const u32 shift = g94_sor_dp_lane_map(device, ln); |
2a7909c0 | 57 | const u32 loff = gf119_sor_loff(outp); |
7a14bc78 | 58 | u32 addr, data[4]; |
6c5a0424 | 59 | u8 ver, hdr, cnt, len; |
0a0afd28 | 60 | struct nvbios_dpout info; |
6c5a0424 BS |
61 | struct nvbios_dpcfg ocfg; |
62 | ||
3b52a1f9 BS |
63 | addr = nvbios_dpout_match(bios, outp->base.info.hasht, |
64 | outp->base.info.hashm, | |
878da15a | 65 | &ver, &hdr, &cnt, &len, &info); |
6c5a0424 BS |
66 | if (!addr) |
67 | return -ENODEV; | |
68 | ||
7a14bc78 | 69 | addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, |
878da15a | 70 | &ver, &hdr, &cnt, &len, &ocfg); |
6c5a0424 BS |
71 | if (!addr) |
72 | return -EINVAL; | |
73 | ||
2fde1f1c BS |
74 | data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); |
75 | data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); | |
76 | data[2] = nvkm_rd32(device, 0x61c130 + loff); | |
3e1eb5cf BS |
77 | if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) |
78 | data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); | |
2fde1f1c BS |
79 | nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); |
80 | nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); | |
81 | nvkm_wr32(device, 0x61c130 + loff, data[2]); | |
82 | data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); | |
83 | nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); | |
6c5a0424 BS |
84 | return 0; |
85 | } | |
0a0afd28 | 86 | |
af85389c BS |
87 | static int |
88 | gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) | |
4cddeb9b BS |
89 | { |
90 | struct nvkm_device *device = outp->base.disp->engine.subdev.device; | |
af85389c BS |
91 | const u32 soff = gf119_sor_soff(outp); |
92 | nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern); | |
93 | return 0; | |
94 | } | |
4cddeb9b | 95 | |
af85389c | 96 | int |
7dc0bac4 | 97 | gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) |
af85389c | 98 | { |
7dc0bac4 BS |
99 | struct nvkm_device *device = sor->disp->engine.subdev.device; |
100 | const u32 soff = nv50_ior_base(sor); | |
101 | const u32 loff = nv50_sor_link(sor); | |
af85389c BS |
102 | u32 dpctrl = 0x00000000; |
103 | u32 clksor = 0x00000000; | |
104 | ||
7dc0bac4 BS |
105 | clksor |= sor->dp.bw << 18; |
106 | dpctrl |= ((1 << sor->dp.nr) - 1) << 16; | |
107 | if (sor->dp.mst) | |
af85389c | 108 | dpctrl |= 0x40000000; |
7dc0bac4 | 109 | if (sor->dp.ef) |
af85389c BS |
110 | dpctrl |= 0x00004000; |
111 | ||
112 | nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); | |
113 | nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); | |
114 | return 0; | |
4cddeb9b BS |
115 | } |
116 | ||
f2c906fc | 117 | static const struct nvkm_output_dp_func |
2a7909c0 BS |
118 | gf119_sor_dp_func = { |
119 | .pattern = gf119_sor_dp_pattern, | |
878da15a | 120 | .lnk_pwr = g94_sor_dp_lnk_pwr, |
2a7909c0 | 121 | .drv_ctl = gf119_sor_dp_drv_ctl, |
4cddeb9b | 122 | .vcpi = gf119_sor_dp_vcpi, |
b8407c9e | 123 | }; |
f2c906fc BS |
124 | |
125 | int | |
2a7909c0 | 126 | gf119_sor_dp_new(struct nvkm_disp *disp, int index, |
f2c906fc BS |
127 | struct dcb_output *dcbE, struct nvkm_output **poutp) |
128 | { | |
2a7909c0 | 129 | return nvkm_output_dp_new_(&gf119_sor_dp_func, disp, index, dcbE, poutp); |
f2c906fc | 130 | } |
78f1ad6f | 131 | |
29c0ca73 BS |
132 | void |
133 | gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) | |
134 | { | |
135 | struct nvkm_device *device = sor->disp->engine.subdev.device; | |
136 | const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20; | |
137 | u32 ctrl = nvkm_rd32(device, 0x640200 + coff); | |
138 | ||
139 | state->proto_evo = (ctrl & 0x00000f00) >> 8; | |
140 | switch (state->proto_evo) { | |
141 | case 0: state->proto = LVDS; state->link = 1; break; | |
142 | case 1: state->proto = TMDS; state->link = 1; break; | |
143 | case 2: state->proto = TMDS; state->link = 2; break; | |
144 | case 5: state->proto = TMDS; state->link = 3; break; | |
145 | case 8: state->proto = DP; state->link = 1; break; | |
146 | case 9: state->proto = DP; state->link = 2; break; | |
147 | default: | |
148 | state->proto = UNKNOWN; | |
149 | break; | |
150 | } | |
151 | ||
152 | state->head = ctrl & 0x0000000f; | |
153 | } | |
154 | ||
78f1ad6f BS |
155 | static const struct nvkm_ior_func |
156 | gf119_sor = { | |
29c0ca73 | 157 | .state = gf119_sor_state, |
9c5753bc | 158 | .power = nv50_sor_power, |
797b2fb8 BS |
159 | .hdmi = { |
160 | .ctrl = gf119_hdmi_ctrl, | |
161 | }, | |
33378104 BS |
162 | .dp = { |
163 | .lanes = { 2, 1, 0, 3 }, | |
7dc0bac4 | 164 | .links = gf119_sor_dp_links, |
33378104 | 165 | }, |
78f1ad6f BS |
166 | }; |
167 | ||
168 | int | |
169 | gf119_sor_new(struct nvkm_disp *disp, int id) | |
170 | { | |
171 | return nvkm_ior_new_(&gf119_sor, disp, SOR, id); | |
172 | } |