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5132f377 | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
5132f377 BS |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
05c7145d | 24 | #include "gk104.h" |
9a65a38c | 25 | #include "changk104.h" |
5132f377 | 26 | |
ebb945a9 | 27 | #include <core/client.h> |
13de7f46 | 28 | #include <core/gpuobj.h> |
358ce601 | 29 | #include <subdev/bar.h> |
e93e198d | 30 | #include <subdev/top.h> |
61570911 | 31 | #include <engine/sw.h> |
5132f377 | 32 | |
05c7145d | 33 | #include <nvif/class.h> |
5132f377 | 34 | |
98ac3f06 BS |
35 | static int |
36 | gk104_fifo_class_get(struct nvkm_fifo *base, int index, | |
37 | const struct nvkm_fifo_chan_oclass **psclass) | |
38 | { | |
39 | struct gk104_fifo *fifo = gk104_fifo(base); | |
40 | int c = 0; | |
41 | ||
42 | while ((*psclass = fifo->func->chan[c])) { | |
43 | if (c++ == index) | |
44 | return 0; | |
45 | } | |
46 | ||
47 | return c; | |
48 | } | |
49 | ||
50 | static void | |
13de7f46 | 51 | gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) |
9a65a38c | 52 | { |
9a65a38c BS |
53 | struct nvkm_device *device = fifo->engine.subdev.device; |
54 | nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); | |
55 | } | |
5132f377 | 56 | |
98ac3f06 | 57 | static void |
13de7f46 | 58 | gk104_fifo_uevent_init(struct nvkm_fifo *fifo) |
9a65a38c | 59 | { |
9a65a38c BS |
60 | struct nvkm_device *device = fifo->engine.subdev.device; |
61 | nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); | |
62 | } | |
ebb945a9 | 63 | |
9a65a38c | 64 | void |
69aa40e2 | 65 | gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl) |
5132f377 | 66 | { |
8f0649b5 | 67 | struct gk104_fifo_chan *chan; |
e5c5e4f5 BS |
68 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
69 | struct nvkm_device *device = subdev->device; | |
69aa40e2 | 70 | struct nvkm_memory *mem; |
8f0649b5 | 71 | int nr = 0; |
a2e435a1 | 72 | int target; |
5132f377 | 73 | |
13de7f46 | 74 | mutex_lock(&subdev->mutex); |
69aa40e2 BS |
75 | mem = fifo->runlist[runl].mem[fifo->runlist[runl].next]; |
76 | fifo->runlist[runl].next = !fifo->runlist[runl].next; | |
5132f377 | 77 | |
69aa40e2 BS |
78 | nvkm_kmap(mem); |
79 | list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { | |
80 | nvkm_wo32(mem, (nr * 8) + 0, chan->base.chid); | |
81 | nvkm_wo32(mem, (nr * 8) + 4, 0x00000000); | |
8f0649b5 | 82 | nr++; |
5132f377 | 83 | } |
69aa40e2 | 84 | nvkm_done(mem); |
5132f377 | 85 | |
d2ee3605 BS |
86 | switch (nvkm_memory_target(mem)) { |
87 | case NVKM_MEM_TARGET_VRAM: target = 0; break; | |
88 | case NVKM_MEM_TARGET_NCOH: target = 3; break; | |
89 | default: | |
90 | WARN_ON(1); | |
91 | return; | |
92 | } | |
a2e435a1 | 93 | |
69aa40e2 | 94 | nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | |
a2e435a1 | 95 | (target << 28)); |
69aa40e2 | 96 | nvkm_wr32(device, 0x002274, (runl << 20) | nr); |
87032e11 | 97 | |
69aa40e2 BS |
98 | if (wait_event_timeout(fifo->runlist[runl].wait, |
99 | !(nvkm_rd32(device, 0x002284 + (runl * 0x08)) | |
100 | & 0x00100000), | |
101 | msecs_to_jiffies(2000)) == 0) | |
102 | nvkm_error(subdev, "runlist %d update timeout\n", runl); | |
13de7f46 | 103 | mutex_unlock(&subdev->mutex); |
5132f377 BS |
104 | } |
105 | ||
386ffd5e BS |
106 | void |
107 | gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) | |
108 | { | |
109 | mutex_lock(&fifo->base.engine.subdev.mutex); | |
110 | list_del_init(&chan->head); | |
111 | mutex_unlock(&fifo->base.engine.subdev.mutex); | |
112 | } | |
113 | ||
114 | void | |
115 | gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan) | |
116 | { | |
117 | mutex_lock(&fifo->base.engine.subdev.mutex); | |
69aa40e2 | 118 | list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan); |
386ffd5e BS |
119 | mutex_unlock(&fifo->base.engine.subdev.mutex); |
120 | } | |
121 | ||
98d1e317 | 122 | static void |
55252da1 | 123 | gk104_fifo_recover_work(struct work_struct *w) |
98d1e317 | 124 | { |
55252da1 | 125 | struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work); |
87744403 | 126 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
6cf813fb | 127 | struct nvkm_engine *engine; |
98d1e317 | 128 | unsigned long flags; |
19f89279 BS |
129 | u32 engm, runm, todo; |
130 | int engn, runl; | |
98d1e317 | 131 | |
6189f1b0 | 132 | spin_lock_irqsave(&fifo->base.lock, flags); |
19f89279 BS |
133 | runm = fifo->recover.runm; |
134 | engm = fifo->recover.engm; | |
135 | fifo->recover.engm = 0; | |
136 | fifo->recover.runm = 0; | |
6189f1b0 | 137 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
98d1e317 | 138 | |
19f89279 | 139 | nvkm_mask(device, 0x002630, runm, runm); |
98d1e317 | 140 | |
19f89279 BS |
141 | for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) { |
142 | if ((engine = fifo->engine[engn].engine)) { | |
6cf813fb BS |
143 | nvkm_subdev_fini(&engine->subdev, false); |
144 | WARN_ON(nvkm_subdev_init(&engine->subdev)); | |
98d1e317 | 145 | } |
98d1e317 BS |
146 | } |
147 | ||
19f89279 BS |
148 | for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl)) |
149 | gk104_fifo_runlist_commit(fifo, runl); | |
150 | ||
151 | nvkm_wr32(device, 0x00262c, runm); | |
152 | nvkm_mask(device, 0x002630, runm, 0x00000000); | |
98d1e317 BS |
153 | } |
154 | ||
155 | static void | |
6189f1b0 | 156 | gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, |
19f89279 | 157 | struct gk104_fifo_chan *chan) |
98d1e317 | 158 | { |
e5c5e4f5 BS |
159 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
160 | struct nvkm_device *device = subdev->device; | |
98d1e317 | 161 | u32 chid = chan->base.chid; |
19f89279 | 162 | int engn; |
98d1e317 | 163 | |
e5c5e4f5 | 164 | nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", |
13de7f46 | 165 | nvkm_subdev_name[engine->subdev.index], chid); |
6ca307b0 | 166 | assert_spin_locked(&fifo->base.lock); |
98d1e317 | 167 | |
87744403 | 168 | nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); |
8f0649b5 BS |
169 | list_del_init(&chan->head); |
170 | chan->killed = true; | |
98d1e317 | 171 | |
19f89279 BS |
172 | for (engn = 0; engn < fifo->engine_nr; engn++) { |
173 | if (fifo->engine[engn].engine == engine) { | |
174 | fifo->recover.engm |= BIT(engn); | |
175 | break; | |
176 | } | |
177 | } | |
178 | ||
179 | fifo->recover.runm |= BIT(chan->runl); | |
55252da1 | 180 | schedule_work(&fifo->recover.work); |
ff9f29ab | 181 | nvkm_fifo_kevent(&fifo->base, chid); |
98d1e317 BS |
182 | } |
183 | ||
05c7145d BS |
184 | static const struct nvkm_enum |
185 | gk104_fifo_bind_reason[] = { | |
56b2f68c BS |
186 | { 0x01, "BIND_NOT_UNBOUND" }, |
187 | { 0x02, "SNOOP_WITHOUT_BAR1" }, | |
188 | { 0x03, "UNBIND_WHILE_RUNNING" }, | |
189 | { 0x05, "INVALID_RUNLIST" }, | |
190 | { 0x06, "INVALID_CTX_TGT" }, | |
191 | { 0x0b, "UNBIND_WHILE_PARKED" }, | |
192 | {} | |
193 | }; | |
194 | ||
195 | static void | |
6189f1b0 | 196 | gk104_fifo_intr_bind(struct gk104_fifo *fifo) |
56b2f68c | 197 | { |
e5c5e4f5 BS |
198 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
199 | struct nvkm_device *device = subdev->device; | |
87744403 | 200 | u32 intr = nvkm_rd32(device, 0x00252c); |
56b2f68c | 201 | u32 code = intr & 0x000000ff; |
e5c5e4f5 BS |
202 | const struct nvkm_enum *en = |
203 | nvkm_enum_find(gk104_fifo_bind_reason, code); | |
56b2f68c | 204 | |
e5c5e4f5 | 205 | nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : ""); |
56b2f68c BS |
206 | } |
207 | ||
05c7145d BS |
208 | static const struct nvkm_enum |
209 | gk104_fifo_sched_reason[] = { | |
e9fb9805 BS |
210 | { 0x0a, "CTXSW_TIMEOUT" }, |
211 | {} | |
212 | }; | |
213 | ||
129dcca7 | 214 | static void |
6189f1b0 | 215 | gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) |
129dcca7 | 216 | { |
87744403 | 217 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
05c7145d | 218 | struct gk104_fifo_chan *chan; |
6ca307b0 | 219 | unsigned long flags; |
129dcca7 BS |
220 | u32 engn; |
221 | ||
6ca307b0 | 222 | spin_lock_irqsave(&fifo->base.lock, flags); |
41e5171b | 223 | for (engn = 0; engn < fifo->engine_nr; engn++) { |
af83a677 BS |
224 | struct nvkm_engine *engine = fifo->engine[engn].engine; |
225 | int runl = fifo->engine[engn].runl; | |
da4ee13c | 226 | u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); |
129dcca7 | 227 | u32 busy = (stat & 0x80000000); |
0689aad7 | 228 | u32 next = (stat & 0x0fff0000) >> 16; |
129dcca7 BS |
229 | u32 chsw = (stat & 0x00008000); |
230 | u32 save = (stat & 0x00004000); | |
231 | u32 load = (stat & 0x00002000); | |
0689aad7 | 232 | u32 prev = (stat & 0x00000fff); |
129dcca7 BS |
233 | u32 chid = load ? next : prev; |
234 | (void)save; | |
235 | ||
af83a677 BS |
236 | if (!busy || !chsw) |
237 | continue; | |
238 | ||
239 | list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { | |
240 | if (chan->base.chid == chid && engine) { | |
241 | gk104_fifo_recover(fifo, engine, chan); | |
242 | break; | |
8f0649b5 | 243 | } |
129dcca7 BS |
244 | } |
245 | } | |
6ca307b0 | 246 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
129dcca7 BS |
247 | } |
248 | ||
885f3ced | 249 | static void |
6189f1b0 | 250 | gk104_fifo_intr_sched(struct gk104_fifo *fifo) |
885f3ced | 251 | { |
e5c5e4f5 BS |
252 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
253 | struct nvkm_device *device = subdev->device; | |
87744403 | 254 | u32 intr = nvkm_rd32(device, 0x00254c); |
885f3ced | 255 | u32 code = intr & 0x000000ff; |
e5c5e4f5 BS |
256 | const struct nvkm_enum *en = |
257 | nvkm_enum_find(gk104_fifo_sched_reason, code); | |
0a7760e0 | 258 | |
e5c5e4f5 | 259 | nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); |
129dcca7 BS |
260 | |
261 | switch (code) { | |
262 | case 0x0a: | |
6189f1b0 | 263 | gk104_fifo_intr_sched_ctxsw(fifo); |
129dcca7 BS |
264 | break; |
265 | default: | |
266 | break; | |
267 | } | |
885f3ced BS |
268 | } |
269 | ||
270 | static void | |
6189f1b0 | 271 | gk104_fifo_intr_chsw(struct gk104_fifo *fifo) |
885f3ced | 272 | { |
e5c5e4f5 BS |
273 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
274 | struct nvkm_device *device = subdev->device; | |
87744403 | 275 | u32 stat = nvkm_rd32(device, 0x00256c); |
e5c5e4f5 | 276 | nvkm_error(subdev, "CHSW_ERROR %08x\n", stat); |
87744403 | 277 | nvkm_wr32(device, 0x00256c, stat); |
885f3ced BS |
278 | } |
279 | ||
280 | static void | |
6189f1b0 | 281 | gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) |
885f3ced | 282 | { |
e5c5e4f5 BS |
283 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
284 | struct nvkm_device *device = subdev->device; | |
87744403 | 285 | u32 stat = nvkm_rd32(device, 0x00259c); |
e5c5e4f5 | 286 | nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); |
885f3ced BS |
287 | } |
288 | ||
e9fb9805 | 289 | static void |
6189f1b0 | 290 | gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) |
5132f377 | 291 | { |
e5c5e4f5 BS |
292 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
293 | struct nvkm_device *device = subdev->device; | |
87744403 BS |
294 | u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); |
295 | u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); | |
296 | u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); | |
297 | u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); | |
885f3ced | 298 | u32 gpc = (stat & 0x1f000000) >> 24; |
5132f377 | 299 | u32 client = (stat & 0x00001f00) >> 8; |
885f3ced BS |
300 | u32 write = (stat & 0x00000080); |
301 | u32 hub = (stat & 0x00000040); | |
302 | u32 reason = (stat & 0x0000000f); | |
05c7145d | 303 | const struct nvkm_enum *er, *eu, *ec; |
6ca307b0 BS |
304 | struct nvkm_engine *engine = NULL; |
305 | struct nvkm_fifo_chan *chan; | |
306 | unsigned long flags; | |
e50d0237 | 307 | char gpcid[8] = "", en[16] = ""; |
885f3ced | 308 | |
91419acf BS |
309 | er = nvkm_enum_find(fifo->func->fault.reason, reason); |
310 | eu = nvkm_enum_find(fifo->func->fault.engine, unit); | |
e5c5e4f5 | 311 | if (hub) { |
91419acf | 312 | ec = nvkm_enum_find(fifo->func->fault.hubclient, client); |
e5c5e4f5 | 313 | } else { |
91419acf | 314 | ec = nvkm_enum_find(fifo->func->fault.gpcclient, client); |
e5c5e4f5 BS |
315 | snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); |
316 | } | |
317 | ||
acdf7d4f | 318 | if (eu && eu->data2) { |
885f3ced | 319 | switch (eu->data2) { |
68f3f702 | 320 | case NVKM_SUBDEV_BAR: |
87744403 | 321 | nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); |
885f3ced | 322 | break; |
68f3f702 | 323 | case NVKM_SUBDEV_INSTMEM: |
87744403 | 324 | nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); |
885f3ced | 325 | break; |
68f3f702 | 326 | case NVKM_ENGINE_IFB: |
87744403 | 327 | nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); |
885f3ced BS |
328 | break; |
329 | default: | |
13de7f46 | 330 | engine = nvkm_device_engine(device, eu->data2); |
885f3ced | 331 | break; |
cb1567c2 | 332 | } |
885f3ced BS |
333 | } |
334 | ||
e50d0237 | 335 | if (eu == NULL) { |
952eb819 | 336 | enum nvkm_devidx engidx = nvkm_top_fault(device, unit); |
e50d0237 BS |
337 | if (engidx < NVKM_SUBDEV_NR) { |
338 | const char *src = nvkm_subdev_name[engidx]; | |
339 | char *dst = en; | |
340 | do { | |
341 | *dst++ = toupper(*src++); | |
342 | } while(*src); | |
343 | engine = nvkm_device_engine(device, engidx); | |
344 | } | |
345 | } else { | |
346 | snprintf(en, sizeof(en), "%s", eu->name); | |
347 | } | |
348 | ||
6ca307b0 BS |
349 | chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); |
350 | ||
e5c5e4f5 BS |
351 | nvkm_error(subdev, |
352 | "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " | |
353 | "reason %02x [%s] on channel %d [%010llx %s]\n", | |
354 | write ? "write" : "read", (u64)vahi << 32 | valo, | |
e50d0237 | 355 | unit, en, client, gpcid, ec ? ec->name : "", |
6ca307b0 | 356 | reason, er ? er->name : "", chan ? chan->chid : -1, |
8f0649b5 BS |
357 | (u64)inst << 12, |
358 | chan ? chan->object.client->name : "unknown"); | |
98d1e317 | 359 | |
6ca307b0 BS |
360 | if (engine && chan) |
361 | gk104_fifo_recover(fifo, engine, (void *)chan); | |
362 | nvkm_fifo_chan_put(&fifo->base, flags, &chan); | |
5132f377 BS |
363 | } |
364 | ||
05c7145d | 365 | static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { |
3d61b967 BS |
366 | { 0x00000001, "MEMREQ" }, |
367 | { 0x00000002, "MEMACK_TIMEOUT" }, | |
368 | { 0x00000004, "MEMACK_EXTRA" }, | |
369 | { 0x00000008, "MEMDAT_TIMEOUT" }, | |
370 | { 0x00000010, "MEMDAT_EXTRA" }, | |
371 | { 0x00000020, "MEMFLUSH" }, | |
372 | { 0x00000040, "MEMOP" }, | |
373 | { 0x00000080, "LBCONNECT" }, | |
374 | { 0x00000100, "LBREQ" }, | |
375 | { 0x00000200, "LBACK_TIMEOUT" }, | |
376 | { 0x00000400, "LBACK_EXTRA" }, | |
377 | { 0x00000800, "LBDAT_TIMEOUT" }, | |
378 | { 0x00001000, "LBDAT_EXTRA" }, | |
379 | { 0x00002000, "GPFIFO" }, | |
380 | { 0x00004000, "GPPTR" }, | |
381 | { 0x00008000, "GPENTRY" }, | |
382 | { 0x00010000, "GPCRC" }, | |
383 | { 0x00020000, "PBPTR" }, | |
384 | { 0x00040000, "PBENTRY" }, | |
385 | { 0x00080000, "PBCRC" }, | |
386 | { 0x00100000, "XBARCONNECT" }, | |
387 | { 0x00200000, "METHOD" }, | |
388 | { 0x00400000, "METHODCRC" }, | |
389 | { 0x00800000, "DEVICE" }, | |
390 | { 0x02000000, "SEMAPHORE" }, | |
391 | { 0x04000000, "ACQUIRE" }, | |
392 | { 0x08000000, "PRI" }, | |
393 | { 0x20000000, "NO_CTXSW_SEG" }, | |
394 | { 0x40000000, "PBSEG" }, | |
395 | { 0x80000000, "SIGNATURE" }, | |
396 | {} | |
397 | }; | |
e2b34fa0 | 398 | |
5132f377 | 399 | static void |
6189f1b0 | 400 | gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) |
5132f377 | 401 | { |
e5c5e4f5 BS |
402 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
403 | struct nvkm_device *device = subdev->device; | |
87744403 BS |
404 | u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000)); |
405 | u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask; | |
406 | u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); | |
407 | u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); | |
408 | u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; | |
ebb945a9 | 409 | u32 subc = (addr & 0x00070000) >> 16; |
5132f377 | 410 | u32 mthd = (addr & 0x00003ffc); |
e2b34fa0 | 411 | u32 show = stat; |
8f0649b5 BS |
412 | struct nvkm_fifo_chan *chan; |
413 | unsigned long flags; | |
e5c5e4f5 | 414 | char msg[128]; |
e2b34fa0 | 415 | |
ebb945a9 | 416 | if (stat & 0x00800000) { |
61570911 BS |
417 | if (device->sw) { |
418 | if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) | |
419 | show &= ~0x00800000; | |
420 | } | |
ebb945a9 BS |
421 | } |
422 | ||
b4c5fc4b BS |
423 | nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); |
424 | ||
e2b34fa0 | 425 | if (show) { |
e5c5e4f5 | 426 | nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show); |
8f0649b5 BS |
427 | chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); |
428 | nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " | |
429 | "subc %d mthd %04x data %08x\n", | |
430 | unit, show, msg, chid, chan ? chan->inst->addr : 0, | |
431 | chan ? chan->object.client->name : "unknown", | |
e5c5e4f5 | 432 | subc, mthd, data); |
8f0649b5 | 433 | nvkm_fifo_chan_put(&fifo->base, flags, &chan); |
e2b34fa0 | 434 | } |
5132f377 | 435 | |
87744403 | 436 | nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); |
5132f377 BS |
437 | } |
438 | ||
05c7145d | 439 | static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { |
70b2cc8e BS |
440 | { 0x00000001, "HCE_RE_ILLEGAL_OP" }, |
441 | { 0x00000002, "HCE_RE_ALIGNB" }, | |
442 | { 0x00000004, "HCE_PRIV" }, | |
443 | { 0x00000008, "HCE_ILLEGAL_MTHD" }, | |
444 | { 0x00000010, "HCE_ILLEGAL_CLASS" }, | |
445 | {} | |
446 | }; | |
447 | ||
448 | static void | |
6189f1b0 | 449 | gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) |
70b2cc8e | 450 | { |
e5c5e4f5 BS |
451 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
452 | struct nvkm_device *device = subdev->device; | |
87744403 BS |
453 | u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000)); |
454 | u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask; | |
455 | u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff; | |
e5c5e4f5 | 456 | char msg[128]; |
70b2cc8e BS |
457 | |
458 | if (stat) { | |
e5c5e4f5 BS |
459 | nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat); |
460 | nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n", | |
461 | unit, stat, msg, chid, | |
462 | nvkm_rd32(device, 0x040150 + (unit * 0x2000)), | |
463 | nvkm_rd32(device, 0x040154 + (unit * 0x2000))); | |
70b2cc8e BS |
464 | } |
465 | ||
87744403 | 466 | nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat); |
70b2cc8e BS |
467 | } |
468 | ||
138b873f | 469 | static void |
6189f1b0 | 470 | gk104_fifo_intr_runlist(struct gk104_fifo *fifo) |
138b873f | 471 | { |
87744403 BS |
472 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
473 | u32 mask = nvkm_rd32(device, 0x002a00); | |
138b873f | 474 | while (mask) { |
69aa40e2 BS |
475 | int runl = __ffs(mask); |
476 | wake_up(&fifo->runlist[runl].wait); | |
477 | nvkm_wr32(device, 0x002a00, 1 << runl); | |
478 | mask &= ~(1 << runl); | |
138b873f BS |
479 | } |
480 | } | |
481 | ||
c074bdbc | 482 | static void |
6189f1b0 | 483 | gk104_fifo_intr_engine(struct gk104_fifo *fifo) |
c074bdbc | 484 | { |
6189f1b0 | 485 | nvkm_fifo_uevent(&fifo->base); |
c074bdbc BS |
486 | } |
487 | ||
98ac3f06 | 488 | static void |
13de7f46 | 489 | gk104_fifo_intr(struct nvkm_fifo *base) |
5132f377 | 490 | { |
13de7f46 BS |
491 | struct gk104_fifo *fifo = gk104_fifo(base); |
492 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; | |
493 | struct nvkm_device *device = subdev->device; | |
87744403 BS |
494 | u32 mask = nvkm_rd32(device, 0x002140); |
495 | u32 stat = nvkm_rd32(device, 0x002100) & mask; | |
5132f377 | 496 | |
e9fb9805 | 497 | if (stat & 0x00000001) { |
6189f1b0 | 498 | gk104_fifo_intr_bind(fifo); |
87744403 | 499 | nvkm_wr32(device, 0x002100, 0x00000001); |
e9fb9805 BS |
500 | stat &= ~0x00000001; |
501 | } | |
502 | ||
503 | if (stat & 0x00000010) { | |
e5c5e4f5 | 504 | nvkm_error(subdev, "PIO_ERROR\n"); |
87744403 | 505 | nvkm_wr32(device, 0x002100, 0x00000010); |
e9fb9805 BS |
506 | stat &= ~0x00000010; |
507 | } | |
508 | ||
5132f377 | 509 | if (stat & 0x00000100) { |
6189f1b0 | 510 | gk104_fifo_intr_sched(fifo); |
87744403 | 511 | nvkm_wr32(device, 0x002100, 0x00000100); |
5132f377 BS |
512 | stat &= ~0x00000100; |
513 | } | |
514 | ||
e9fb9805 | 515 | if (stat & 0x00010000) { |
6189f1b0 | 516 | gk104_fifo_intr_chsw(fifo); |
87744403 | 517 | nvkm_wr32(device, 0x002100, 0x00010000); |
e9fb9805 BS |
518 | stat &= ~0x00010000; |
519 | } | |
520 | ||
521 | if (stat & 0x00800000) { | |
e5c5e4f5 | 522 | nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n"); |
87744403 | 523 | nvkm_wr32(device, 0x002100, 0x00800000); |
e9fb9805 BS |
524 | stat &= ~0x00800000; |
525 | } | |
526 | ||
527 | if (stat & 0x01000000) { | |
e5c5e4f5 | 528 | nvkm_error(subdev, "LB_ERROR\n"); |
87744403 | 529 | nvkm_wr32(device, 0x002100, 0x01000000); |
e9fb9805 BS |
530 | stat &= ~0x01000000; |
531 | } | |
532 | ||
533 | if (stat & 0x08000000) { | |
6189f1b0 | 534 | gk104_fifo_intr_dropped_fault(fifo); |
87744403 | 535 | nvkm_wr32(device, 0x002100, 0x08000000); |
e9fb9805 BS |
536 | stat &= ~0x08000000; |
537 | } | |
538 | ||
5132f377 | 539 | if (stat & 0x10000000) { |
87744403 | 540 | u32 mask = nvkm_rd32(device, 0x00259c); |
885f3ced BS |
541 | while (mask) { |
542 | u32 unit = __ffs(mask); | |
6189f1b0 | 543 | gk104_fifo_intr_fault(fifo, unit); |
87744403 | 544 | nvkm_wr32(device, 0x00259c, (1 << unit)); |
885f3ced | 545 | mask &= ~(1 << unit); |
5132f377 | 546 | } |
5132f377 BS |
547 | stat &= ~0x10000000; |
548 | } | |
549 | ||
550 | if (stat & 0x20000000) { | |
87744403 | 551 | u32 mask = nvkm_rd32(device, 0x0025a0); |
3d61b967 BS |
552 | while (mask) { |
553 | u32 unit = __ffs(mask); | |
6189f1b0 BS |
554 | gk104_fifo_intr_pbdma_0(fifo, unit); |
555 | gk104_fifo_intr_pbdma_1(fifo, unit); | |
87744403 | 556 | nvkm_wr32(device, 0x0025a0, (1 << unit)); |
3d61b967 | 557 | mask &= ~(1 << unit); |
5132f377 | 558 | } |
5132f377 BS |
559 | stat &= ~0x20000000; |
560 | } | |
561 | ||
562 | if (stat & 0x40000000) { | |
6189f1b0 | 563 | gk104_fifo_intr_runlist(fifo); |
5132f377 BS |
564 | stat &= ~0x40000000; |
565 | } | |
566 | ||
9bd2ddba | 567 | if (stat & 0x80000000) { |
87744403 | 568 | nvkm_wr32(device, 0x002100, 0x80000000); |
6189f1b0 | 569 | gk104_fifo_intr_engine(fifo); |
9bd2ddba BS |
570 | stat &= ~0x80000000; |
571 | } | |
572 | ||
5132f377 | 573 | if (stat) { |
e5c5e4f5 | 574 | nvkm_error(subdev, "INTR %08x\n", stat); |
87744403 BS |
575 | nvkm_mask(device, 0x002140, stat, 0x00000000); |
576 | nvkm_wr32(device, 0x002100, stat); | |
5132f377 BS |
577 | } |
578 | } | |
c420b2dc | 579 | |
98ac3f06 | 580 | static void |
13de7f46 BS |
581 | gk104_fifo_fini(struct nvkm_fifo *base) |
582 | { | |
583 | struct gk104_fifo *fifo = gk104_fifo(base); | |
584 | struct nvkm_device *device = fifo->base.engine.subdev.device; | |
55252da1 | 585 | flush_work(&fifo->recover.work); |
13de7f46 BS |
586 | /* allow mmu fault interrupts, even when we're not using fifo */ |
587 | nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); | |
588 | } | |
589 | ||
98ac3f06 | 590 | static int |
13de7f46 | 591 | gk104_fifo_oneinit(struct nvkm_fifo *base) |
649ec925 | 592 | { |
13de7f46 | 593 | struct gk104_fifo *fifo = gk104_fifo(base); |
6d39b83f BS |
594 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
595 | struct nvkm_device *device = subdev->device; | |
e93e198d BS |
596 | int engn, runl, pbid, ret, i, j; |
597 | enum nvkm_devidx engidx; | |
41e5171b | 598 | u32 *map; |
649ec925 | 599 | |
6d39b83f BS |
600 | /* Determine number of PBDMAs by checking valid enable bits. */ |
601 | nvkm_wr32(device, 0x000204, 0xffffffff); | |
602 | fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204)); | |
603 | nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr); | |
604 | ||
41e5171b BS |
605 | /* Read PBDMA->runlist(s) mapping from HW. */ |
606 | if (!(map = kzalloc(sizeof(*map) * fifo->pbdma_nr, GFP_KERNEL))) | |
607 | return -ENOMEM; | |
608 | ||
609 | for (i = 0; i < fifo->pbdma_nr; i++) | |
610 | map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); | |
611 | ||
e93e198d BS |
612 | /* Determine runlist configuration from topology device info. */ |
613 | i = 0; | |
952eb819 | 614 | while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) { |
41e5171b | 615 | /* Determine which PBDMA handles requests for this engine. */ |
e93e198d | 616 | for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { |
41e5171b BS |
617 | if (map[j] & (1 << runl)) { |
618 | pbid = j; | |
619 | break; | |
620 | } | |
621 | } | |
622 | ||
1fe8c02f BS |
623 | nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n", |
624 | engn, runl, pbid, nvkm_subdev_name[engidx]); | |
41e5171b | 625 | |
e93e198d BS |
626 | fifo->engine[engn].engine = nvkm_device_engine(device, engidx); |
627 | fifo->engine[engn].runl = runl; | |
628 | fifo->engine[engn].pbid = pbid; | |
629 | fifo->engine_nr = max(fifo->engine_nr, engn + 1); | |
630 | fifo->runlist[runl].engm |= 1 << engn; | |
631 | fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); | |
41e5171b BS |
632 | } |
633 | ||
634 | kfree(map); | |
635 | ||
636 | for (i = 0; i < fifo->runlist_nr; i++) { | |
13de7f46 BS |
637 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, |
638 | 0x8000, 0x1000, false, | |
69aa40e2 | 639 | &fifo->runlist[i].mem[0]); |
13de7f46 BS |
640 | if (ret) |
641 | return ret; | |
642 | ||
643 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, | |
644 | 0x8000, 0x1000, false, | |
69aa40e2 | 645 | &fifo->runlist[i].mem[1]); |
13de7f46 BS |
646 | if (ret) |
647 | return ret; | |
648 | ||
69aa40e2 BS |
649 | init_waitqueue_head(&fifo->runlist[i].wait); |
650 | INIT_LIST_HEAD(&fifo->runlist[i].chan); | |
13de7f46 BS |
651 | } |
652 | ||
653 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, | |
654 | fifo->base.nr * 0x200, 0x1000, true, | |
655 | &fifo->user.mem); | |
649ec925 BS |
656 | if (ret) |
657 | return ret; | |
658 | ||
13de7f46 BS |
659 | ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12, |
660 | &fifo->user.bar); | |
661 | if (ret) | |
662 | return ret; | |
663 | ||
664 | nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); | |
649ec925 BS |
665 | return 0; |
666 | } | |
667 | ||
98ac3f06 | 668 | static void |
13de7f46 | 669 | gk104_fifo_init(struct nvkm_fifo *base) |
a763951a | 670 | { |
13de7f46 | 671 | struct gk104_fifo *fifo = gk104_fifo(base); |
6d39b83f | 672 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
13de7f46 | 673 | int i; |
a763951a | 674 | |
6d39b83f BS |
675 | /* Enable PBDMAs. */ |
676 | nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1); | |
a763951a | 677 | |
39b05542 | 678 | /* PBDMA[n] */ |
6d39b83f | 679 | for (i = 0; i < fifo->pbdma_nr; i++) { |
87744403 BS |
680 | nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
681 | nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ | |
682 | nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ | |
a763951a BS |
683 | } |
684 | ||
70b2cc8e | 685 | /* PBDMA[n].HCE */ |
6d39b83f | 686 | for (i = 0; i < fifo->pbdma_nr; i++) { |
87744403 BS |
687 | nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */ |
688 | nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ | |
70b2cc8e BS |
689 | } |
690 | ||
87744403 | 691 | nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); |
a763951a | 692 | |
87744403 BS |
693 | nvkm_wr32(device, 0x002100, 0xffffffff); |
694 | nvkm_wr32(device, 0x002140, 0x7fffffff); | |
a763951a BS |
695 | } |
696 | ||
98ac3f06 | 697 | static void * |
13de7f46 | 698 | gk104_fifo_dtor(struct nvkm_fifo *base) |
a763951a | 699 | { |
13de7f46 | 700 | struct gk104_fifo *fifo = gk104_fifo(base); |
a763951a BS |
701 | int i; |
702 | ||
358ce601 BS |
703 | nvkm_vm_put(&fifo->user.bar); |
704 | nvkm_memory_del(&fifo->user.mem); | |
a763951a | 705 | |
41e5171b | 706 | for (i = 0; i < fifo->runlist_nr; i++) { |
69aa40e2 BS |
707 | nvkm_memory_del(&fifo->runlist[i].mem[1]); |
708 | nvkm_memory_del(&fifo->runlist[i].mem[0]); | |
a763951a BS |
709 | } |
710 | ||
13de7f46 BS |
711 | return fifo; |
712 | } | |
713 | ||
98ac3f06 BS |
714 | static const struct nvkm_fifo_func |
715 | gk104_fifo_ = { | |
716 | .dtor = gk104_fifo_dtor, | |
717 | .oneinit = gk104_fifo_oneinit, | |
718 | .init = gk104_fifo_init, | |
719 | .fini = gk104_fifo_fini, | |
720 | .intr = gk104_fifo_intr, | |
721 | .uevent_init = gk104_fifo_uevent_init, | |
722 | .uevent_fini = gk104_fifo_uevent_fini, | |
723 | .class_get = gk104_fifo_class_get, | |
724 | }; | |
725 | ||
13de7f46 | 726 | int |
98ac3f06 | 727 | gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, |
13de7f46 BS |
728 | int index, int nr, struct nvkm_fifo **pfifo) |
729 | { | |
730 | struct gk104_fifo *fifo; | |
731 | ||
732 | if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) | |
733 | return -ENOMEM; | |
98ac3f06 | 734 | fifo->func = func; |
55252da1 | 735 | INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); |
13de7f46 BS |
736 | *pfifo = &fifo->base; |
737 | ||
98ac3f06 | 738 | return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); |
a763951a BS |
739 | } |
740 | ||
91419acf BS |
741 | const struct nvkm_enum |
742 | gk104_fifo_fault_engine[] = { | |
743 | { 0x00, "GR", NULL, NVKM_ENGINE_GR }, | |
289e0827 BS |
744 | { 0x01, "DISPLAY" }, |
745 | { 0x02, "CAPTURE" }, | |
91419acf BS |
746 | { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, |
747 | { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, | |
289e0827 BS |
748 | { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, |
749 | { 0x06, "SCHED" }, | |
ec884f74 BS |
750 | { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO }, |
751 | { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO }, | |
752 | { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO }, | |
753 | { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO }, | |
754 | { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO }, | |
755 | { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO }, | |
756 | { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO }, | |
757 | { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO }, | |
289e0827 | 758 | { 0x0f, "HOSTSR" }, |
91419acf BS |
759 | { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, |
760 | { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, | |
761 | { 0x13, "PERF" }, | |
762 | { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, | |
763 | { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, | |
764 | { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, | |
765 | { 0x17, "PMU" }, | |
289e0827 | 766 | { 0x18, "PTP" }, |
91419acf BS |
767 | { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, |
768 | { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, | |
769 | {} | |
770 | }; | |
771 | ||
772 | const struct nvkm_enum | |
773 | gk104_fifo_fault_reason[] = { | |
774 | { 0x00, "PDE" }, | |
775 | { 0x01, "PDE_SIZE" }, | |
776 | { 0x02, "PTE" }, | |
777 | { 0x03, "VA_LIMIT_VIOLATION" }, | |
778 | { 0x04, "UNBOUND_INST_BLOCK" }, | |
779 | { 0x05, "PRIV_VIOLATION" }, | |
780 | { 0x06, "RO_VIOLATION" }, | |
781 | { 0x07, "WO_VIOLATION" }, | |
782 | { 0x08, "PITCH_MASK_VIOLATION" }, | |
783 | { 0x09, "WORK_CREATION" }, | |
784 | { 0x0a, "UNSUPPORTED_APERTURE" }, | |
785 | { 0x0b, "COMPRESSION_FAILURE" }, | |
786 | { 0x0c, "UNSUPPORTED_KIND" }, | |
787 | { 0x0d, "REGION_VIOLATION" }, | |
788 | { 0x0e, "BOTH_PTES_VALID" }, | |
789 | { 0x0f, "INFO_TYPE_POISONED" }, | |
790 | {} | |
791 | }; | |
792 | ||
793 | const struct nvkm_enum | |
794 | gk104_fifo_fault_hubclient[] = { | |
795 | { 0x00, "VIP" }, | |
796 | { 0x01, "CE0" }, | |
797 | { 0x02, "CE1" }, | |
798 | { 0x03, "DNISO" }, | |
799 | { 0x04, "FE" }, | |
800 | { 0x05, "FECS" }, | |
801 | { 0x06, "HOST" }, | |
802 | { 0x07, "HOST_CPU" }, | |
803 | { 0x08, "HOST_CPU_NB" }, | |
804 | { 0x09, "ISO" }, | |
805 | { 0x0a, "MMU" }, | |
806 | { 0x0b, "MSPDEC" }, | |
807 | { 0x0c, "MSPPP" }, | |
808 | { 0x0d, "MSVLD" }, | |
809 | { 0x0e, "NISO" }, | |
810 | { 0x0f, "P2P" }, | |
811 | { 0x10, "PD" }, | |
812 | { 0x11, "PERF" }, | |
813 | { 0x12, "PMU" }, | |
814 | { 0x13, "RASTERTWOD" }, | |
815 | { 0x14, "SCC" }, | |
816 | { 0x15, "SCC_NB" }, | |
817 | { 0x16, "SEC" }, | |
818 | { 0x17, "SSYNC" }, | |
819 | { 0x18, "GR_CE" }, | |
820 | { 0x19, "CE2" }, | |
821 | { 0x1a, "XV" }, | |
822 | { 0x1b, "MMU_NB" }, | |
823 | { 0x1c, "MSENC" }, | |
824 | { 0x1d, "DFALCON" }, | |
825 | { 0x1e, "SKED" }, | |
826 | { 0x1f, "AFALCON" }, | |
827 | {} | |
828 | }; | |
829 | ||
830 | const struct nvkm_enum | |
831 | gk104_fifo_fault_gpcclient[] = { | |
832 | { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, | |
833 | { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, | |
834 | { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, | |
835 | { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, | |
836 | { 0x0c, "RAST" }, | |
837 | { 0x0d, "GCC" }, | |
838 | { 0x0e, "GPCCS" }, | |
839 | { 0x0f, "PROP_0" }, | |
840 | { 0x10, "PROP_1" }, | |
841 | { 0x11, "PROP_2" }, | |
842 | { 0x12, "PROP_3" }, | |
843 | { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, | |
844 | { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, | |
845 | { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, | |
846 | { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, | |
847 | { 0x1f, "GPM" }, | |
848 | { 0x20, "LTP_UTLB_0" }, | |
849 | { 0x21, "LTP_UTLB_1" }, | |
850 | { 0x22, "LTP_UTLB_2" }, | |
851 | { 0x23, "LTP_UTLB_3" }, | |
852 | { 0x24, "GPC_RGG_UTLB" }, | |
853 | {} | |
854 | }; | |
855 | ||
98ac3f06 | 856 | static const struct gk104_fifo_func |
13de7f46 | 857 | gk104_fifo = { |
91419acf BS |
858 | .fault.engine = gk104_fifo_fault_engine, |
859 | .fault.reason = gk104_fifo_fault_reason, | |
860 | .fault.hubclient = gk104_fifo_fault_hubclient, | |
861 | .fault.gpcclient = gk104_fifo_fault_gpcclient, | |
8f0649b5 BS |
862 | .chan = { |
863 | &gk104_fifo_gpfifo_oclass, | |
864 | NULL | |
865 | }, | |
866 | }; | |
867 | ||
a763951a | 868 | int |
13de7f46 | 869 | gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) |
ebb945a9 | 870 | { |
13de7f46 | 871 | return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo); |
ebb945a9 | 872 | } |