[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / fifo / gpfifogv100.c

/*
 * Copyright 2018 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#include "changk104.h"
#include "cgrp.h"

#include <core/client.h>
#include <core/gpuobj.h>

#include <nvif/clc36f.h>
#include <nvif/unpack.h>

static u32
gv100_fifo_gpfifo_submit_token(struct nvkm_fifo_chan *chan)
{
	return chan->chid;
}

static int
gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid)
{
	struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev;
	struct nvkm_device *device = subdev->device;
	const u32 mask = ce ? 0x00020000 : 0x00010000;
	const u32 data = valid ? mask : 0x00000000;
	int ret;

	/* Block runlist to prevent the channel from being rescheduled. */
	mutex_lock(&subdev->mutex);
	nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl));

	/* Preempt the channel. */
	ret = gk104_fifo_gpfifo_kick_locked(chan);
	if (ret == 0) {
		/* Update engine context validity. */
		nvkm_kmap(chan->base.inst);
		nvkm_mo32(chan->base.inst, 0x0ac, mask, data);
		nvkm_done(chan->base.inst);
	}

	/* Resume runlist. */
	nvkm_mask(device, 0x002630, BIT(chan->runl), 0);
	mutex_unlock(&subdev->mutex);
	return ret;
}

int
gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
			      struct nvkm_engine *engine, bool suspend)
{
	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
	struct nvkm_gpuobj *inst = chan->base.inst;
	int ret;

	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
	    engine->subdev.index <= NVKM_ENGINE_CE_LAST)
		return gk104_fifo_gpfifo_kick(chan);

	ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
	if (ret && suspend)
		return ret;

	nvkm_kmap(inst);
	nvkm_wo32(inst, 0x0210, 0x00000000);
	nvkm_wo32(inst, 0x0214, 0x00000000);
	nvkm_done(inst);
	return ret;
}

int
gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
			      struct nvkm_engine *engine)
{
	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
	struct nvkm_gpuobj *inst = chan->base.inst;
	u64 addr;

	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
	    engine->subdev.index <= NVKM_ENGINE_CE_LAST)
		return 0;

	addr = chan->engn[engine->subdev.index].vma->addr;
	nvkm_kmap(inst);
	nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004);
	nvkm_wo32(inst, 0x214, upper_32_bits(addr));
	nvkm_done(inst);

	return gv100_fifo_gpfifo_engine_valid(chan, false, true);
}

static const struct nvkm_fifo_chan_func
gv100_fifo_gpfifo = {
	.dtor = gk104_fifo_gpfifo_dtor,
	.init = gk104_fifo_gpfifo_init,
	.fini = gk104_fifo_gpfifo_fini,
	.ntfy = gf100_fifo_chan_ntfy,
	.engine_ctor = gk104_fifo_gpfifo_engine_ctor,
	.engine_dtor = gk104_fifo_gpfifo_engine_dtor,
	.engine_init = gv100_fifo_gpfifo_engine_init,
	.engine_fini = gv100_fifo_gpfifo_engine_fini,
	.submit_token = gv100_fifo_gpfifo_submit_token,
};

int
gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
		       struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
		       u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv,
		       u32 *token, const struct nvkm_oclass *oclass,
		       struct nvkm_object **pobject)
{
	struct nvkm_device *device = fifo->base.engine.subdev.device;
	struct gk104_fifo_chan *chan;
	int runlist = ffs(*runlists) -1, ret, i;
	unsigned long engm;
	u64 subdevs = 0;
	u64 usermem, mthd;
	u32 size;

	if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
		return -EINVAL;
	*runlists = BIT_ULL(runlist);

	engm = fifo->runlist[runlist].engm;
	for_each_set_bit(i, &engm, fifo->engine_nr) {
		if (fifo->engine[i].engine)
			subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
	}

	/* Allocate the channel. */
	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
		return -ENOMEM;
	*pobject = &chan->base.object;
	chan->fifo = fifo;
	chan->runl = runlist;
	INIT_LIST_HEAD(&chan->head);

	ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm,
				  0, subdevs, 1, fifo->user.bar->addr, 0x200,
				  oclass, &chan->base);
	if (ret)
		return ret;

	*chid = chan->base.chid;
	*inst = chan->base.inst->addr;
	*token = chan->base.func->submit_token(&chan->base);

	/* Hack to support GPUs where even individual channels should be
	 * part of a channel group.
	 */
	if (fifo->func->cgrp_force) {
		if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
			return -ENOMEM;
		chan->cgrp->id = chan->base.chid;
		INIT_LIST_HEAD(&chan->cgrp->head);
		INIT_LIST_HEAD(&chan->cgrp->chan);
		chan->cgrp->chan_nr = 0;
	}

	/* Clear channel control registers. */
	usermem = chan->base.chid * 0x200;
	ilength = order_base_2(ilength / 8);

	nvkm_kmap(fifo->user.mem);
	for (i = 0; i < 0x200; i += 4)
		nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
	nvkm_done(fifo->user.mem);
	usermem = nvkm_memory_addr(fifo->user.mem) + usermem;

	/* Allocate fault method buffer (magics come from nvgpu). */
	size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
	size = 27 * 5 * (((9 + 1 + 3) * hweight32(size)) + 2);
	size = roundup(size, PAGE_SIZE);

	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, true,
			      &chan->mthd);
	if (ret)
		return ret;

	mthd = nvkm_memory_bar2(chan->mthd);
	if (mthd == ~0ULL)
		return -EFAULT;

	/* RAMFC */
	nvkm_kmap(chan->base.inst);
	nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
	nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
	nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
	nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
	nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset));
	nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) |
					  (ilength << 16));
	nvkm_wo32(chan->base.inst, 0x084, 0x20400000);
	nvkm_wo32(chan->base.inst, 0x094, 0x30000001);
	nvkm_wo32(chan->base.inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
	nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid);
	nvkm_wo32(chan->base.inst, 0x0f4, 0x00001000);
	nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080);
	nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
	nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(mthd));
	nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd));
	nvkm_done(chan->base.inst);
	return gv100_fifo_gpfifo_engine_valid(chan, true, true);
}

int
gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass,
		      void *data, u32 size, struct nvkm_object **pobject)
{
	struct nvkm_object *parent = oclass->parent;
	union {
		struct volta_channel_gpfifo_a_v0 v0;
	} *args = data;
	int ret = -ENOSYS;

	nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
		nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
				   "ioffset %016llx ilength %08x "
				   "runlist %016llx priv %d\n",
			   args->v0.version, args->v0.vmm, args->v0.ioffset,
			   args->v0.ilength, args->v0.runlist, args->v0.priv);
		if (args->v0.priv && !oclass->client->super)
			return -EINVAL;
		return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo,
					      &args->v0.runlist,
					      &args->v0.chid,
					       args->v0.vmm,
					       args->v0.ioffset,
					       args->v0.ilength,
					      &args->v0.inst,
					       args->v0.priv,
					      &args->v0.token,
					      oclass, pobject);
	}

	return ret;
}
Commit	Line	Data
37e1c45a BS	1	/*
	2	* Copyright 2018 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "changk104.h"
	23	#include "cgrp.h"
	24
	25	#include <core/client.h>
	26	#include <core/gpuobj.h>
	27
9d24907c	28	#include <nvif/clc36f.h>
37e1c45a BS	29	#include <nvif/unpack.h>
37e1c45a BS	30
9d24907c BS	31	static u32
	32	gv100_fifo_gpfifo_submit_token(struct nvkm_fifo_chan *chan)
	33	{
	34	return chan->chid;
	35	}
	36
37e1c45a BS	37	static int
	38	gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid)
	39	{
	40	struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev;
	41	struct nvkm_device *device = subdev->device;
	42	const u32 mask = ce ? 0x00020000 : 0x00010000;
	43	const u32 data = valid ? mask : 0x00000000;
	44	int ret;
	45
	46	/* Block runlist to prevent the channel from being rescheduled. */
	47	mutex_lock(&subdev->mutex);
	48	nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl));
	49
	50	/* Preempt the channel. */
	51	ret = gk104_fifo_gpfifo_kick_locked(chan);
	52	if (ret == 0) {
	53	/* Update engine context validity. */
	54	nvkm_kmap(chan->base.inst);
	55	nvkm_mo32(chan->base.inst, 0x0ac, mask, data);
	56	nvkm_done(chan->base.inst);
	57	}
	58
	59	/* Resume runlist. */
	60	nvkm_mask(device, 0x002630, BIT(chan->runl), 0);
	61	mutex_unlock(&subdev->mutex);
	62	return ret;
	63	}
	64
641d0b30	65	int
37e1c45a BS	66	gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
	67	struct nvkm_engine *engine, bool suspend)
	68	{
	69	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
	70	struct nvkm_gpuobj *inst = chan->base.inst;
	71	int ret;
	72
	73	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
	74	engine->subdev.index <= NVKM_ENGINE_CE_LAST)
	75	return gk104_fifo_gpfifo_kick(chan);
	76
	77	ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
	78	if (ret && suspend)
	79	return ret;
	80
	81	nvkm_kmap(inst);
	82	nvkm_wo32(inst, 0x0210, 0x00000000);
	83	nvkm_wo32(inst, 0x0214, 0x00000000);
	84	nvkm_done(inst);
	85	return ret;
	86	}
	87
641d0b30	88	int
37e1c45a BS	89	gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
	90	struct nvkm_engine *engine)
	91	{
	92	struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
	93	struct nvkm_gpuobj *inst = chan->base.inst;
	94	u64 addr;
	95
	96	if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
	97	engine->subdev.index <= NVKM_ENGINE_CE_LAST)
	98	return 0;
	99
	100	addr = chan->engn[engine->subdev.index].vma->addr;
	101	nvkm_kmap(inst);
	102	nvkm_wo32(inst, 0x210, lower_32_bits(addr) \| 0x00000004);
	103	nvkm_wo32(inst, 0x214, upper_32_bits(addr));
	104	nvkm_done(inst);
	105
	106	return gv100_fifo_gpfifo_engine_valid(chan, false, true);
	107	}
	108
9d24907c BS	109	static const struct nvkm_fifo_chan_func
9d24907c BS	110	gv100_fifo_gpfifo = {
37e1c45a BS	111	.dtor = gk104_fifo_gpfifo_dtor,
	112	.init = gk104_fifo_gpfifo_init,
	113	.fini = gk104_fifo_gpfifo_fini,
	114	.ntfy = gf100_fifo_chan_ntfy,
	115	.engine_ctor = gk104_fifo_gpfifo_engine_ctor,
	116	.engine_dtor = gk104_fifo_gpfifo_engine_dtor,
	117	.engine_init = gv100_fifo_gpfifo_engine_init,
	118	.engine_fini = gv100_fifo_gpfifo_engine_fini,
9d24907c	119	.submit_token = gv100_fifo_gpfifo_submit_token,
37e1c45a BS	120	};
37e1c45a BS	121
9d24907c BS	122	int
	123	gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func *func,
	124	struct gk104_fifo fifo, u64 runlists, u16 *chid,
85532bd9	125	u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv,
9d24907c	126	u32 token, const struct nvkm_oclass oclass,
37e1c45a BS	127	struct nvkm_object **pobject)
37e1c45a BS	128	{
a98a3c52	129	struct nvkm_device *device = fifo->base.engine.subdev.device;
37e1c45a BS	130	struct gk104_fifo_chan *chan;
	131	int runlist = ffs(*runlists) -1, ret, i;
	132	unsigned long engm;
	133	u64 subdevs = 0;
a98a3c52 BS	134	u64 usermem, mthd;
a98a3c52 BS	135	u32 size;
37e1c45a BS	136
	137	if (!vmm \|\| runlist < 0 \|\| runlist >= fifo->runlist_nr)
	138	return -EINVAL;
	139	*runlists = BIT_ULL(runlist);
	140
	141	engm = fifo->runlist[runlist].engm;
	142	for_each_set_bit(i, &engm, fifo->engine_nr) {
	143	if (fifo->engine[i].engine)
	144	subdevs \|= BIT_ULL(fifo->engine[i].engine->subdev.index);
	145	}
	146
	147	/* Allocate the channel. */
	148	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
	149	return -ENOMEM;
	150	*pobject = &chan->base.object;
	151	chan->fifo = fifo;
	152	chan->runl = runlist;
	153	INIT_LIST_HEAD(&chan->head);
	154
9d24907c BS	155	ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm,
9d24907c BS	156	0, subdevs, 1, fifo->user.bar->addr, 0x200,
37e1c45a BS	157	oclass, &chan->base);
	158	if (ret)
	159	return ret;
	160
	161	*chid = chan->base.chid;
86b442d7	162	*inst = chan->base.inst->addr;
9d24907c	163	*token = chan->base.func->submit_token(&chan->base);
37e1c45a BS	164
	165	/* Hack to support GPUs where even individual channels should be
	166	* part of a channel group.
	167	*/
	168	if (fifo->func->cgrp_force) {
	169	if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
	170	return -ENOMEM;
	171	chan->cgrp->id = chan->base.chid;
	172	INIT_LIST_HEAD(&chan->cgrp->head);
	173	INIT_LIST_HEAD(&chan->cgrp->chan);
	174	chan->cgrp->chan_nr = 0;
	175	}
	176
	177	/* Clear channel control registers. */
	178	usermem = chan->base.chid * 0x200;
	179	ilength = order_base_2(ilength / 8);
	180
	181	nvkm_kmap(fifo->user.mem);
	182	for (i = 0; i < 0x200; i += 4)
	183	nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
	184	nvkm_done(fifo->user.mem);
	185	usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
	186
a98a3c52 BS	187	/* Allocate fault method buffer (magics come from nvgpu). */
	188	size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
	189	size = 27 * 5 * (((9 + 1 + 3) * hweight32(size)) + 2);
	190	size = roundup(size, PAGE_SIZE);
	191
	192	ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, true,
	193	&chan->mthd);
	194	if (ret)
	195	return ret;
	196
	197	mthd = nvkm_memory_bar2(chan->mthd);
	198	if (mthd == ~0ULL)
	199	return -EFAULT;
	200
37e1c45a BS	201	/* RAMFC */
	202	nvkm_kmap(chan->base.inst);
	203	nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
	204	nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
	205	nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
	206	nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
	207	nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset));
	208	nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) \|
	209	(ilength << 16));
	210	nvkm_wo32(chan->base.inst, 0x084, 0x20400000);
	211	nvkm_wo32(chan->base.inst, 0x094, 0x30000001);
85532bd9	212	nvkm_wo32(chan->base.inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
37e1c45a	213	nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid);
85532bd9	214	nvkm_wo32(chan->base.inst, 0x0f4, 0x00001000);
37e1c45a BS	215	nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080);
37e1c45a BS	216	nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
a98a3c52 BS	217	nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(mthd));
a98a3c52 BS	218	nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd));
37e1c45a BS	219	nvkm_done(chan->base.inst);
	220	return gv100_fifo_gpfifo_engine_valid(chan, true, true);
	221	}
	222
	223	int
	224	gv100_fifo_gpfifo_new(struct gk104_fifo fifo, const struct nvkm_oclass oclass,
	225	void data, u32 size, struct nvkm_object *pobject)
	226	{
	227	struct nvkm_object *parent = oclass->parent;
	228	union {
9d24907c	229	struct volta_channel_gpfifo_a_v0 v0;
37e1c45a BS	230	} *args = data;
	231	int ret = -ENOSYS;
	232
	233	nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
	234	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
	235	nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
	236	"ioffset %016llx ilength %08x "
85532bd9	237	"runlist %016llx priv %d\n",
37e1c45a	238	args->v0.version, args->v0.vmm, args->v0.ioffset,
85532bd9 BS	239	args->v0.ilength, args->v0.runlist, args->v0.priv);
	240	if (args->v0.priv && !oclass->client->super)
	241	return -EINVAL;
9d24907c	242	return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo,
37e1c45a BS	243	&args->v0.runlist,
	244	&args->v0.chid,
	245	args->v0.vmm,
	246	args->v0.ioffset,
	247	args->v0.ilength,
86b442d7	248	&args->v0.inst,
85532bd9	249	args->v0.priv,
9d24907c	250	&args->v0.token,
37e1c45a BS	251	oclass, pobject);
	252	}
	253
	254	return ret;
	255	}