]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c
drm/nouveau/disp: power down unused DP links during init
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / fifo / gpfifonv50.c
CommitLineData
9a65a38c
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "channv50.h"
25
26#include <core/client.h>
27#include <core/ramht.h>
28
29#include <nvif/class.h>
8ed1730c 30#include <nvif/cl506f.h>
9a65a38c
BS
31#include <nvif/unpack.h>
32
33static int
8f0649b5
BS
34nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
35 void *data, u32 size, struct nvkm_object **pobject)
9a65a38c 36{
8f0649b5 37 struct nvkm_object *parent = oclass->parent;
9a65a38c
BS
38 union {
39 struct nv50_channel_gpfifo_v0 v0;
40 } *args = data;
8f0649b5 41 struct nv50_fifo *fifo = nv50_fifo(base);
9a65a38c
BS
42 struct nv50_fifo_chan *chan;
43 u64 ioffset, ilength;
f01c4e68 44 int ret = -ENOSYS;
9a65a38c
BS
45
46 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
f01c4e68 47 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
832ca2ac 48 nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
9a65a38c
BS
49 "pushbuf %llx ioffset %016llx "
50 "ilength %08x\n",
832ca2ac 51 args->v0.version, args->v0.vmm, args->v0.pushbuf,
9a65a38c 52 args->v0.ioffset, args->v0.ilength);
8f0649b5
BS
53 if (!args->v0.pushbuf)
54 return -EINVAL;
9a65a38c
BS
55 } else
56 return ret;
57
8f0649b5
BS
58 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
59 return -ENOMEM;
60 *pobject = &chan->base.object;
9a65a38c 61
832ca2ac 62 ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
8f0649b5 63 oclass, chan);
9a65a38c
BS
64 if (ret)
65 return ret;
66
8f0649b5 67 args->v0.chid = chan->base.chid;
9a65a38c
BS
68 ioffset = args->v0.ioffset;
69 ilength = order_base_2(args->v0.ilength / 8);
70
8f0649b5
BS
71 nvkm_kmap(chan->ramfc);
72 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
75 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset));
76 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
77 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
78 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
79 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
80 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
9a65a38c
BS
81 (4 << 24) /* SEARCH_FULL */ |
82 (chan->ramht->gpuobj->node->offset >> 4));
8f0649b5 83 nvkm_done(chan->ramfc);
9a65a38c
BS
84 return 0;
85}
86
8f0649b5
BS
87const struct nvkm_fifo_chan_oclass
88nv50_fifo_gpfifo_oclass = {
89 .base.oclass = NV50_CHANNEL_GPFIFO,
90 .base.minver = 0,
91 .base.maxver = 0,
92 .ctor = nv50_fifo_gpfifo_new,
9a65a38c 93};