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a4d4bbf1 | 1 | /* |
c4d0f8f6 | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
a4d4bbf1 AC |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
20 | * DEALINGS IN THE SOFTWARE. | |
21 | */ | |
e3c71eb2 | 22 | #include "ctxgf100.h" |
c85ee6ca | 23 | #include "gf100.h" |
c4d0f8f6 AC |
24 | |
25 | #include <subdev/mc.h> | |
26 | ||
27 | static void | |
bfee3f3d | 28 | gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) |
c4d0f8f6 | 29 | { |
276836d4 | 30 | struct nvkm_device *device = gr->base.engine.subdev.device; |
27f3d6cf | 31 | const struct gf100_grctx_func *grctx = gr->func->grctx; |
933ad445 | 32 | u32 idle_timeout; |
c4d0f8f6 AC |
33 | int i; |
34 | ||
bfee3f3d | 35 | gf100_gr_mmio(gr, gr->fuc_sw_ctx); |
c4d0f8f6 | 36 | |
bfee3f3d | 37 | gf100_gr_wait_idle(gr); |
c4d0f8f6 | 38 | |
933ad445 | 39 | idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); |
c4d0f8f6 | 40 | |
27f3d6cf | 41 | grctx->attrib(info); |
c4d0f8f6 | 42 | |
27f3d6cf | 43 | grctx->unkn(gr); |
c4d0f8f6 | 44 | |
bfee3f3d BS |
45 | gf100_grctx_generate_tpcid(gr); |
46 | gf100_grctx_generate_r406028(gr); | |
47 | gk104_grctx_generate_r418bb8(gr); | |
48 | gf100_grctx_generate_r406800(gr); | |
c4d0f8f6 AC |
49 | |
50 | for (i = 0; i < 8; i++) | |
276836d4 | 51 | nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); |
c4d0f8f6 | 52 | |
276836d4 | 53 | nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); |
c4d0f8f6 | 54 | |
cfb4f929 | 55 | nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); |
c4d0f8f6 | 56 | |
bfee3f3d | 57 | gf100_gr_wait_idle(gr); |
c4d0f8f6 | 58 | |
933ad445 | 59 | nvkm_wr32(device, 0x404154, idle_timeout); |
bfee3f3d | 60 | gf100_gr_wait_idle(gr); |
c4d0f8f6 | 61 | |
bfee3f3d BS |
62 | gf100_gr_mthd(gr, gr->fuc_method); |
63 | gf100_gr_wait_idle(gr); | |
a4d4bbf1 | 64 | |
bfee3f3d | 65 | gf100_gr_icmd(gr, gr->fuc_bundle); |
27f3d6cf BS |
66 | grctx->pagepool(info); |
67 | grctx->bundle(info); | |
c4d0f8f6 | 68 | } |
a4d4bbf1 | 69 | |
27f3d6cf BS |
70 | const struct gf100_grctx_func |
71 | gk20a_grctx = { | |
c4d0f8f6 | 72 | .main = gk20a_grctx_generate_main, |
e3c71eb2 | 73 | .unkn = gk104_grctx_generate_unkn, |
e3c71eb2 | 74 | .bundle = gk104_grctx_generate_bundle, |
aa2d58c3 BS |
75 | .bundle_size = 0x1800, |
76 | .bundle_min_gpm_fifo_depth = 0x62, | |
77 | .bundle_token_limit = 0x100, | |
e3c71eb2 | 78 | .pagepool = gk104_grctx_generate_pagepool, |
f331a15f | 79 | .pagepool_size = 0x8000, |
e3c71eb2 | 80 | .attrib = gf117_grctx_generate_attrib, |
67cfbfdf BS |
81 | .attrib_nr_max = 0x240, |
82 | .attrib_nr = 0x240, | |
83 | .alpha_nr_max = 0x648 + (0x648 / 2), | |
84 | .alpha_nr = 0x648, | |
27f3d6cf | 85 | }; |