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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e3c71eb2 BS |
2 | #ifndef __NVKM_GRCTX_H__ |
3 | #define __NVKM_GRCTX_H__ | |
4 | #include <core/gpuobj.h> | |
054b93e4 | 5 | |
e3c71eb2 BS |
6 | struct nvkm_grctx { |
7 | struct nvkm_device *device; | |
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8 | |
9 | enum { | |
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10 | NVKM_GRCTX_PROG, |
11 | NVKM_GRCTX_VALS | |
054b93e4 | 12 | } mode; |
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13 | u32 *ucode; |
14 | struct nvkm_gpuobj *data; | |
054b93e4 | 15 | |
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16 | u32 ctxprog_max; |
17 | u32 ctxprog_len; | |
18 | u32 ctxprog_reg; | |
19 | int ctxprog_label[32]; | |
20 | u32 ctxvals_pos; | |
21 | u32 ctxvals_base; | |
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22 | }; |
23 | ||
054b93e4 | 24 | static inline void |
e3c71eb2 | 25 | cp_out(struct nvkm_grctx *ctx, u32 inst) |
054b93e4 | 26 | { |
142ea05f | 27 | u32 *ctxprog = ctx->ucode; |
054b93e4 | 28 | |
e3c71eb2 | 29 | if (ctx->mode != NVKM_GRCTX_PROG) |
054b93e4 BS |
30 | return; |
31 | ||
32 | BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); | |
33 | ctxprog[ctx->ctxprog_len++] = inst; | |
34 | } | |
35 | ||
36 | static inline void | |
e3c71eb2 | 37 | cp_lsr(struct nvkm_grctx *ctx, u32 val) |
054b93e4 BS |
38 | { |
39 | cp_out(ctx, CP_LOAD_SR | val); | |
40 | } | |
41 | ||
42 | static inline void | |
e3c71eb2 | 43 | cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) |
054b93e4 BS |
44 | { |
45 | ctx->ctxprog_reg = (reg - 0x00400000) >> 2; | |
46 | ||
47 | ctx->ctxvals_base = ctx->ctxvals_pos; | |
48 | ctx->ctxvals_pos = ctx->ctxvals_base + length; | |
49 | ||
50 | if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { | |
51 | cp_lsr(ctx, length); | |
52 | length = 0; | |
53 | } | |
54 | ||
55 | cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); | |
56 | } | |
57 | ||
58 | static inline void | |
e3c71eb2 | 59 | cp_name(struct nvkm_grctx *ctx, int name) |
054b93e4 | 60 | { |
142ea05f | 61 | u32 *ctxprog = ctx->ucode; |
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62 | int i; |
63 | ||
e3c71eb2 | 64 | if (ctx->mode != NVKM_GRCTX_PROG) |
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65 | return; |
66 | ||
67 | ctx->ctxprog_label[name] = ctx->ctxprog_len; | |
68 | for (i = 0; i < ctx->ctxprog_len; i++) { | |
69 | if ((ctxprog[i] & 0xfff00000) != 0xff400000) | |
70 | continue; | |
71 | if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) | |
72 | continue; | |
73 | ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | | |
74 | (ctx->ctxprog_len << CP_BRA_IP_SHIFT); | |
75 | } | |
76 | } | |
77 | ||
78 | static inline void | |
e3c71eb2 | 79 | _cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name) |
054b93e4 BS |
80 | { |
81 | int ip = 0; | |
82 | ||
83 | if (mod != 2) { | |
84 | ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; | |
85 | if (ip == 0) | |
86 | ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); | |
87 | } | |
88 | ||
89 | cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | | |
90 | (state ? 0 : CP_BRA_IF_CLEAR)); | |
91 | } | |
0b89a072 | 92 | #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) |
0b89a072 EV |
93 | #define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) |
94 | #define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) | |
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95 | |
96 | static inline void | |
e3c71eb2 | 97 | _cp_wait(struct nvkm_grctx *ctx, int flag, int state) |
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98 | { |
99 | cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); | |
100 | } | |
0b89a072 | 101 | #define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) |
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102 | |
103 | static inline void | |
e3c71eb2 | 104 | _cp_set(struct nvkm_grctx *ctx, int flag, int state) |
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105 | { |
106 | cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); | |
107 | } | |
0b89a072 | 108 | #define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) |
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109 | |
110 | static inline void | |
e3c71eb2 | 111 | cp_pos(struct nvkm_grctx *ctx, int offset) |
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112 | { |
113 | ctx->ctxvals_pos = offset; | |
114 | ctx->ctxvals_base = ctx->ctxvals_pos; | |
115 | ||
116 | cp_lsr(ctx, ctx->ctxvals_pos); | |
117 | cp_out(ctx, CP_SET_CONTEXT_POINTER); | |
118 | } | |
119 | ||
120 | static inline void | |
e3c71eb2 | 121 | gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) |
054b93e4 | 122 | { |
e3c71eb2 | 123 | if (ctx->mode != NVKM_GRCTX_VALS) |
054b93e4 BS |
124 | return; |
125 | ||
126 | reg = (reg - 0x00400000) / 4; | |
127 | reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; | |
128 | ||
142ea05f | 129 | nvkm_wo32(ctx->data, reg * 4, val); |
054b93e4 | 130 | } |
054b93e4 | 131 | #endif |