[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / fuc / gpc.fuc

/* fuc microcode for gf100 PGRAPH/GPC
 *
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

/* TODO
 * - bracket certain functions with scratch writes, useful for debugging
 * - watchdog timer around ctx operations
 */

#ifdef INCLUDE_DATA
gpc_mmio_list_head:	.b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head:	.b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head:	.b32 #mmio_list_base
unk_mmio_list_tail:	.b32 #mmio_list_base

gpc_id:			.b32 0

tpc_count:		.b32 0
tpc_mask:		.b32 0

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count:		.b32 0
unk_mask:		.b32 0
#endif

cmd_queue:		queue_init

mmio_list_base:
#endif

#ifdef INCLUDE_CODE
// reports an exception to the host
//
// In: $r15 error code (see os.h)
//
error:
	push $r14
	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
	mov $r15 1
	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
	pop $r14
	ret

// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
//   CC_SCRATCH[1]: context base
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: GPC context size
//
init:
	clear b32 $r0

	// setup stack
	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
	extr $r1 $r1 9:17
	shl b32 $r1 8
	mov $sp $r1

	// enable fifo access
	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)

	// enable fifo interrupt
	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)

	// enable interrupts
	bset $flags ie0

	// figure out which GPC we are, and how many TPCs we have
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
	mov $r3 1
	and $r2 0x1f
	shl b32 $r3 $r2
	sub b32 $r3 1
	st b32 D[$r0 + #tpc_count] $r2
	st b32 D[$r0 + #tpc_mask] $r3
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
	st b32 D[$r0 + #gpc_id] $r2

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// figure out which, and how many, UNKs are actually present
	imm32($r14, 0x500c30)
	clear b32 $r2
	clear b32 $r3
	clear b32 $r4
	init_unk_loop:
		call(nv_rd32)
		cmp b32 $r15 0
		bra z #init_unk_next
			mov $r15 1
			shl b32 $r15 $r2
			or $r4 $r15
			add b32 $r3 1
		init_unk_next:
		add b32 $r2 1
		add b32 $r14 4
		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
		bra ne #init_unk_loop
	init_unk_done:
	st b32 D[$r0 + #unk_count] $r3
	st b32 D[$r0 + #unk_mask] $r4
#endif

	// initialise context base, and size tracking
	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,
	// they don't currently ever change
	shr b32 $r5 $r2 8
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)

	// calculate GPC mmio context size
	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
	call(mmctx_size)
	add b32 $r2 $r15
	add b32 $r3 $r15

	// calculate per-TPC mmio context size
	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #tpc_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// calculate per-UNK mmio context size
	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	call(mmctx_size)
	ld b32 $r14 D[$r0 + #unk_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14
#endif

	// round up base/size to 256 byte boundary (for strand SWBASE)
	shr b32 $r3 2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
	shr b32 $r2 8
	shr b32 $r3 6
	add b32 $r2 1
	add b32 $r3 1
	shl b32 $r2 8
	shl b32 $r3 8

	// calculate size of strand context data
	mov b32 $r15 $r2
	call(strand_ctx_init)
	add b32 $r3 $r15

	// save context size, and tell HUB we're done
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
	clear b32 $r2
	bset $r2 31
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)

// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
main:
	bset $flags $p0
	sleep $p0
	mov $r13 #cmd_queue
	call(queue_get)
	bra $p1 #main

	// 0x0000-0x0003 are all context transfers
	cmpu b32 $r14 0x04
	bra nc #main_not_ctx_xfer
		// fetch $flags and mask off $p1/$p2
		mov $r1 $flags
		mov $r2 0x0006
		not b32 $r2
		and $r1 $r2
		// set $p1/$p2 according to transfer type
		shl b32 $r14 1
		or $r1 $r14
		mov $flags $r1
		// transfer context data
		call(ctx_xfer)
		bra #main

	main_not_ctx_xfer:
	shl b32 $r15 $r14 16
	or $r15 E_BAD_COMMAND
	call(error)
	bra #main

// interrupt handler
ih:
	push $r8
	mov $r8 $flags
	push $r8
	push $r9
	push $r10
	push $r11
	push $r13
	push $r14
	push $r15
	clear b32 $r0

	// incoming fifo command?
	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
	bra e #ih_no_fifo
		// queue incoming fifo command for later processing
		mov $r13 #cmd_queue
		nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
		nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
		call(queue_put)
		mov $r14 1
		nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)

	// ack, and wake up main()
	ih_no_fifo:
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)

	pop $r15
	pop $r14
	pop $r13
	pop $r11
	pop $r10
	pop $r9
	pop $r8
	mov $flags $r8
	pop $r8
	bclr $flags $p0
	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
	mov $r15 1
	ld b32 $r14 D[$r0 + #gpc_id]
	shl b32 $r15 $r14
	nv_wr32(0x409418, $r15)	// 0x409418 - HUB_BAR_SET
	ret

// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off?  Anyways, without this,
// funny things happen.
//
ctx_redswitch:
	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	mov $r14 8
	ctx_redswitch_delay:
		sub b32 $r14 1
		bra ne #ctx_redswitch_delay
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	ret

// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
//     $p1 clear on save, set on load
//     $p2 set if opposite direction done/will be done, so:
//		on save it means: "a load will follow this save"
//		on load it means: "a save preceeded this load"
//
ctx_xfer:
	// set context base address
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
	bra not $p1 #ctx_xfer_not_load
		call(ctx_redswitch)
	ctx_xfer_not_load:

	// strands
	call(strand_pre)
	clear b32 $r2
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
	xbit $r2 $flags $p1	// SAVE/LOAD
	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)

	// mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 2		// first
	imm32($r11,0x500000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	mov $r14 0		// not multi
	call(mmctx_xfer)

	// per-TPC mmio context
	xbit $r10 $flags $p1	// direction
#if !NV_PGRAPH_GPCX_UNK__SIZE
	or $r10 4		// last
#endif
	imm32($r11, 0x504000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	ld b32 $r15 D[$r0 + #tpc_mask]
	mov $r14 0x800		// stride = 0x800
	call(mmctx_xfer)

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// per-UNK mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 4		// last
	imm32($r11, 0x503000)
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	ld b32 $r15 D[$r0 + #unk_mask]
	mov $r14 0x200		// stride = 0x200
	call(mmctx_xfer)
#endif

	// wait for strands to finish
	call(strand_wait)

	// if load, or a save without a load following, do some
	// unknown stuff that's done after finishing a block of
	// strand commands
	bra $p1 #ctx_xfer_post
	bra not $p2 #ctx_xfer_done
	ctx_xfer_post:
		call(strand_post)

	// mark completion in HUB's barrier
	ctx_xfer_done:
	call(hub_barrier_done)
	ret
#endif
Commit	Line	Data
e3c71eb2	1	/* fuc microcode for gf100 PGRAPH/GPC
e99716f1 BS	2	*
	3	* Copyright 2011 Red Hat Inc.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors: Ben Skeggs
	24	*/
	25
	26	/* TODO
	27	* - bracket certain functions with scratch writes, useful for debugging
	28	* - watchdog timer around ctx operations
	29	*/
	30
	31	#ifdef INCLUDE_DATA
a32b2ffb BS	32	gpc_mmio_list_head: .b32 #mmio_list_base
	33	gpc_mmio_list_tail:
	34	tpc_mmio_list_head: .b32 #mmio_list_base
	35	tpc_mmio_list_tail:
	36	unk_mmio_list_head: .b32 #mmio_list_base
	37	unk_mmio_list_tail: .b32 #mmio_list_base
	38
e99716f1	39	gpc_id: .b32 0
e99716f1 BS	40
	41	tpc_count: .b32 0
	42	tpc_mask: .b32 0
e99716f1	43
26410c67	44	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
f8adeb82 BS	45	unk_count: .b32 0
f8adeb82 BS	46	unk_mask: .b32 0
5ee86c41 BS	47	#endif
5ee86c41 BS	48
e99716f1	49	cmd_queue: queue_init
a32b2ffb BS	50
a32b2ffb BS	51	mmio_list_base:
e99716f1 BS	52	#endif
	53
	54	#ifdef INCLUDE_CODE
	55	// reports an exception to the host
	56	//
23f67841	57	// In: $r15 error code (see os.h)
e99716f1 BS	58	//
	59	error:
	60	push $r14
67af60f0	61	nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
e99716f1	62	mov $r15 1
67af60f0	63	nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
e99716f1 BS	64	pop $r14
	65	ret
	66
	67	// GPC fuc initialisation, executed by triggering ucode start, will
	68	// fall through to main loop after completion.
	69	//
	70	// Input:
e99716f1 BS	71	// CC_SCRATCH[1]: context base
	72	//
	73	// Output:
	74	// CC_SCRATCH[0]:
	75	// 31:31: set to signal completion
	76	// CC_SCRATCH[1]:
	77	// 31:0: GPC context size
	78	//
	79	init:
	80	clear b32 $r0
6acc09b9 BS	81
	82	// setup stack
	83	nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
	84	extr $r1 $r1 9:17
	85	shl b32 $r1 8
	86	mov $sp $r1
e99716f1 BS	87
e99716f1 BS	88	// enable fifo access
67af60f0 BS	89	mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
67af60f0 BS	90	nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)
e99716f1 BS	91
	92	// setup i0 handler, and route all interrupts to it
	93	mov $r1 #ih
	94	mov $iv0 $r1
67af60f0	95	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
e99716f1 BS	96
e99716f1 BS	97	// enable fifo interrupt
67af60f0 BS	98	mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
67af60f0 BS	99	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)
e99716f1 BS	100
	101	// enable interrupts
	102	bset $flags ie0
	103
	104	// figure out which GPC we are, and how many TPCs we have
67af60f0	105	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
e99716f1 BS	106	mov $r3 1
	107	and $r2 0x1f
	108	shl b32 $r3 $r2
	109	sub b32 $r3 1
	110	st b32 D[$r0 + #tpc_count] $r2
	111	st b32 D[$r0 + #tpc_mask] $r3
67af60f0	112	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
e99716f1 BS	113	st b32 D[$r0 + #gpc_id] $r2
e99716f1 BS	114
f8adeb82 BS	115	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
f8adeb82 BS	116	// figure out which, and how many, UNKs are actually present
67af60f0	117	imm32($r14, 0x500c30)
f8adeb82 BS	118	clear b32 $r2
	119	clear b32 $r3
	120	clear b32 $r4
	121	init_unk_loop:
67af60f0	122	call(nv_rd32)
f8adeb82 BS	123	cmp b32 $r15 0
	124	bra z #init_unk_next
	125	mov $r15 1
	126	shl b32 $r15 $r2
	127	or $r4 $r15
	128	add b32 $r3 1
	129	init_unk_next:
	130	add b32 $r2 1
	131	add b32 $r14 4
	132	cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
	133	bra ne #init_unk_loop
	134	init_unk_done:
	135	st b32 D[$r0 + #unk_count] $r3
	136	st b32 D[$r0 + #unk_mask] $r4
	137	#endif
	138
e99716f1	139	// initialise context base, and size tracking
60a4acd7	140	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
e99716f1 BS	141	clear b32 $r3 // track GPC context size here
	142
	143	// set mmctx base addresses now so we don't have to do it later,
	144	// they don't currently ever change
e99716f1	145	shr b32 $r5 $r2 8
67af60f0 BS	146	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
67af60f0 BS	147	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)
e99716f1	148
a32b2ffb BS	149	// calculate GPC mmio context size
	150	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	151	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
67af60f0	152	call(mmctx_size)
e99716f1 BS	153	add b32 $r2 $r15
	154	add b32 $r3 $r15
	155
a32b2ffb BS	156	// calculate per-TPC mmio context size
	157	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	158	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
67af60f0	159	call(mmctx_size)
e99716f1 BS	160	ld b32 $r14 D[$r0 + #tpc_count]
	161	mulu $r14 $r15
	162	add b32 $r2 $r14
	163	add b32 $r3 $r14
	164
26410c67	165	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
5ee86c41 BS	166	// calculate per-UNK mmio context size
	167	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	168	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
67af60f0	169	call(mmctx_size)
5ee86c41 BS	170	ld b32 $r14 D[$r0 + #unk_count]
	171	mulu $r14 $r15
	172	add b32 $r2 $r14
	173	add b32 $r3 $r14
	174	#endif
	175
e99716f1	176	// round up base/size to 256 byte boundary (for strand SWBASE)
e99716f1	177	shr b32 $r3 2
67af60f0	178	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
e99716f1 BS	179	shr b32 $r2 8
	180	shr b32 $r3 6
	181	add b32 $r2 1
	182	add b32 $r3 1
	183	shl b32 $r2 8
	184	shl b32 $r3 8
	185
	186	// calculate size of strand context data
	187	mov b32 $r15 $r2
67af60f0	188	call(strand_ctx_init)
e99716f1 BS	189	add b32 $r3 $r15
	190
	191	// save context size, and tell HUB we're done
60a4acd7	192	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
e99716f1 BS	193	clear b32 $r2
e99716f1 BS	194	bset $r2 31
60a4acd7	195	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
e99716f1 BS	196
	197	// Main program loop, very simple, sleeps until woken up by the interrupt
	198	// handler, pulls a command from the queue and executes its handler
	199	//
	200	main:
	201	bset $flags $p0
	202	sleep $p0
	203	mov $r13 #cmd_queue
67af60f0	204	call(queue_get)
e99716f1 BS	205	bra $p1 #main
	206
	207	// 0x0000-0x0003 are all context transfers
	208	cmpu b32 $r14 0x04
	209	bra nc #main_not_ctx_xfer
	210	// fetch $flags and mask off $p1/$p2
	211	mov $r1 $flags
	212	mov $r2 0x0006
	213	not b32 $r2
	214	and $r1 $r2
	215	// set $p1/$p2 according to transfer type
	216	shl b32 $r14 1
	217	or $r1 $r14
	218	mov $flags $r1
	219	// transfer context data
67af60f0	220	call(ctx_xfer)
e99716f1 BS	221	bra #main
	222
	223	main_not_ctx_xfer:
	224	shl b32 $r15 $r14 16
	225	or $r15 E_BAD_COMMAND
67af60f0	226	call(error)
e99716f1 BS	227	bra #main
	228
	229	// interrupt handler
	230	ih:
	231	push $r8
	232	mov $r8 $flags
	233	push $r8
	234	push $r9
	235	push $r10
	236	push $r11
	237	push $r13
	238	push $r14
	239	push $r15
60a4acd7	240	clear b32 $r0
e99716f1 BS	241
e99716f1 BS	242	// incoming fifo command?
67af60f0 BS	243	nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
67af60f0 BS	244	and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
e99716f1 BS	245	bra e #ih_no_fifo
e99716f1 BS	246	// queue incoming fifo command for later processing
e99716f1	247	mov $r13 #cmd_queue
67af60f0 BS	248	nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
	249	nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
	250	call(queue_put)
e99716f1	251	mov $r14 1
67af60f0	252	nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)
e99716f1 BS	253
	254	// ack, and wake up main()
	255	ih_no_fifo:
67af60f0	256	nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)
e99716f1 BS	257
	258	pop $r15
	259	pop $r14
	260	pop $r13
	261	pop $r11
	262	pop $r10
	263	pop $r9
	264	pop $r8
	265	mov $flags $r8
	266	pop $r8
	267	bclr $flags $p0
	268	iret
	269
	270	// Set this GPC's bit in HUB_BAR, used to signal completion of various
	271	// activities to the HUB fuc
	272	//
	273	hub_barrier_done:
	274	mov $r15 1
	275	ld b32 $r14 D[$r0 + #gpc_id]
	276	shl b32 $r15 $r14
67af60f0	277	nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET
e99716f1 BS	278	ret
	279
	280	// Disables various things, waits a bit, and re-enables them..
	281	//
	282	// Not sure how exactly this helps, perhaps "ENABLE" is not such a
	283	// good description for the bits we turn off? Anyways, without this,
	284	// funny things happen.
	285	//
	286	ctx_redswitch:
67af60f0 BS	287	mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
	288	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
	289	mov $r14 8
e99716f1	290	ctx_redswitch_delay:
67af60f0	291	sub b32 $r14 1
e99716f1	292	bra ne #ctx_redswitch_delay
67af60f0 BS	293	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
	294	or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
	295	nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
e99716f1 BS	296	ret
	297
	298	// Transfer GPC context data between GPU and storage area
	299	//
	300	// In: $r15 context base address
	301	// $p1 clear on save, set on load
	302	// $p2 set if opposite direction done/will be done, so:
	303	// on save it means: "a load will follow this save"
	304	// on load it means: "a save preceeded this load"
	305	//
	306	ctx_xfer:
	307	// set context base address
67af60f0	308	nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
e99716f1	309	bra not $p1 #ctx_xfer_not_load
67af60f0	310	call(ctx_redswitch)
e99716f1 BS	311	ctx_xfer_not_load:
	312
	313	// strands
67af60f0 BS	314	call(strand_pre)
	315	clear b32 $r2
	316	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
	317	xbit $r2 $flags $p1 // SAVE/LOAD
	318	add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
	319	nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
e99716f1 BS	320
	321	// mmio context
	322	xbit $r10 $flags $p1 // direction
	323	or $r10 2 // first
67af60f0	324	imm32($r11,0x500000)
e99716f1 BS	325	ld b32 $r12 D[$r0 + #gpc_id]
	326	shl b32 $r12 15
	327	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
	328	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	329	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	330	mov $r14 0 // not multi
67af60f0	331	call(mmctx_xfer)
e99716f1 BS	332
	333	// per-TPC mmio context
	334	xbit $r10 $flags $p1 // direction
d2989b53 ML	335	#if !NV_PGRAPH_GPCX_UNK__SIZE
	336	or $r10 4 // last
	337	#endif
67af60f0	338	imm32($r11, 0x504000)
e99716f1 BS	339	ld b32 $r12 D[$r0 + #gpc_id]
	340	shl b32 $r12 15
	341	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
	342	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	343	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	344	ld b32 $r15 D[$r0 + #tpc_mask]
	345	mov $r14 0x800 // stride = 0x800
67af60f0	346	call(mmctx_xfer)
e99716f1	347
26410c67	348	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
5ee86c41 BS	349	// per-UNK mmio context
	350	xbit $r10 $flags $p1 // direction
	351	or $r10 4 // last
67af60f0	352	imm32($r11, 0x503000)
5ee86c41 BS	353	ld b32 $r12 D[$r0 + #gpc_id]
	354	shl b32 $r12 15
	355	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
	356	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	357	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	358	ld b32 $r15 D[$r0 + #unk_mask]
	359	mov $r14 0x200 // stride = 0x200
67af60f0	360	call(mmctx_xfer)
5ee86c41 BS	361	#endif
5ee86c41 BS	362
e99716f1	363	// wait for strands to finish
67af60f0	364	call(strand_wait)
e99716f1 BS	365
	366	// if load, or a save without a load following, do some
	367	// unknown stuff that's done after finishing a block of
	368	// strand commands
	369	bra $p1 #ctx_xfer_post
	370	bra not $p2 #ctx_xfer_done
	371	ctx_xfer_post:
67af60f0	372	call(strand_post)
e99716f1 BS	373
	374	// mark completion in HUB's barrier
	375	ctx_xfer_done:
67af60f0	376	call(hub_barrier_done)
e99716f1 BS	377	ret
e99716f1 BS	378	#endif