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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / gf100.c
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4b223eef 1/*
ebb945a9 2 * Copyright 2012 Red Hat Inc.
4b223eef
BS		 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
e3c71eb2
BS		 24#include "gf100.h"
25#include "ctxgf100.h"
26#include "fuc/os.h"
27
28#include <core/client.h>
e3c71eb2 29#include <core/option.h>
33bcb4c3 30#include <core/firmware.h>
c9469aae 31#include <subdev/secboot.h>
e3c71eb2
BS		 32#include <subdev/fb.h>
33#include <subdev/mc.h>
c85ee6ca 34#include <subdev/pmu.h>
e3c71eb2 35#include <subdev/timer.h>
a65955e1 36#include <engine/fifo.h>
e3c71eb2
BS		 37
38#include <nvif/class.h>
53a6df77 39#include <nvif/cl9097.h>
019e4d76 40#include <nvif/if900d.h>
e3c71eb2 41#include <nvif/unpack.h>
0411de85 42
ac9738bb
BS		 43/*******************************************************************************
44 * Zero Bandwidth Clear
45 ******************************************************************************/
46
47static void
bfee3f3d 48gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
ac9738bb 49{
276836d4 50 struct nvkm_device *device = gr->base.engine.subdev.device;
bfee3f3d 51 if (gr->zbc_color[zbc].format) {
276836d4
BS		 52 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
53 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
54 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
55 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
56 }
57 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
58 nvkm_wr32(device, 0x405820, zbc);
59 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
ac9738bb
BS		 60}
61
62static int
bfee3f3d 63gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
e3c71eb2 64 const u32 ds[4], const u32 l2[4])
ac9738bb 65{
70bc7182 66 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
ac9738bb
BS		 67 int zbc = -ENOSPC, i;
68
69 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
bfee3f3d
BS		 70 if (gr->zbc_color[i].format) {
71 if (gr->zbc_color[i].format != format)
ac9738bb 72 continue;
bfee3f3d
BS		 73 if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
74 gr->zbc_color[i].ds)))
ac9738bb 75 continue;
bfee3f3d
BS		 76 if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
77 gr->zbc_color[i].l2))) {
ac9738bb
BS		 78 WARN_ON(1);
79 return -EINVAL;
80 }
81 return i;
82 } else {
83 zbc = (zbc < 0) ? i : zbc;
84 }
85 }
86
da7c74ea
BS		 87 if (zbc < 0)
88 return zbc;
89
bfee3f3d
BS		 90 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
91 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
92 gr->zbc_color[zbc].format = format;
70bc7182 93 nvkm_ltc_zbc_color_get(ltc, zbc, l2);
bfee3f3d 94 gf100_gr_zbc_clear_color(gr, zbc);
ac9738bb
BS		 95 return zbc;
96}
97
98static void
bfee3f3d 99gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
ac9738bb 100{
276836d4 101 struct nvkm_device *device = gr->base.engine.subdev.device;
bfee3f3d 102 if (gr->zbc_depth[zbc].format)
276836d4
BS		 103 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
104 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
105 nvkm_wr32(device, 0x405820, zbc);
106 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
ac9738bb
BS		 107}
108
109static int
bfee3f3d 110gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
e3c71eb2 111 const u32 ds, const u32 l2)
ac9738bb 112{
70bc7182 113 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
ac9738bb
BS		 114 int zbc = -ENOSPC, i;
115
116 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
bfee3f3d
BS		 117 if (gr->zbc_depth[i].format) {
118 if (gr->zbc_depth[i].format != format)
ac9738bb 119 continue;
bfee3f3d 120 if (gr->zbc_depth[i].ds != ds)
ac9738bb 121 continue;
bfee3f3d 122 if (gr->zbc_depth[i].l2 != l2) {
ac9738bb
BS		 123 WARN_ON(1);
124 return -EINVAL;
125 }
126 return i;
127 } else {
128 zbc = (zbc < 0) ? i : zbc;
129 }
130 }
131
da7c74ea
BS		 132 if (zbc < 0)
133 return zbc;
134
bfee3f3d
BS		 135 gr->zbc_depth[zbc].format = format;
136 gr->zbc_depth[zbc].ds = ds;
137 gr->zbc_depth[zbc].l2 = l2;
70bc7182 138 nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
bfee3f3d 139 gf100_gr_zbc_clear_depth(gr, zbc);
ac9738bb
BS		 140 return zbc;
141}
142
ebb945a9
BS		 143/*******************************************************************************
144 * Graphics object classes
145 ******************************************************************************/
5bf561ee
BS		 146#define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
147
148struct gf100_gr_object {
149 struct nvkm_object object;
150 struct gf100_gr_chan *chan;
151};
ebb945a9 152
ac9738bb 153static int
e3c71eb2 154gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
ac9738bb 155{
0d7fc246 156 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
ac9738bb
BS		 157 union {
158 struct fermi_a_zbc_color_v0 v0;
159 } *args = data;
f01c4e68 160 int ret = -ENOSYS;
ac9738bb 161
f01c4e68 162 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
ac9738bb
BS		 163 switch (args->v0.format) {
164 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
165 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
166 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
167 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
168 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
169 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
170 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
171 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
172 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
173 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
174 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
175 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
176 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
177 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
178 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
179 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
180 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
181 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
182 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
bfee3f3d 183 ret = gf100_gr_zbc_color_get(gr, args->v0.format,
e3c71eb2
BS		 184 args->v0.ds,
185 args->v0.l2);
ac9738bb
BS		 186 if (ret >= 0) {
187 args->v0.index = ret;
188 return 0;
189 }
190 break;
191 default:
192 return -EINVAL;
193 }
194 }
195
196 return ret;
197}
198
199static int
e3c71eb2 200gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
ac9738bb 201{
0d7fc246 202 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
ac9738bb
BS		 203 union {
204 struct fermi_a_zbc_depth_v0 v0;
205 } *args = data;
f01c4e68 206 int ret = -ENOSYS;
ac9738bb 207
f01c4e68 208 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
ac9738bb
BS		 209 switch (args->v0.format) {
210 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
bfee3f3d 211 ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
e3c71eb2
BS		 212 args->v0.ds,
213 args->v0.l2);
ac9738bb
BS		 214 return (ret >= 0) ? 0 : -ENOSPC;
215 default:
216 return -EINVAL;
217 }
218 }
219
220 return ret;
221}
222
223static int
e3c71eb2 224gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
ac9738bb 225{
f01c4e68 226 nvif_ioctl(object, "fermi mthd %08x\n", mthd);
ac9738bb
BS		 227 switch (mthd) {
228 case FERMI_A_ZBC_COLOR:
e3c71eb2 229 return gf100_fermi_mthd_zbc_color(object, data, size);
ac9738bb 230 case FERMI_A_ZBC_DEPTH:
e3c71eb2 231 return gf100_fermi_mthd_zbc_depth(object, data, size);
ac9738bb
BS		 232 default:
233 break;
234 }
235 return -EINVAL;
236}
237
27f3d6cf
BS		 238const struct nvkm_object_func
239gf100_fermi = {
e3c71eb2 240 .mthd = gf100_fermi_mthd,
ac9738bb
BS		 241};
242
a65955e1
BS		 243static void
244gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
d6bd3803 245{
a65955e1
BS		 246 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
247 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
d6bd3803
BS		 248}
249
a65955e1
BS		 250static bool
251gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
252{
253 switch (class & 0x00ff) {
254 case 0x97:
255 case 0xc0:
256 switch (mthd) {
257 case 0x1528:
258 gf100_gr_mthd_set_shader_exceptions(device, data);
259 return true;
260 default:
261 break;
262 }
263 break;
264 default:
265 break;
266 }
267 return false;
268}
d6bd3803 269
5bf561ee
BS		 270static const struct nvkm_object_func
271gf100_gr_object_func = {
272};
273
274static int
275gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
276 struct nvkm_object **pobject)
277{
278 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
279 struct gf100_gr_object *object;
280
281 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
282 return -ENOMEM;
283 *pobject = &object->object;
284
285 nvkm_object_ctor(oclass->base.func ? oclass->base.func :
286 &gf100_gr_object_func, oclass, &object->object);
287 object->chan = chan;
288 return 0;
289}
290
27f3d6cf
BS		 291static int
292gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
293{
294 struct gf100_gr *gr = gf100_gr(base);
295 int c = 0;
296
297 while (gr->func->sclass[c].oclass) {
298 if (c++ == index) {
299 *sclass = gr->func->sclass[index];
5bf561ee 300 sclass->ctor = gf100_gr_object_new;
27f3d6cf
BS		 301 return index;
302 }
303 }
304
305 return c;
306}
ebb945a9 307
ebb945a9
BS		 308/*******************************************************************************
309 * PGRAPH context
310 ******************************************************************************/
966a5b7d 311
27f3d6cf
BS		 312static int
313gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
314 int align, struct nvkm_gpuobj **pgpuobj)
966a5b7d 315{
27f3d6cf
BS		 316 struct gf100_gr_chan *chan = gf100_gr_chan(object);
317 struct gf100_gr *gr = chan->gr;
318 int ret, i;
319
320 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
321 align, false, parent, pgpuobj);
322 if (ret)
323 return ret;
324
325 nvkm_kmap(*pgpuobj);
326 for (i = 0; i < gr->size; i += 4)
327 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
328
329 if (!gr->firmware) {
330 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
019e4d76 331 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
27f3d6cf
BS		 332 } else {
333 nvkm_wo32(*pgpuobj, 0xf4, 0);
334 nvkm_wo32(*pgpuobj, 0xf8, 0);
335 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
019e4d76
BS		 336 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
337 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
27f3d6cf
BS		 338 nvkm_wo32(*pgpuobj, 0x1c, 1);
339 nvkm_wo32(*pgpuobj, 0x20, 0);
340 nvkm_wo32(*pgpuobj, 0x28, 0);
341 nvkm_wo32(*pgpuobj, 0x2c, 0);
342 }
343 nvkm_done(*pgpuobj);
344 return 0;
345}
346
347static void *
348gf100_gr_chan_dtor(struct nvkm_object *object)
349{
350 struct gf100_gr_chan *chan = gf100_gr_chan(object);
351 int i;
352
353 for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
019e4d76 354 nvkm_vmm_put(chan->vmm, &chan->data[i].vma);
997a8900 355 nvkm_memory_unref(&chan->data[i].mem);
27f3d6cf
BS		 356 }
357
019e4d76 358 nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
997a8900 359 nvkm_memory_unref(&chan->mmio);
019e4d76 360 nvkm_vmm_unref(&chan->vmm);
27f3d6cf
BS		 361 return chan;
362}
363
364static const struct nvkm_object_func
365gf100_gr_chan = {
366 .dtor = gf100_gr_chan_dtor,
367 .bind = gf100_gr_chan_bind,
368};
369
370static int
371gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
372 const struct nvkm_oclass *oclass,
373 struct nvkm_object **pobject)
374{
375 struct gf100_gr *gr = gf100_gr(base);
bfee3f3d
BS		 376 struct gf100_gr_data *data = gr->mmio_data;
377 struct gf100_gr_mmio *mmio = gr->mmio_list;
e3c71eb2 378 struct gf100_gr_chan *chan;
019e4d76 379 struct gf100_vmm_map_v0 args = { .priv = 1 };
227c95d9 380 struct nvkm_device *device = gr->base.engine.subdev.device;
966a5b7d 381 int ret, i;
966a5b7d 382
27f3d6cf
BS		 383 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
384 return -ENOMEM;
385 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
386 chan->gr = gr;
019e4d76 387 chan->vmm = nvkm_vmm_ref(fifoch->vmm);
27f3d6cf 388 *pobject = &chan->object;
966a5b7d 389
ac1499d9
BS		 390 /* allocate memory for a "mmio list" buffer that's used by the HUB
391 * fuc to modify some per-context register settings on first load
392 * of the context.
393 */
227c95d9
BS		 394 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
395 false, &chan->mmio);
73a60c0d
BS		 396 if (ret)
397 return ret;
398
019e4d76 399 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
73a60c0d
BS		 400 if (ret)
401 return ret;
402
f66c57d9 403 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
019e4d76 404 chan->mmio_vma, &args, sizeof(args));
19a82e49
BS		 405 if (ret)
406 return ret;
227c95d9 407
ac1499d9 408 /* allocate buffers referenced by mmio list */
bfee3f3d 409 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
227c95d9
BS		 410 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
411 data->size, data->align, false,
412 &chan->data[i].mem);
ac1499d9
BS		 413 if (ret)
414 return ret;
73a60c0d 415
019e4d76
BS		 416 ret = nvkm_vmm_get(fifoch->vmm, 12,
417 nvkm_memory_size(chan->data[i].mem),
418 &chan->data[i].vma);
ac1499d9
BS		 419 if (ret)
420 return ret;
966a5b7d 421
019e4d76
BS		 422 args.priv = data->priv;
423
424 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm,
425 chan->data[i].vma, &args, sizeof(args));
19a82e49
BS		 426 if (ret)
427 return ret;
428
ac1499d9 429 data++;
966a5b7d
BS		 430 }
431
ac1499d9 432 /* finally, fill in the mmio list and point the context at it */
142ea05f 433 nvkm_kmap(chan->mmio);
bfee3f3d 434 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
ac1499d9
BS		 435 u32 addr = mmio->addr;
436 u32 data = mmio->data;
966a5b7d 437
694c6caf 438 if (mmio->buffer >= 0) {
019e4d76 439 u64 info = chan->data[mmio->buffer].vma->addr;
ac1499d9
BS		 440 data |= info >> mmio->shift;
441 }
73a60c0d 442
142ea05f
BS		 443 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
444 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
ac1499d9
BS		 445 mmio++;
446 }
142ea05f 447 nvkm_done(chan->mmio);
ebb945a9 448 return 0;
4b223eef
BS		 449}
450
ebb945a9 451/*******************************************************************************
c33b1e8c 452 * PGRAPH register lists
ebb945a9
BS		 453 ******************************************************************************/
454
e3c71eb2
BS		 455const struct gf100_gr_init
456gf100_gr_init_main_0[] = {
30f4e087
BS		 457 { 0x400080, 1, 0x04, 0x003083c2 },
458 { 0x400088, 1, 0x04, 0x00006fe7 },
459 { 0x40008c, 1, 0x04, 0x00000000 },
460 { 0x400090, 1, 0x04, 0x00000030 },
461 { 0x40013c, 1, 0x04, 0x013901f7 },
462 { 0x400140, 1, 0x04, 0x00000100 },
463 { 0x400144, 1, 0x04, 0x00000000 },
464 { 0x400148, 1, 0x04, 0x00000110 },
465 { 0x400138, 1, 0x04, 0x00000000 },
466 { 0x400130, 2, 0x04, 0x00000000 },
467 { 0x400124, 1, 0x04, 0x00000002 },
468 {}
469};
470
e3c71eb2
BS		 471const struct gf100_gr_init
472gf100_gr_init_fe_0[] = {
30f4e087
BS		 473 { 0x40415c, 1, 0x04, 0x00000000 },
474 { 0x404170, 1, 0x04, 0x00000000 },
475 {}
476};
477
e3c71eb2
BS		 478const struct gf100_gr_init
479gf100_gr_init_pri_0[] = {
30f4e087
BS		 480 { 0x404488, 2, 0x04, 0x00000000 },
481 {}
482};
483
e3c71eb2
BS		 484const struct gf100_gr_init
485gf100_gr_init_rstr2d_0[] = {
30f4e087
BS		 486 { 0x407808, 1, 0x04, 0x00000000 },
487 {}
488};
489
e3c71eb2
BS		 490const struct gf100_gr_init
491gf100_gr_init_pd_0[] = {
30f4e087
BS		 492 { 0x406024, 1, 0x04, 0x00000000 },
493 {}
494};
495
e3c71eb2
BS		 496const struct gf100_gr_init
497gf100_gr_init_ds_0[] = {
30f4e087
BS		 498 { 0x405844, 1, 0x04, 0x00ffffff },
499 { 0x405850, 1, 0x04, 0x00000000 },
500 { 0x405908, 1, 0x04, 0x00000000 },
501 {}
502};
503
e3c71eb2
BS		 504const struct gf100_gr_init
505gf100_gr_init_scc_0[] = {
30f4e087
BS		 506 { 0x40803c, 1, 0x04, 0x00000000 },
507 {}
508};
509
e3c71eb2
BS		 510const struct gf100_gr_init
511gf100_gr_init_prop_0[] = {
30f4e087 512 { 0x4184a0, 1, 0x04, 0x00000000 },
97af71fa
BS		 513 {}
514};
515
e3c71eb2
BS		 516const struct gf100_gr_init
517gf100_gr_init_gpc_unk_0[] = {
30f4e087
BS		 518 { 0x418604, 1, 0x04, 0x00000000 },
519 { 0x418680, 1, 0x04, 0x00000000 },
520 { 0x418714, 1, 0x04, 0x80000000 },
521 { 0x418384, 1, 0x04, 0x00000000 },
97af71fa
BS		 522 {}
523};
524
e3c71eb2
BS		 525const struct gf100_gr_init
526gf100_gr_init_setup_0[] = {
30f4e087 527 { 0x418814, 3, 0x04, 0x00000000 },
97af71fa
BS		 528 {}
529};
530
e3c71eb2
BS		 531const struct gf100_gr_init
532gf100_gr_init_crstr_0[] = {
30f4e087 533 { 0x418b04, 1, 0x04, 0x00000000 },
97af71fa
BS		 534 {}
535};
536
e3c71eb2
BS		 537const struct gf100_gr_init
538gf100_gr_init_setup_1[] = {
30f4e087
BS		 539 { 0x4188c8, 1, 0x04, 0x80000000 },
540 { 0x4188cc, 1, 0x04, 0x00000000 },
541 { 0x4188d0, 1, 0x04, 0x00010000 },
542 { 0x4188d4, 1, 0x04, 0x00000001 },
97af71fa
BS		 543 {}
544};
545
e3c71eb2
BS		 546const struct gf100_gr_init
547gf100_gr_init_zcull_0[] = {
30f4e087
BS		 548 { 0x418910, 1, 0x04, 0x00010001 },
549 { 0x418914, 1, 0x04, 0x00000301 },
550 { 0x418918, 1, 0x04, 0x00800000 },
551 { 0x418980, 1, 0x04, 0x77777770 },
552 { 0x418984, 3, 0x04, 0x77777777 },
97af71fa
BS		 553 {}
554};
555
e3c71eb2
BS		 556const struct gf100_gr_init
557gf100_gr_init_gpm_0[] = {
30f4e087
BS		 558 { 0x418c04, 1, 0x04, 0x00000000 },
559 { 0x418c88, 1, 0x04, 0x00000000 },
97af71fa
BS		 560 {}
561};
562
e3c71eb2
BS		 563const struct gf100_gr_init
564gf100_gr_init_gpc_unk_1[] = {
30f4e087
BS		 565 { 0x418d00, 1, 0x04, 0x00000000 },
566 { 0x418f08, 1, 0x04, 0x00000000 },
567 { 0x418e00, 1, 0x04, 0x00000050 },
568 { 0x418e08, 1, 0x04, 0x00000000 },
97af71fa
BS		 569 {}
570};
571
e3c71eb2
BS		 572const struct gf100_gr_init
573gf100_gr_init_gcc_0[] = {
30f4e087
BS		 574 { 0x41900c, 1, 0x04, 0x00000000 },
575 { 0x419018, 1, 0x04, 0x00000000 },
576 {}
577};
578
e3c71eb2
BS		 579const struct gf100_gr_init
580gf100_gr_init_tpccs_0[] = {
30f4e087
BS		 581 { 0x419d08, 2, 0x04, 0x00000000 },
582 { 0x419d10, 1, 0x04, 0x00000014 },
7e194533
BS		 583 {}
584};
585
e3c71eb2
BS		 586const struct gf100_gr_init
587gf100_gr_init_tex_0[] = {
30f4e087
BS		 588 { 0x419ab0, 1, 0x04, 0x00000000 },
589 { 0x419ab8, 1, 0x04, 0x000000e7 },
590 { 0x419abc, 2, 0x04, 0x00000000 },
7e194533
BS		 591 {}
592};
593
e3c71eb2
BS		 594const struct gf100_gr_init
595gf100_gr_init_pe_0[] = {
30f4e087
BS		 596 { 0x41980c, 3, 0x04, 0x00000000 },
597 { 0x419844, 1, 0x04, 0x00000000 },
598 { 0x41984c, 1, 0x04, 0x00005bc5 },
599 { 0x419850, 4, 0x04, 0x00000000 },
7e194533
BS		 600 {}
601};
602
e3c71eb2
BS		 603const struct gf100_gr_init
604gf100_gr_init_l1c_0[] = {
30f4e087
BS		 605 { 0x419c98, 1, 0x04, 0x00000000 },
606 { 0x419ca8, 1, 0x04, 0x80000000 },
607 { 0x419cb4, 1, 0x04, 0x00000000 },
608 { 0x419cb8, 1, 0x04, 0x00008bf4 },
609 { 0x419cbc, 1, 0x04, 0x28137606 },
610 { 0x419cc0, 2, 0x04, 0x00000000 },
7e194533
BS		 611 {}
612};
613
e3c71eb2
BS		 614const struct gf100_gr_init
615gf100_gr_init_wwdx_0[] = {
30f4e087
BS		 616 { 0x419bd4, 1, 0x04, 0x00800000 },
617 { 0x419bdc, 1, 0x04, 0x00000000 },
7e194533
BS		 618 {}
619};
620
e3c71eb2
BS		 621const struct gf100_gr_init
622gf100_gr_init_tpccs_1[] = {
30f4e087 623 { 0x419d2c, 1, 0x04, 0x00000000 },
7e194533
BS		 624 {}
625};
626
e3c71eb2
BS		 627const struct gf100_gr_init
628gf100_gr_init_mpc_0[] = {
30f4e087 629 { 0x419c0c, 1, 0x04, 0x00000000 },
7e194533
BS		 630 {}
631};
632
e3c71eb2
BS		 633static const struct gf100_gr_init
634gf100_gr_init_sm_0[] = {
30f4e087
BS		 635 { 0x419e00, 1, 0x04, 0x00000000 },
636 { 0x419ea0, 1, 0x04, 0x00000000 },
637 { 0x419ea4, 1, 0x04, 0x00000100 },
638 { 0x419ea8, 1, 0x04, 0x00001100 },
639 { 0x419eac, 1, 0x04, 0x11100702 },
640 { 0x419eb0, 1, 0x04, 0x00000003 },
641 { 0x419eb4, 4, 0x04, 0x00000000 },
642 { 0x419ec8, 1, 0x04, 0x06060618 },
643 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
644 { 0x419ed4, 1, 0x04, 0x011104f1 },
645 { 0x419edc, 1, 0x04, 0x00000000 },
646 { 0x419f00, 1, 0x04, 0x00000000 },
647 { 0x419f2c, 1, 0x04, 0x00000000 },
648 {}
649};
650
e3c71eb2
BS		 651const struct gf100_gr_init
652gf100_gr_init_be_0[] = {
30f4e087
BS		 653 { 0x40880c, 1, 0x04, 0x00000000 },
654 { 0x408910, 9, 0x04, 0x00000000 },
655 { 0x408950, 1, 0x04, 0x00000000 },
656 { 0x408954, 1, 0x04, 0x0000ffff },
657 { 0x408984, 1, 0x04, 0x00000000 },
658 { 0x408988, 1, 0x04, 0x08040201 },
659 { 0x40898c, 1, 0x04, 0x80402010 },
660 {}
661};
662
e3c71eb2
BS		 663const struct gf100_gr_init
664gf100_gr_init_fe_1[] = {
c33b1e8c
BS		 665 { 0x4040f0, 1, 0x04, 0x00000000 },
666 {}
667};
668
e3c71eb2
BS		 669const struct gf100_gr_init
670gf100_gr_init_pe_1[] = {
c33b1e8c
BS		 671 { 0x419880, 1, 0x04, 0x00000002 },
672 {}
673};
674
e3c71eb2
BS		 675static const struct gf100_gr_pack
676gf100_gr_pack_mmio[] = {
677 { gf100_gr_init_main_0 },
678 { gf100_gr_init_fe_0 },
679 { gf100_gr_init_pri_0 },
680 { gf100_gr_init_rstr2d_0 },
681 { gf100_gr_init_pd_0 },
682 { gf100_gr_init_ds_0 },
683 { gf100_gr_init_scc_0 },
684 { gf100_gr_init_prop_0 },
685 { gf100_gr_init_gpc_unk_0 },
686 { gf100_gr_init_setup_0 },
687 { gf100_gr_init_crstr_0 },
688 { gf100_gr_init_setup_1 },
689 { gf100_gr_init_zcull_0 },
690 { gf100_gr_init_gpm_0 },
691 { gf100_gr_init_gpc_unk_1 },
692 { gf100_gr_init_gcc_0 },
693 { gf100_gr_init_tpccs_0 },
694 { gf100_gr_init_tex_0 },
695 { gf100_gr_init_pe_0 },
696 { gf100_gr_init_l1c_0 },
697 { gf100_gr_init_wwdx_0 },
698 { gf100_gr_init_tpccs_1 },
699 { gf100_gr_init_mpc_0 },
700 { gf100_gr_init_sm_0 },
701 { gf100_gr_init_be_0 },
702 { gf100_gr_init_fe_1 },
703 { gf100_gr_init_pe_1 },
26410c67
ML		 704 {}
705};
706
c33b1e8c
BS		 707/*******************************************************************************
708 * PGRAPH engine/subdev functions
709 ******************************************************************************/
710
6845c313
BS		 711static bool
712gf100_gr_chsw_load(struct nvkm_gr *base)
713{
714 struct gf100_gr *gr = gf100_gr(base);
715 if (!gr->firmware) {
716 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
717 if (trace & 0x00000040)
718 return true;
719 } else {
720 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
721 if (mthd & 0x00080000)
722 return true;
723 }
724 return false;
725}
726
64cb5a31
BS		 727int
728gf100_gr_rops(struct gf100_gr *gr)
729{
730 struct nvkm_device *device = gr->base.engine.subdev.device;
731 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
732}
733
ac9738bb 734void
bfee3f3d 735gf100_gr_zbc_init(struct gf100_gr *gr)
ac9738bb
BS		 736{
737 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
738 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
739 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
740 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
741 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
742 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
743 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
744 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
70bc7182 745 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
ac9738bb
BS		 746 int index;
747
bfee3f3d
BS		 748 if (!gr->zbc_color[0].format) {
749 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]);
750 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]);
751 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]);
752 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]);
753 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);
754 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);
ac9738bb
BS		 755 }
756
757 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
bfee3f3d 758 gf100_gr_zbc_clear_color(gr, index);
ac9738bb 759 for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
bfee3f3d 760 gf100_gr_zbc_clear_depth(gr, index);
ac9738bb
BS		 761}
762
4a8cf451
AC		 763/**
764 * Wait until GR goes idle. GR is considered idle if it is disabled by the
765 * MC (0x200) register, or GR is not busy and a context switch is not in
766 * progress.
767 */
768int
bfee3f3d 769gf100_gr_wait_idle(struct gf100_gr *gr)
4a8cf451 770{
109c2f2f
BS		 771 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
772 struct nvkm_device *device = subdev->device;
4a8cf451
AC		 773 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
774 bool gr_enabled, ctxsw_active, gr_busy;
775
776 do {
777 /*
778 * required to make sure FIFO_ENGINE_STATUS (0x2640) is
779 * up-to-date
780 */
276836d4 781 nvkm_rd32(device, 0x400700);
4a8cf451 782
276836d4
BS		 783 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
784 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
785 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
4a8cf451
AC		 786
787 if (!gr_enabled || (!gr_busy && !ctxsw_active))
788 return 0;
789 } while (time_before(jiffies, end_jiffies));
790
109c2f2f
BS		 791 nvkm_error(subdev,
792 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
793 gr_enabled, ctxsw_active, gr_busy);
4a8cf451
AC		 794 return -EAGAIN;
795}
796
30f4e087 797void
bfee3f3d 798gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
4b223eef 799{
276836d4 800 struct nvkm_device *device = gr->base.engine.subdev.device;
e3c71eb2
BS		 801 const struct gf100_gr_pack *pack;
802 const struct gf100_gr_init *init;
c33b1e8c
BS		 803
804 pack_for_each_init(init, pack, p) {
805 u32 next = init->addr + init->count * init->pitch;
806 u32 addr = init->addr;
807 while (addr < next) {
276836d4 808 nvkm_wr32(device, addr, init->data);
30f4e087
BS		 809 addr += init->pitch;
810 }
811 }
ebb945a9
BS		 812}
813
814void
bfee3f3d 815gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
ebb945a9 816{
276836d4 817 struct nvkm_device *device = gr->base.engine.subdev.device;
e3c71eb2
BS		 818 const struct gf100_gr_pack *pack;
819 const struct gf100_gr_init *init;
c33b1e8c 820 u32 data = 0;
30f4e087 821
276836d4 822 nvkm_wr32(device, 0x400208, 0x80000000);
c33b1e8c
BS		 823
824 pack_for_each_init(init, pack, p) {
825 u32 next = init->addr + init->count * init->pitch;
826 u32 addr = init->addr;
827
828 if ((pack == p && init == p->init) || data != init->data) {
276836d4 829 nvkm_wr32(device, 0x400204, init->data);
30f4e087
BS		 830 data = init->data;
831 }
ebb945a9 832
c33b1e8c 833 while (addr < next) {
276836d4 834 nvkm_wr32(device, 0x400200, addr);
4a8cf451
AC		 835 /**
836 * Wait for GR to go idle after submitting a
837 * GO_IDLE bundle
838 */
839 if ((addr & 0xffff) == 0xe100)
bfee3f3d 840 gf100_gr_wait_idle(gr);
c4584adc
BS		 841 nvkm_msec(device, 2000,
842 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
843 break;
844 );
30f4e087 845 addr += init->pitch;
30f4e087
BS		 846 }
847 }
c33b1e8c 848
276836d4 849 nvkm_wr32(device, 0x400208, 0x00000000);
30f4e087
BS		 850}
851
852void
bfee3f3d 853gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
30f4e087 854{
276836d4 855 struct nvkm_device *device = gr->base.engine.subdev.device;
e3c71eb2
BS		 856 const struct gf100_gr_pack *pack;
857 const struct gf100_gr_init *init;
c33b1e8c 858 u32 data = 0;
30f4e087 859
c33b1e8c
BS		 860 pack_for_each_init(init, pack, p) {
861 u32 ctrl = 0x80000000 | pack->type;
862 u32 next = init->addr + init->count * init->pitch;
863 u32 addr = init->addr;
864
865 if ((pack == p && init == p->init) || data != init->data) {
276836d4 866 nvkm_wr32(device, 0x40448c, init->data);
c33b1e8c
BS		 867 data = init->data;
868 }
869
870 while (addr < next) {
276836d4 871 nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
c33b1e8c 872 addr += init->pitch;
30f4e087
BS		 873 }
874 }
875}
876
877u64
c85ee6ca 878gf100_gr_units(struct nvkm_gr *base)
30f4e087 879{
c85ee6ca 880 struct gf100_gr *gr = gf100_gr(base);
30f4e087
BS		 881 u64 cfg;
882
bfee3f3d
BS		 883 cfg = (u32)gr->gpc_nr;
884 cfg |= (u32)gr->tpc_total << 8;
885 cfg |= (u64)gr->rop_nr << 32;
30f4e087
BS		 886
887 return cfg;
ebb945a9
BS		 888}
889
caf2be8a
IM		 890static const struct nvkm_bitfield gf100_dispatch_error[] = {
891 { 0x00000001, "INJECTED_BUNDLE_ERROR" },
892 { 0x00000002, "CLASS_SUBCH_MISMATCH" },
893 { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
894 {}
895};
896
897static const struct nvkm_bitfield gf100_m2mf_error[] = {
898 { 0x00000001, "PUSH_TOO_MUCH_DATA" },
899 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
900 {}
901};
902
903static const struct nvkm_bitfield gf100_unk6_error[] = {
904 { 0x00000001, "TEMP_TOO_SMALL" },
905 {}
906};
907
908static const struct nvkm_bitfield gf100_ccache_error[] = {
909 { 0x00000001, "INTR" },
910 { 0x00000002, "LDCONST_OOB" },
911 {}
912};
913
914static const struct nvkm_bitfield gf100_macro_error[] = {
915 { 0x00000001, "TOO_FEW_PARAMS" },
916 { 0x00000002, "TOO_MANY_PARAMS" },
917 { 0x00000004, "ILLEGAL_OPCODE" },
918 { 0x00000008, "DOUBLE_BRANCH" },
919 { 0x00000010, "WATCHDOG" },
920 {}
921};
922
109c2f2f 923static const struct nvkm_bitfield gk104_sked_error[] = {
caf2be8a 924 { 0x00000040, "CTA_RESUME" },
109c2f2f
BS		 925 { 0x00000080, "CONSTANT_BUFFER_SIZE" },
926 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
927 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
928 { 0x00000800, "WARP_CSTACK_SIZE" },
929 { 0x00001000, "TOTAL_TEMP_SIZE" },
930 { 0x00002000, "REGISTER_COUNT" },
931 { 0x00040000, "TOTAL_THREADS" },
932 { 0x00100000, "PROGRAM_OFFSET" },
933 { 0x00200000, "SHARED_MEMORY_SIZE" },
caf2be8a
IM		 934 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
935 { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
109c2f2f
BS		 936 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
937 { 0x04000000, "TOTAL_REGISTER_COUNT" },
30f4e087
BS		 938 {}
939};
940
109c2f2f
BS		 941static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
942 { 0x00000002, "RT_PITCH_OVERRUN" },
943 { 0x00000010, "RT_WIDTH_OVERRUN" },
944 { 0x00000020, "RT_HEIGHT_OVERRUN" },
945 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
946 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
947 { 0x00000400, "RT_LINEAR_MISMATCH" },
30f4e087
BS		 948 {}
949};
950
ebb945a9 951static void
bfee3f3d 952gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
ebb945a9 953{
109c2f2f
BS		 954 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
955 struct nvkm_device *device = subdev->device;
956 char error[128];
30f4e087 957 u32 trap[4];
ebb945a9 958
109c2f2f 959 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
276836d4
BS		 960 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
961 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
962 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
ebb945a9 963
109c2f2f 964 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
30f4e087 965
109c2f2f
BS		 966 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
967 "format = %x, storage type = %x\n",
968 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
969 (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
276836d4 970 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
ebb945a9
BS		 971}
972
e3c71eb2 973static const struct nvkm_enum gf100_mp_warp_error[] = {
383d0a41
BS		 974 { 0x01, "STACK_ERROR" },
975 { 0x02, "API_STACK_ERROR" },
976 { 0x03, "RET_EMPTY_STACK_ERROR" },
977 { 0x04, "PC_WRAP" },
fec43a72 978 { 0x05, "MISALIGNED_PC" },
383d0a41
BS		 979 { 0x06, "PC_OVERFLOW" },
980 { 0x07, "MISALIGNED_IMMC_ADDR" },
981 { 0x08, "MISALIGNED_REG" },
982 { 0x09, "ILLEGAL_INSTR_ENCODING" },
983 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
984 { 0x0b, "ILLEGAL_INSTR_PARAM" },
985 { 0x0c, "INVALID_CONST_ADDR" },
986 { 0x0d, "OOR_REG" },
987 { 0x0e, "OOR_ADDR" },
988 { 0x0f, "MISALIGNED_ADDR" },
3988f645 989 { 0x10, "INVALID_ADDR_SPACE" },
383d0a41
BS		 990 { 0x11, "ILLEGAL_INSTR_PARAM2" },
991 { 0x12, "INVALID_CONST_ADDR_LDC" },
992 { 0x13, "GEOMETRY_SM_ERROR" },
993 { 0x14, "DIVERGENT" },
994 { 0x15, "WARP_EXIT" },
fec43a72
BS		 995 {}
996};
997
e3c71eb2 998static const struct nvkm_bitfield gf100_mp_global_error[] = {
383d0a41
BS		 999 { 0x00000001, "SM_TO_SM_FAULT" },
1000 { 0x00000002, "L1_ERROR" },
fec43a72 1001 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
383d0a41
BS		 1002 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1003 { 0x00000010, "BPT_INT" },
1004 { 0x00000020, "BPT_PAUSE" },
1005 { 0x00000040, "SINGLE_STEP_COMPLETE" },
1006 { 0x20000000, "ECC_SEC_ERROR" },
1007 { 0x40000000, "ECC_DED_ERROR" },
1008 { 0x80000000, "TIMEOUT" },
fec43a72
BS		 1009 {}
1010};
1011
1012static void
bfee3f3d 1013gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
fec43a72 1014{
109c2f2f
BS		 1015 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1016 struct nvkm_device *device = subdev->device;
276836d4
BS		 1017 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1018 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
109c2f2f
BS		 1019 const struct nvkm_enum *warp;
1020 char glob[128];
fec43a72 1021
109c2f2f
BS		 1022 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
1023 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
1024
1025 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
1026 "global %08x [%s] warp %04x [%s]\n",
1027 gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
fec43a72 1028
276836d4
BS		 1029 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1030 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
fec43a72
BS		 1031}
1032
f73221e4 1033static void
bfee3f3d 1034gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
f73221e4 1035{
109c2f2f
BS		 1036 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1037 struct nvkm_device *device = subdev->device;
276836d4 1038 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
f73221e4
BS		 1039
1040 if (stat & 0x00000001) {
276836d4 1041 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
109c2f2f 1042 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
276836d4 1043 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
f73221e4
BS		 1044 stat &= ~0x00000001;
1045 }
1046
1047 if (stat & 0x00000002) {
bfee3f3d 1048 gf100_gr_trap_mp(gr, gpc, tpc);
f73221e4
BS		 1049 stat &= ~0x00000002;
1050 }
1051
1052 if (stat & 0x00000004) {
276836d4 1053 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
109c2f2f 1054 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
276836d4 1055 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
f73221e4
BS		 1056 stat &= ~0x00000004;
1057 }
1058
1059 if (stat & 0x00000008) {
276836d4 1060 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
109c2f2f 1061 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
276836d4 1062 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
f73221e4
BS		 1063 stat &= ~0x00000008;
1064 }
1065
64373e4b
BS		 1066 if (stat & 0x00000010) {
1067 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1068 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
1069 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1070 stat &= ~0x00000010;
1071 }
1072
f73221e4 1073 if (stat) {
109c2f2f 1074 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
f73221e4
BS		 1075 }
1076}
1077
1078static void
bfee3f3d 1079gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
f73221e4 1080{
109c2f2f
BS		 1081 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1082 struct nvkm_device *device = subdev->device;
276836d4 1083 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
f73221e4
BS		 1084 int tpc;
1085
1086 if (stat & 0x00000001) {
bfee3f3d 1087 gf100_gr_trap_gpc_rop(gr, gpc);
f73221e4
BS		 1088 stat &= ~0x00000001;
1089 }
1090
1091 if (stat & 0x00000002) {
276836d4 1092 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
109c2f2f 1093 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
276836d4 1094 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
f73221e4
BS		 1095 stat &= ~0x00000002;
1096 }
1097
1098 if (stat & 0x00000004) {
276836d4 1099 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
109c2f2f 1100 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
276836d4 1101 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
f73221e4
BS		 1102 stat &= ~0x00000004;
1103 }
1104
1105 if (stat & 0x00000008) {
276836d4 1106 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
109c2f2f 1107 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
276836d4 1108 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
f73221e4
BS		 1109 stat &= ~0x00000009;
1110 }
1111
bfee3f3d 1112 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
f73221e4
BS		 1113 u32 mask = 0x00010000 << tpc;
1114 if (stat & mask) {
bfee3f3d 1115 gf100_gr_trap_tpc(gr, gpc, tpc);
276836d4 1116 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
f73221e4
BS		 1117 stat &= ~mask;
1118 }
1119 }
1120
1121 if (stat) {
109c2f2f 1122 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
f73221e4
BS		 1123 }
1124}
1125
1126static void
bfee3f3d 1127gf100_gr_trap_intr(struct gf100_gr *gr)
f73221e4 1128{
109c2f2f
BS		 1129 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1130 struct nvkm_device *device = subdev->device;
caf2be8a 1131 char error[128];
276836d4 1132 u32 trap = nvkm_rd32(device, 0x400108);
109c2f2f 1133 int rop, gpc;
f73221e4
BS		 1134
1135 if (trap & 0x00000001) {
276836d4 1136 u32 stat = nvkm_rd32(device, 0x404000);
caf2be8a
IM		 1137
1138 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
1139 stat & 0x3fffffff);
1140 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
276836d4
BS		 1141 nvkm_wr32(device, 0x404000, 0xc0000000);
1142 nvkm_wr32(device, 0x400108, 0x00000001);
f73221e4
BS		 1143 trap &= ~0x00000001;
1144 }
1145
1146 if (trap & 0x00000002) {
276836d4 1147 u32 stat = nvkm_rd32(device, 0x404600);
caf2be8a
IM		 1148
1149 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
1150 stat & 0x3fffffff);
1151 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
1152
276836d4
BS		 1153 nvkm_wr32(device, 0x404600, 0xc0000000);
1154 nvkm_wr32(device, 0x400108, 0x00000002);
f73221e4
BS		 1155 trap &= ~0x00000002;
1156 }
1157
1158 if (trap & 0x00000008) {
276836d4 1159 u32 stat = nvkm_rd32(device, 0x408030);
caf2be8a 1160
1894054d 1161 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
caf2be8a
IM		 1162 stat & 0x3fffffff);
1163 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
276836d4
BS		 1164 nvkm_wr32(device, 0x408030, 0xc0000000);
1165 nvkm_wr32(device, 0x400108, 0x00000008);
f73221e4
BS		 1166 trap &= ~0x00000008;
1167 }
1168
1169 if (trap & 0x00000010) {
276836d4 1170 u32 stat = nvkm_rd32(device, 0x405840);
caf2be8a
IM		 1171 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
1172 stat, stat & 0xffffff, (stat >> 24) & 0x3f);
276836d4
BS		 1173 nvkm_wr32(device, 0x405840, 0xc0000000);
1174 nvkm_wr32(device, 0x400108, 0x00000010);
f73221e4
BS		 1175 trap &= ~0x00000010;
1176 }
1177
1178 if (trap & 0x00000040) {
276836d4 1179 u32 stat = nvkm_rd32(device, 0x40601c);
caf2be8a
IM		 1180
1181 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
1182 stat & 0x3fffffff);
1183 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
1184
276836d4
BS		 1185 nvkm_wr32(device, 0x40601c, 0xc0000000);
1186 nvkm_wr32(device, 0x400108, 0x00000040);
f73221e4
BS		 1187 trap &= ~0x00000040;
1188 }
1189
1190 if (trap & 0x00000080) {
276836d4 1191 u32 stat = nvkm_rd32(device, 0x404490);
caf2be8a
IM		 1192 u32 pc = nvkm_rd32(device, 0x404494);
1193 u32 op = nvkm_rd32(device, 0x40449c);
1194
1195 nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
1196 stat & 0x1fffffff);
1197 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
1198 stat, error, pc & 0x7ff,
1199 (pc & 0x10000000) ? "" : " (invalid)",
1200 op);
1201
276836d4
BS		 1202 nvkm_wr32(device, 0x404490, 0xc0000000);
1203 nvkm_wr32(device, 0x400108, 0x00000080);
f73221e4
BS		 1204 trap &= ~0x00000080;
1205 }
1206
30f4e087 1207 if (trap & 0x00000100) {
109c2f2f 1208 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
30f4e087 1209
caf2be8a
IM		 1210 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
1211 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
30f4e087 1212
109c2f2f 1213 if (stat)
276836d4
BS		 1214 nvkm_wr32(device, 0x407020, 0x40000000);
1215 nvkm_wr32(device, 0x400108, 0x00000100);
30f4e087
BS		 1216 trap &= ~0x00000100;
1217 }
1218
f73221e4 1219 if (trap & 0x01000000) {
276836d4 1220 u32 stat = nvkm_rd32(device, 0x400118);
bfee3f3d 1221 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
f73221e4
BS		 1222 u32 mask = 0x00000001 << gpc;
1223 if (stat & mask) {
bfee3f3d 1224 gf100_gr_trap_gpc(gr, gpc);
276836d4 1225 nvkm_wr32(device, 0x400118, mask);
f73221e4
BS		 1226 stat &= ~mask;
1227 }
1228 }
276836d4 1229 nvkm_wr32(device, 0x400108, 0x01000000);
f73221e4
BS		 1230 trap &= ~0x01000000;
1231 }
1232
1233 if (trap & 0x02000000) {
bfee3f3d 1234 for (rop = 0; rop < gr->rop_nr; rop++) {
276836d4
BS		 1235 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1236 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
109c2f2f 1237 nvkm_error(subdev, "ROP%d %08x %08x\n",
f73221e4 1238 rop, statz, statc);
276836d4
BS		 1239 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1240 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
f73221e4 1241 }
276836d4 1242 nvkm_wr32(device, 0x400108, 0x02000000);
f73221e4
BS		 1243 trap &= ~0x02000000;
1244 }
1245
1246 if (trap) {
109c2f2f 1247 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
276836d4 1248 nvkm_wr32(device, 0x400108, trap);
f73221e4
BS		 1249 }
1250}
1251
30f4e087 1252static void
bfee3f3d 1253gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
30f4e087 1254{
109c2f2f
BS		 1255 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1256 struct nvkm_device *device = subdev->device;
1257 nvkm_error(subdev, "%06x - done %08x\n", base,
1258 nvkm_rd32(device, base + 0x400));
1259 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1260 nvkm_rd32(device, base + 0x800),
1261 nvkm_rd32(device, base + 0x804),
1262 nvkm_rd32(device, base + 0x808),
1263 nvkm_rd32(device, base + 0x80c));
1264 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1265 nvkm_rd32(device, base + 0x810),
1266 nvkm_rd32(device, base + 0x814),
1267 nvkm_rd32(device, base + 0x818),
1268 nvkm_rd32(device, base + 0x81c));
30f4e087
BS		 1269}
1270
1271void
bfee3f3d 1272gf100_gr_ctxctl_debug(struct gf100_gr *gr)
30f4e087 1273{
276836d4
BS		 1274 struct nvkm_device *device = gr->base.engine.subdev.device;
1275 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
30f4e087
BS		 1276 u32 gpc;
1277
bfee3f3d 1278 gf100_gr_ctxctl_debug_unit(gr, 0x409000);
30f4e087 1279 for (gpc = 0; gpc < gpcnr; gpc++)
bfee3f3d 1280 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
30f4e087
BS		 1281}
1282
1283static void
bfee3f3d 1284gf100_gr_ctxctl_isr(struct gf100_gr *gr)
30f4e087 1285{
109c2f2f
BS		 1286 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1287 struct nvkm_device *device = subdev->device;
276836d4 1288 u32 stat = nvkm_rd32(device, 0x409c18);
30f4e087 1289
732be807 1290 if (!gr->firmware && (stat & 0x00000001)) {
276836d4 1291 u32 code = nvkm_rd32(device, 0x409814);
23f67841 1292 if (code == E_BAD_FWMTHD) {
276836d4
BS		 1293 u32 class = nvkm_rd32(device, 0x409808);
1294 u32 addr = nvkm_rd32(device, 0x40980c);
23f67841
BS		 1295 u32 subc = (addr & 0x00070000) >> 16;
1296 u32 mthd = (addr & 0x00003ffc);
276836d4 1297 u32 data = nvkm_rd32(device, 0x409810);
23f67841 1298
109c2f2f
BS		 1299 nvkm_error(subdev, "FECS MTHD subc %d class %04x "
1300 "mthd %04x data %08x\n",
1301 subc, class, mthd, data);
23f67841 1302 } else {
109c2f2f 1303 nvkm_error(subdev, "FECS ucode error %d\n", code);
23f67841 1304 }
48dac935
BS		 1305 nvkm_wr32(device, 0x409c20, 0x00000001);
1306 stat &= ~0x00000001;
23f67841 1307 }
30f4e087 1308
732be807 1309 if (!gr->firmware && (stat & 0x00080000)) {
109c2f2f 1310 nvkm_error(subdev, "FECS watchdog timeout\n");
bfee3f3d 1311 gf100_gr_ctxctl_debug(gr);
276836d4 1312 nvkm_wr32(device, 0x409c20, 0x00080000);
23f67841
BS		 1313 stat &= ~0x00080000;
1314 }
1315
1316 if (stat) {
109c2f2f 1317 nvkm_error(subdev, "FECS %08x\n", stat);
bfee3f3d 1318 gf100_gr_ctxctl_debug(gr);
276836d4 1319 nvkm_wr32(device, 0x409c20, stat);
23f67841 1320 }
30f4e087
BS		 1321}
1322
ebb945a9 1323static void
c85ee6ca 1324gf100_gr_intr(struct nvkm_gr *base)
ebb945a9 1325{
c85ee6ca
BS		 1326 struct gf100_gr *gr = gf100_gr(base);
1327 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1328 struct nvkm_device *device = subdev->device;
a65955e1
BS		 1329 struct nvkm_fifo_chan *chan;
1330 unsigned long flags;
276836d4
BS		 1331 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1332 u32 stat = nvkm_rd32(device, 0x400100);
1333 u32 addr = nvkm_rd32(device, 0x400704);
ebb945a9
BS		 1334 u32 mthd = (addr & 0x00003ffc);
1335 u32 subc = (addr & 0x00070000) >> 16;
276836d4
BS		 1336 u32 data = nvkm_rd32(device, 0x400708);
1337 u32 code = nvkm_rd32(device, 0x400110);
91c772ec 1338 u32 class;
8f0649b5
BS		 1339 const char *name = "unknown";
1340 int chid = -1;
72a14827 1341
a65955e1 1342 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);
8f0649b5
BS		 1343 if (chan) {
1344 name = chan->object.client->name;
1345 chid = chan->chid;
1346 }
a65955e1 1347
c85ee6ca 1348 if (device->card_type < NV_E0 || subc < 4)
276836d4 1349 class = nvkm_rd32(device, 0x404200 + (subc * 4));
91c772ec
BS		 1350 else
1351 class = 0x0000;
1352
c6a7b026
LP		 1353 if (stat & 0x00000001) {
1354 /*
1355 * notifier interrupt, only needed for cyclestats
1356 * can be safely ignored
1357 */
276836d4 1358 nvkm_wr32(device, 0x400100, 0x00000001);
c6a7b026
LP		 1359 stat &= ~0x00000001;
1360 }
1361
ebb945a9 1362 if (stat & 0x00000010) {
a65955e1 1363 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
109c2f2f
BS		 1364 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
1365 "subc %d class %04x mthd %04x data %08x\n",
8f0649b5
BS		 1366 chid, inst << 12, name, subc,
1367 class, mthd, data);
ebb945a9 1368 }
276836d4 1369 nvkm_wr32(device, 0x400100, 0x00000010);
ebb945a9
BS		 1370 stat &= ~0x00000010;
1371 }
1372
1373 if (stat & 0x00000020) {
109c2f2f
BS		 1374 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
1375 "subc %d class %04x mthd %04x data %08x\n",
8f0649b5 1376 chid, inst << 12, name, subc, class, mthd, data);
276836d4 1377 nvkm_wr32(device, 0x400100, 0x00000020);
ebb945a9
BS		 1378 stat &= ~0x00000020;
1379 }
1380
1381 if (stat & 0x00100000) {
109c2f2f
BS		 1382 const struct nvkm_enum *en =
1383 nvkm_enum_find(nv50_data_error_names, code);
1384 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
1385 "subc %d class %04x mthd %04x data %08x\n",
1386 code, en ? en->name : "", chid, inst << 12,
8f0649b5 1387 name, subc, class, mthd, data);
276836d4 1388 nvkm_wr32(device, 0x400100, 0x00100000);
ebb945a9
BS		 1389 stat &= ~0x00100000;
1390 }
1391
1392 if (stat & 0x00200000) {
109c2f2f 1393 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
8f0649b5 1394 chid, inst << 12, name);
bfee3f3d 1395 gf100_gr_trap_intr(gr);
276836d4 1396 nvkm_wr32(device, 0x400100, 0x00200000);
ebb945a9
BS		 1397 stat &= ~0x00200000;
1398 }
1399
1400 if (stat & 0x00080000) {
bfee3f3d 1401 gf100_gr_ctxctl_isr(gr);
276836d4 1402 nvkm_wr32(device, 0x400100, 0x00080000);
ebb945a9
BS		 1403 stat &= ~0x00080000;
1404 }
1405
1406 if (stat) {
109c2f2f 1407 nvkm_error(subdev, "intr %08x\n", stat);
276836d4 1408 nvkm_wr32(device, 0x400100, stat);
ebb945a9
BS		 1409 }
1410
276836d4 1411 nvkm_wr32(device, 0x400500, 0x00010001);
a65955e1 1412 nvkm_fifo_chan_put(device->fifo, flags, &chan);
ebb945a9
BS		 1413}
1414
e08a1d97 1415static void
89cd6e20 1416gf100_gr_init_fw(struct nvkm_falcon *falcon,
e3c71eb2 1417 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
ebb945a9 1418{
89cd6e20
AC		 1419 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
1420 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
966a5b7d
BS		 1421}
1422
a32b2ffb 1423static void
bfee3f3d 1424gf100_gr_init_csdata(struct gf100_gr *gr,
e3c71eb2
BS		 1425 const struct gf100_gr_pack *pack,
1426 u32 falcon, u32 starstar, u32 base)
a32b2ffb 1427{
276836d4 1428 struct nvkm_device *device = gr->base.engine.subdev.device;
e3c71eb2
BS		 1429 const struct gf100_gr_pack *iter;
1430 const struct gf100_gr_init *init;
c33b1e8c 1431 u32 addr = ~0, prev = ~0, xfer = 0;
a32b2ffb
BS		 1432 u32 star, temp;
1433
276836d4
BS		 1434 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1435 star = nvkm_rd32(device, falcon + 0x01c4);
1436 temp = nvkm_rd32(device, falcon + 0x01c4);
a32b2ffb
BS		 1437 if (temp > star)
1438 star = temp;
276836d4 1439 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
a32b2ffb 1440
c33b1e8c
BS		 1441 pack_for_each_init(init, iter, pack) {
1442 u32 head = init->addr - base;
1443 u32 tail = head + init->count * init->pitch;
1444 while (head < tail) {
1445 if (head != prev + 4 || xfer >= 32) {
1446 if (xfer) {
1447 u32 data = ((--xfer << 26) | addr);
276836d4 1448 nvkm_wr32(device, falcon + 0x01c4, data);
c33b1e8c
BS		 1449 star += 4;
1450 }
1451 addr = head;
1452 xfer = 0;
a32b2ffb 1453 }
c33b1e8c
BS		 1454 prev = head;
1455 xfer = xfer + 1;
1456 head = head + init->pitch;
a32b2ffb 1457 }
c33b1e8c 1458 }
a32b2ffb 1459
276836d4
BS		 1460 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1461 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1462 nvkm_wr32(device, falcon + 0x01c4, star + 4);
a32b2ffb
BS		 1463}
1464
0296b5d9
AC		 1465/* Initialize context from an external (secure or not) firmware */
1466static int
1467gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
966a5b7d 1468{
109c2f2f
BS		 1469 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1470 struct nvkm_device *device = subdev->device;
c9469aae 1471 struct nvkm_secboot *sb = device->secboot;
598a8148 1472 u32 secboot_mask = 0;
ebb945a9 1473
0296b5d9
AC		 1474 /* load fuc microcode */
1475 nvkm_mc_unk260(device, 0);
c9469aae 1476
0296b5d9
AC		 1477 /* securely-managed falcons must be reset using secure boot */
1478 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
598a8148 1479 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS);
0296b5d9 1480 else
89cd6e20 1481 gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
7fcab839 1482
0296b5d9 1483 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
598a8148 1484 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS);
0296b5d9 1485 else
89cd6e20 1486 gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
598a8148
AC		 1487
1488 if (secboot_mask != 0) {
1489 int ret = nvkm_secboot_reset(sb, secboot_mask);
1490 if (ret)
1491 return ret;
1492 }
c9469aae 1493
0296b5d9
AC		 1494 nvkm_mc_unk260(device, 1);
1495
1496 /* start both of them running */
1497 nvkm_wr32(device, 0x409840, 0xffffffff);
1498 nvkm_wr32(device, 0x41a10c, 0x00000000);
1499 nvkm_wr32(device, 0x40910c, 0x00000000);
1500
89cd6e20
AC		 1501 nvkm_falcon_start(gr->gpccs);
1502 nvkm_falcon_start(gr->fecs);
1503
0296b5d9
AC		 1504 if (nvkm_msec(device, 2000,
1505 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1506 break;
1507 ) < 0)
1508 return -EBUSY;
1509
1510 nvkm_wr32(device, 0x409840, 0xffffffff);
1511 nvkm_wr32(device, 0x409500, 0x7fffffff);
1512 nvkm_wr32(device, 0x409504, 0x00000021);
1513
1514 nvkm_wr32(device, 0x409840, 0xffffffff);
1515 nvkm_wr32(device, 0x409500, 0x00000000);
1516 nvkm_wr32(device, 0x409504, 0x00000010);
1517 if (nvkm_msec(device, 2000,
1518 if ((gr->size = nvkm_rd32(device, 0x409800)))
1519 break;
1520 ) < 0)
1521 return -EBUSY;
1522
1523 nvkm_wr32(device, 0x409840, 0xffffffff);
1524 nvkm_wr32(device, 0x409500, 0x00000000);
1525 nvkm_wr32(device, 0x409504, 0x00000016);
1526 if (nvkm_msec(device, 2000,
1527 if (nvkm_rd32(device, 0x409800))
1528 break;
1529 ) < 0)
1530 return -EBUSY;
bfee3f3d 1531
0296b5d9
AC		 1532 nvkm_wr32(device, 0x409840, 0xffffffff);
1533 nvkm_wr32(device, 0x409500, 0x00000000);
1534 nvkm_wr32(device, 0x409504, 0x00000025);
1535 if (nvkm_msec(device, 2000,
1536 if (nvkm_rd32(device, 0x409800))
1537 break;
1538 ) < 0)
1539 return -EBUSY;
bfee3f3d 1540
0296b5d9
AC		 1541 if (device->chipset >= 0xe0) {
1542 nvkm_wr32(device, 0x409800, 0x00000000);
1543 nvkm_wr32(device, 0x409500, 0x00000001);
1544 nvkm_wr32(device, 0x409504, 0x00000030);
c4584adc 1545 if (nvkm_msec(device, 2000,
0296b5d9 1546 if (nvkm_rd32(device, 0x409800))
c4584adc
BS		 1547 break;
1548 ) < 0)
30f4e087 1549 return -EBUSY;
0411de85 1550
0296b5d9
AC		 1551 nvkm_wr32(device, 0x409810, 0xb00095c8);
1552 nvkm_wr32(device, 0x409800, 0x00000000);
1553 nvkm_wr32(device, 0x409500, 0x00000001);
1554 nvkm_wr32(device, 0x409504, 0x00000031);
c4584adc
BS		 1555 if (nvkm_msec(device, 2000,
1556 if (nvkm_rd32(device, 0x409800))
1557 break;
1558 ) < 0)
ac1499d9 1559 return -EBUSY;
ac1499d9 1560
0296b5d9
AC		 1561 nvkm_wr32(device, 0x409810, 0x00080420);
1562 nvkm_wr32(device, 0x409800, 0x00000000);
1563 nvkm_wr32(device, 0x409500, 0x00000001);
1564 nvkm_wr32(device, 0x409504, 0x00000032);
c4584adc
BS		 1565 if (nvkm_msec(device, 2000,
1566 if (nvkm_rd32(device, 0x409800))
1567 break;
1568 ) < 0)
ac1499d9 1569 return -EBUSY;
ac1499d9 1570
0296b5d9
AC		 1571 nvkm_wr32(device, 0x409614, 0x00000070);
1572 nvkm_wr32(device, 0x409614, 0x00000770);
1573 nvkm_wr32(device, 0x40802c, 0x00000001);
1574 }
30f4e087 1575
0296b5d9
AC		 1576 if (gr->data == NULL) {
1577 int ret = gf100_grctx_generate(gr);
1578 if (ret) {
1579 nvkm_error(subdev, "failed to construct context\n");
1580 return ret;
30f4e087 1581 }
0296b5d9 1582 }
30f4e087 1583
0296b5d9
AC		 1584 return 0;
1585}
1586
1587static int
1588gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
1589{
1590 const struct gf100_grctx_func *grctx = gr->func->grctx;
1591 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1592 struct nvkm_device *device = subdev->device;
ebb945a9 1593
c85ee6ca 1594 if (!gr->func->fecs.ucode) {
96616b4c 1595 return -ENOSYS;
0411de85 1596 }
966a5b7d 1597
ac1499d9 1598 /* load HUB microcode */
d3981190 1599 nvkm_mc_unk260(device, 0);
89cd6e20
AC		 1600 nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
1601 gr->func->fecs.ucode->data.size, 0);
1602 nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
1603 gr->func->fecs.ucode->code.size, 0, 0, false);
ac1499d9
BS		 1604
1605 /* load GPC microcode */
89cd6e20
AC		 1606 nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
1607 gr->func->gpccs.ucode->data.size, 0);
1608 nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
1609 gr->func->gpccs.ucode->code.size, 0, 0, false);
d3981190 1610 nvkm_mc_unk260(device, 1);
966a5b7d 1611
c33b1e8c 1612 /* load register lists */
27f3d6cf
BS		 1613 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
1614 gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000);
1615 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
1616 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
a32b2ffb 1617
ac1499d9 1618 /* start HUB ucode running, it'll init the GPCs */
276836d4
BS		 1619 nvkm_wr32(device, 0x40910c, 0x00000000);
1620 nvkm_wr32(device, 0x409100, 0x00000002);
c4584adc
BS		 1621 if (nvkm_msec(device, 2000,
1622 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1623 break;
1624 ) < 0) {
bfee3f3d 1625 gf100_gr_ctxctl_debug(gr);
966a5b7d
BS		 1626 return -EBUSY;
1627 }
966a5b7d 1628
276836d4 1629 gr->size = nvkm_rd32(device, 0x409804);
bfee3f3d
BS		 1630 if (gr->data == NULL) {
1631 int ret = gf100_grctx_generate(gr);
ac1499d9 1632 if (ret) {
109c2f2f 1633 nvkm_error(subdev, "failed to construct context\n");
ac1499d9
BS		 1634 return ret;
1635 }
966a5b7d
BS		 1636 }
1637
1638 return 0;
4b223eef
BS		 1639}
1640
0296b5d9
AC		 1641int
1642gf100_gr_init_ctxctl(struct gf100_gr *gr)
1643{
1644 int ret;
1645
1646 if (gr->firmware)
1647 ret = gf100_gr_init_ctxctl_ext(gr);
1648 else
1649 ret = gf100_gr_init_ctxctl_int(gr);
1650
1651 return ret;
1652}
1653
c85ee6ca
BS		 1654static int
1655gf100_gr_oneinit(struct nvkm_gr *base)
1656{
1657 struct gf100_gr *gr = gf100_gr(base);
9e439757
AC		 1658 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1659 struct nvkm_device *device = subdev->device;
99c59172 1660 int i, j;
9e439757
AC		 1661 int ret;
1662
1663 ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
1664 if (ret)
1665 return ret;
1666
1667 ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
1668 if (ret)
1669 return ret;
c85ee6ca
BS		 1670
1671 nvkm_pmu_pgob(device->pmu, false);
1672
64cb5a31
BS		 1673 gr->rop_nr = gr->func->rops(gr);
1674 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
c85ee6ca
BS		 1675 for (i = 0; i < gr->gpc_nr; i++) {
1676 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
1677 gr->tpc_total += gr->tpc_nr[i];
1678 gr->ppc_nr[i] = gr->func->ppc_nr;
1679 for (j = 0; j < gr->ppc_nr[i]; j++) {
1680 u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
2fb2b3c6
BS		 1681 if (mask)
1682 gr->ppc_mask[i] |= (1 << j);
c85ee6ca
BS		 1683 gr->ppc_tpc_nr[i][j] = hweight8(mask);
1684 }
1685 }
1686
1687 /*XXX: these need figuring out... though it might not even matter */
1688 switch (device->chipset) {
1689 case 0xc0:
1690 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
5ec3def7 1691 gr->screen_tile_row_offset = 0x07;
c85ee6ca
BS		 1692 } else
1693 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
5ec3def7 1694 gr->screen_tile_row_offset = 0x05;
c85ee6ca
BS		 1695 } else
1696 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
5ec3def7 1697 gr->screen_tile_row_offset = 0x06;
c85ee6ca
BS		 1698 }
1699 break;
1700 case 0xc3: /* 450, 4/0/0/0, 2 */
5ec3def7 1701 gr->screen_tile_row_offset = 0x03;
c85ee6ca
BS		 1702 break;
1703 case 0xc4: /* 460, 3/4/0/0, 4 */
5ec3def7 1704 gr->screen_tile_row_offset = 0x01;
c85ee6ca
BS		 1705 break;
1706 case 0xc1: /* 2/0/0/0, 1 */
5ec3def7 1707 gr->screen_tile_row_offset = 0x01;
c85ee6ca
BS		 1708 break;
1709 case 0xc8: /* 4/4/3/4, 5 */
5ec3def7 1710 gr->screen_tile_row_offset = 0x06;
c85ee6ca
BS		 1711 break;
1712 case 0xce: /* 4/4/0/0, 4 */
5ec3def7 1713 gr->screen_tile_row_offset = 0x03;
c85ee6ca
BS		 1714 break;
1715 case 0xcf: /* 4/0/0/0, 3 */
5ec3def7 1716 gr->screen_tile_row_offset = 0x03;
c85ee6ca
BS		 1717 break;
1718 case 0xd7:
1719 case 0xd9: /* 1/0/0/0, 1 */
1720 case 0xea: /* gk20a */
1721 case 0x12b: /* gm20b */
5ec3def7 1722 gr->screen_tile_row_offset = 0x01;
c85ee6ca
BS		 1723 break;
1724 }
1725
1726 return 0;
1727}
1728
e08a1d97 1729static int
c85ee6ca
BS		 1730gf100_gr_init_(struct nvkm_gr *base)
1731{
1732 struct gf100_gr *gr = gf100_gr(base);
89cd6e20
AC		 1733 struct nvkm_subdev *subdev = &base->engine.subdev;
1734 u32 ret;
1735
c85ee6ca 1736 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
89cd6e20
AC		 1737
1738 ret = nvkm_falcon_get(gr->fecs, subdev);
1739 if (ret)
1740 return ret;
1741
1742 ret = nvkm_falcon_get(gr->gpccs, subdev);
1743 if (ret)
1744 return ret;
1745
c85ee6ca
BS		 1746 return gr->func->init(gr);
1747}
1748
89cd6e20
AC		 1749static int
1750gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
1751{
1752 struct gf100_gr *gr = gf100_gr(base);
1753 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1754 nvkm_falcon_put(gr->gpccs, subdev);
1755 nvkm_falcon_put(gr->fecs, subdev);
1756 return 0;
1757}
1758
c85ee6ca
BS		 1759void
1760gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1761{
1762 kfree(fuc->data);
1763 fuc->data = NULL;
1764}
1765
336c4652
AC		 1766static void
1767gf100_gr_dtor_init(struct gf100_gr_pack *pack)
1768{
1769 vfree(pack);
1770}
1771
c85ee6ca
BS		 1772void *
1773gf100_gr_dtor(struct nvkm_gr *base)
1774{
1775 struct gf100_gr *gr = gf100_gr(base);
1776
1777 if (gr->func->dtor)
1778 gr->func->dtor(gr);
1779 kfree(gr->data);
1780
89cd6e20
AC		 1781 nvkm_falcon_del(&gr->gpccs);
1782 nvkm_falcon_del(&gr->fecs);
1783
c85ee6ca
BS		 1784 gf100_gr_dtor_fw(&gr->fuc409c);
1785 gf100_gr_dtor_fw(&gr->fuc409d);
1786 gf100_gr_dtor_fw(&gr->fuc41ac);
1787 gf100_gr_dtor_fw(&gr->fuc41ad);
1788
336c4652
AC		 1789 gf100_gr_dtor_init(gr->fuc_bundle);
1790 gf100_gr_dtor_init(gr->fuc_method);
1791 gf100_gr_dtor_init(gr->fuc_sw_ctx);
1792 gf100_gr_dtor_init(gr->fuc_sw_nonctx);
1793
c85ee6ca
BS		 1794 return gr;
1795}
1796
1797static const struct nvkm_gr_func
1798gf100_gr_ = {
1799 .dtor = gf100_gr_dtor,
1800 .oneinit = gf100_gr_oneinit,
1801 .init = gf100_gr_init_,
89cd6e20 1802 .fini = gf100_gr_fini_,
c85ee6ca
BS		 1803 .intr = gf100_gr_intr,
1804 .units = gf100_gr_units,
1805 .chan_new = gf100_gr_chan_new,
1806 .object_get = gf100_gr_object_get,
6845c313 1807 .chsw_load = gf100_gr_chsw_load,
c85ee6ca
BS		 1808};
1809
e137040e
AC		 1810int
1811gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname,
1812 struct gf100_gr_fuc *fuc, int ret)
1813{
1814 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1815 struct nvkm_device *device = subdev->device;
1816 const struct firmware *fw;
1817 char f[32];
1818
1819 /* see if this firmware has a legacy path */
1820 if (!strcmp(fwname, "fecs_inst"))
1821 fwname = "fuc409c";
1822 else if (!strcmp(fwname, "fecs_data"))
1823 fwname = "fuc409d";
1824 else if (!strcmp(fwname, "gpccs_inst"))
1825 fwname = "fuc41ac";
1826 else if (!strcmp(fwname, "gpccs_data"))
1827 fwname = "fuc41ad";
1828 else {
1829 /* nope, let's just return the error we got */
1830 nvkm_error(subdev, "failed to load %s\n", fwname);
1831 return ret;
1832 }
1833
1834 /* yes, try to load from the legacy path */
1835 nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname);
1836
1837 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1838 ret = request_firmware(&fw, f, device->dev);
1839 if (ret) {
1840 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1841 ret = request_firmware(&fw, f, device->dev);
1842 if (ret) {
1843 nvkm_error(subdev, "failed to load %s\n", fwname);
1844 return ret;
1845 }
1846 }
1847
1848 fuc->size = fw->size;
1849 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1850 release_firmware(fw);
1851 return (fuc->data != NULL) ? 0 : -ENOMEM;
1852}
1853
c85ee6ca
BS		 1854int
1855gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1856 struct gf100_gr_fuc *fuc)
1857{
1858 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1859 struct nvkm_device *device = subdev->device;
1860 const struct firmware *fw;
c85ee6ca 1861 int ret;
c85ee6ca 1862
33bcb4c3 1863 ret = nvkm_firmware_get(device, fwname, &fw);
46bda4f4
BS		 1864 if (ret) {
1865 ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret);
1866 if (ret)
1867 return -ENODEV;
1868 return 0;
1869 }
c85ee6ca
BS		 1870
1871 fuc->size = fw->size;
1872 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
33bcb4c3 1873 nvkm_firmware_put(fw);
c85ee6ca
BS		 1874 return (fuc->data != NULL) ? 0 : -ENOMEM;
1875}
1876
1877int
1878gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
1879 int index, struct gf100_gr *gr)
1880{
c85ee6ca
BS		 1881 gr->func = func;
1882 gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
1883 func->fecs.ucode == NULL);
1884
9e439757
AC		 1885 return nvkm_gr_ctor(&gf100_gr_, device, index,
1886 gr->firmware || func->fecs.ucode != NULL,
1887 &gr->base);
c85ee6ca
BS		 1888}
1889
30f4e087 1890int
c85ee6ca
BS		 1891gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
1892 int index, struct nvkm_gr **pgr)
1893{
1894 struct gf100_gr *gr;
18cd5bc8
AC		 1895 int ret;
1896
c85ee6ca
BS		 1897 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
1898 return -ENOMEM;
1899 *pgr = &gr->base;
18cd5bc8
AC		 1900
1901 ret = gf100_gr_ctor(func, device, index, gr);
1902 if (ret)
1903 return ret;
1904
1905 if (gr->firmware) {
1906 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
1907 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
1908 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
1909 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
1910 return -ENODEV;
1911 }
1912
1913 return 0;
c85ee6ca
BS		 1914}
1915
223eaf4b
BS		 1916void
1917gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
1918{
1919 struct nvkm_device *device = gr->base.engine.subdev.device;
1920 struct nvkm_fb *fb = device->fb;
1921
b6838c14 1922 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
223eaf4b
BS		 1923 nvkm_wr32(device, 0x4188a4, 0x00000000);
1924 nvkm_wr32(device, 0x418888, 0x00000000);
1925 nvkm_wr32(device, 0x41888c, 0x00000000);
1926 nvkm_wr32(device, 0x418890, 0x00000000);
1927 nvkm_wr32(device, 0x418894, 0x00000000);
1928 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
1929 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
1930}
1931
c85ee6ca
BS		 1932int
1933gf100_gr_init(struct gf100_gr *gr)
4b223eef 1934{
276836d4 1935 struct nvkm_device *device = gr->base.engine.subdev.device;
bfee3f3d 1936 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
30f4e087
BS		 1937 u32 data[TPC_MAX / 8] = {};
1938 u8 tpcnr[GPC_MAX];
1939 int gpc, tpc, rop;
c85ee6ca 1940 int i;
ebb945a9 1941
223eaf4b 1942 gr->func->init_gpc_mmu(gr);
30f4e087 1943
c85ee6ca 1944 gf100_gr_mmio(gr, gr->func->mmio);
30f4e087 1945
28dca905
BS		 1946 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
1947
bfee3f3d
BS		 1948 memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
1949 for (i = 0, gpc = -1; i < gr->tpc_total; i++) {
30f4e087 1950 do {
bfee3f3d 1951 gpc = (gpc + 1) % gr->gpc_nr;
30f4e087 1952 } while (!tpcnr[gpc]);
bfee3f3d 1953 tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;
30f4e087
BS		 1954
1955 data[i / 8] |= tpc << ((i % 8) * 4);
1956 }
1957
276836d4
BS		 1958 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);
1959 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);
1960 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);
1961 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);
30f4e087 1962
bfee3f3d 1963 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
276836d4 1964 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
5ec3def7 1965 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
276836d4 1966 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
5ec3def7 1967 gr->tpc_total);
276836d4 1968 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
30f4e087
BS		 1969 }
1970
c85ee6ca 1971 if (device->chipset != 0xd7)
276836d4 1972 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
26410c67 1973 else
276836d4 1974 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
bfee3f3d 1975
276836d4 1976 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
bfee3f3d 1977
276836d4 1978 nvkm_wr32(device, 0x400500, 0x00010001);
bfee3f3d 1979
276836d4
BS		 1980 nvkm_wr32(device, 0x400100, 0xffffffff);
1981 nvkm_wr32(device, 0x40013c, 0xffffffff);
bfee3f3d 1982
276836d4
BS		 1983 nvkm_wr32(device, 0x409c24, 0x000f0000);
1984 nvkm_wr32(device, 0x404000, 0xc0000000);
1985 nvkm_wr32(device, 0x404600, 0xc0000000);
1986 nvkm_wr32(device, 0x408030, 0xc0000000);
1987 nvkm_wr32(device, 0x40601c, 0xc0000000);
1988 nvkm_wr32(device, 0x404490, 0xc0000000);
1989 nvkm_wr32(device, 0x406018, 0xc0000000);
1990 nvkm_wr32(device, 0x405840, 0xc0000000);
1991 nvkm_wr32(device, 0x405844, 0x00ffffff);
1992 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
1993 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
bfee3f3d
BS		 1994
1995 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
276836d4
BS		 1996 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1997 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1998 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1999 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
bfee3f3d 2000 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
276836d4
BS		 2001 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2002 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2003 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2004 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2005 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2006 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2007 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
30f4e087 2008 }
276836d4
BS		 2009 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2010 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
30f4e087
BS		 2011 }
2012
bfee3f3d 2013 for (rop = 0; rop < gr->rop_nr; rop++) {
276836d4
BS		 2014 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
2015 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
2016 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2017 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
30f4e087 2018 }
ebb945a9 2019
276836d4
BS		 2020 nvkm_wr32(device, 0x400108, 0xffffffff);
2021 nvkm_wr32(device, 0x400138, 0xffffffff);
2022 nvkm_wr32(device, 0x400118, 0xffffffff);
2023 nvkm_wr32(device, 0x400130, 0xffffffff);
2024 nvkm_wr32(device, 0x40011c, 0xffffffff);
2025 nvkm_wr32(device, 0x400134, 0xffffffff);
30f4e087 2026
276836d4 2027 nvkm_wr32(device, 0x400054, 0x34ce3464);
ac9738bb 2028
bfee3f3d 2029 gf100_gr_zbc_init(gr);
ac9738bb 2030
bfee3f3d 2031 return gf100_gr_init_ctxctl(gr);
30f4e087
BS		 2032}
2033
e3c71eb2 2034#include "fuc/hubgf100.fuc3.h"
30f4e087 2035
e3c71eb2
BS		 2036struct gf100_gr_ucode
2037gf100_gr_fecs_ucode = {
2038 .code.data = gf100_grhub_code,
2039 .code.size = sizeof(gf100_grhub_code),
2040 .data.data = gf100_grhub_data,
2041 .data.size = sizeof(gf100_grhub_data),
30f4e087
BS		 2042};
2043
e3c71eb2 2044#include "fuc/gpcgf100.fuc3.h"
30f4e087 2045
e3c71eb2
BS		 2046struct gf100_gr_ucode
2047gf100_gr_gpccs_ucode = {
2048 .code.data = gf100_grgpc_code,
2049 .code.size = sizeof(gf100_grgpc_code),
2050 .data.data = gf100_grgpc_data,
2051 .data.size = sizeof(gf100_grgpc_data),
30f4e087
BS		 2052};
2053
27f3d6cf
BS		 2054static const struct gf100_gr_func
2055gf100_gr = {
c85ee6ca 2056 .init = gf100_gr_init,
223eaf4b 2057 .init_gpc_mmu = gf100_gr_init_gpc_mmu,
c85ee6ca
BS		 2058 .mmio = gf100_gr_pack_mmio,
2059 .fecs.ucode = &gf100_gr_fecs_ucode,
2060 .gpccs.ucode = &gf100_gr_gpccs_ucode,
64cb5a31 2061 .rops = gf100_gr_rops,
27f3d6cf
BS		 2062 .grctx = &gf100_grctx,
2063 .sclass = {
2064 { -1, -1, FERMI_TWOD_A },
2065 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2066 { -1, -1, FERMI_A, &gf100_fermi },
2067 { -1, -1, FERMI_COMPUTE_A },
2068 {}
2069 }
2070};
2071
c85ee6ca
BS		 2072int
2073gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
2074{
2075 return gf100_gr_new_(&gf100_gr, device, index, pgr);
2076}
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