]>
Commit | Line | Data |
---|---|---|
b8bf04e1 BS |
1 | #ifndef __NV40_GR_H__ |
2 | #define __NV40_GR_H__ | |
27f3d6cf BS |
3 | #define nv40_gr(p) container_of((p), struct nv40_gr, base) |
4 | #include "priv.h" | |
9719047b | 5 | |
27f3d6cf BS |
6 | struct nv40_gr { |
7 | struct nvkm_gr base; | |
8 | u32 size; | |
9 | struct list_head chan; | |
10 | }; | |
11 | ||
c85ee6ca BS |
12 | int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, |
13 | struct nvkm_gr **); | |
14 | int nv40_gr_init(struct nvkm_gr *); | |
15 | void nv40_gr_intr(struct nvkm_gr *); | |
16 | u64 nv40_gr_units(struct nvkm_gr *); | |
17 | ||
27f3d6cf | 18 | #define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object) |
4246b92c | 19 | #include <core/object.h> |
27f3d6cf BS |
20 | |
21 | struct nv40_gr_chan { | |
22 | struct nvkm_object object; | |
23 | struct nv40_gr *gr; | |
24 | struct nvkm_fifo_chan *fifo; | |
25 | u32 inst; | |
26 | struct list_head head; | |
27 | }; | |
c98b8194 | 28 | |
c85ee6ca BS |
29 | int nv40_gr_chan_new(struct nvkm_gr *, struct nvkm_fifo_chan *, |
30 | const struct nvkm_oclass *, struct nvkm_object **); | |
31 | ||
32 | extern const struct nvkm_object_func nv40_gr_object; | |
33 | ||
ebb945a9 BS |
34 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, |
35 | * helpful to determine a number of other hardware features | |
36 | */ | |
37 | static inline int | |
b7a2bc18 | 38 | nv44_gr_class(struct nvkm_device *device) |
ebb945a9 | 39 | { |
ebb945a9 BS |
40 | if ((device->chipset & 0xf0) == 0x60) |
41 | return 1; | |
42 | ||
c85ee6ca | 43 | return !(0x0aaf & (1 << (device->chipset & 0x0f))); |
ebb945a9 BS |
44 | } |
45 | ||
e3c71eb2 BS |
46 | int nv40_grctx_init(struct nvkm_device *, u32 *size); |
47 | void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *); | |
ebb945a9 | 48 | #endif |