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ebb945a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
f84aff4e | 24 | #include "nv50.h" |
ebb945a9 | 25 | |
ebb945a9 | 26 | #include <core/handle.h> |
f84aff4e | 27 | #include <core/namedb.h> |
ebb945a9 | 28 | #include <engine/disp.h> |
f84aff4e | 29 | #include <subdev/bar.h> |
ebb945a9 | 30 | |
f84aff4e | 31 | #include <nvif/event.h> |
f58ddf95 | 32 | #include <nvif/ioctl.h> |
ebb945a9 BS |
33 | |
34 | /******************************************************************************* | |
35 | * software object classes | |
36 | ******************************************************************************/ | |
37 | ||
f84aff4e | 38 | static struct nvkm_oclass |
8700287b | 39 | nv50_sw_sclass[] = { |
61570911 | 40 | { NVIF_IOCTL_NEW_V0_SW_NV50, &nvkm_nvsw_ofuncs }, |
ebb945a9 BS |
41 | {} |
42 | }; | |
43 | ||
44 | /******************************************************************************* | |
45 | * software context | |
46 | ******************************************************************************/ | |
47 | ||
1d7c71a3 | 48 | static int |
8700287b | 49 | nv50_sw_vblsem_release(struct nvkm_notify *notify) |
1d7c71a3 | 50 | { |
8700287b | 51 | struct nv50_sw_chan *chan = |
79ca2770 | 52 | container_of(notify, typeof(*chan), vblank.notify[notify->index]); |
226dcefe | 53 | struct nvkm_sw *sw = (void *)nv_object(chan)->engine; |
01d64afc BS |
54 | struct nvkm_device *device = sw->engine.subdev.device; |
55 | struct nvkm_bar *bar = device->bar; | |
1d7c71a3 | 56 | |
01d64afc BS |
57 | nvkm_wr32(device, 0x001704, chan->vblank.channel); |
58 | nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma); | |
1d7c71a3 BS |
59 | bar->flush(bar); |
60 | ||
226dcefe | 61 | if (nv_device(sw)->chipset == 0x50) { |
01d64afc BS |
62 | nvkm_wr32(device, 0x001570, chan->vblank.offset); |
63 | nvkm_wr32(device, 0x001574, chan->vblank.value); | |
1d7c71a3 | 64 | } else { |
01d64afc BS |
65 | nvkm_wr32(device, 0x060010, chan->vblank.offset); |
66 | nvkm_wr32(device, 0x060014, chan->vblank.value); | |
1d7c71a3 BS |
67 | } |
68 | ||
79ca2770 | 69 | return NVKM_NOTIFY_DROP; |
1d7c71a3 BS |
70 | } |
71 | ||
61570911 BS |
72 | static bool |
73 | nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) | |
74 | { | |
75 | struct nv50_sw_chan *chan = nv50_sw_chan(base); | |
2a7909c0 BS |
76 | struct nvkm_engine *engine = chan->base.base.gpuobj.object.engine; |
77 | struct nvkm_device *device = engine->subdev.device; | |
61570911 BS |
78 | switch (mthd) { |
79 | case 0x018c: chan->vblank.ctxdma = data; return true; | |
80 | case 0x0400: chan->vblank.offset = data; return true; | |
81 | case 0x0404: chan->vblank.value = data; return true; | |
82 | case 0x0408: | |
2a7909c0 | 83 | if (data < device->disp->vblank.index_nr) { |
61570911 BS |
84 | nvkm_notify_get(&chan->vblank.notify[data]); |
85 | return true; | |
86 | } | |
87 | break; | |
88 | default: | |
89 | break; | |
90 | } | |
91 | return false; | |
92 | } | |
93 | ||
94 | static const struct nvkm_sw_chan_func | |
95 | nv50_sw_chan_func = { | |
96 | .mthd = nv50_sw_chan_mthd, | |
97 | }; | |
98 | ||
51cb4b39 | 99 | void |
f84aff4e | 100 | nv50_sw_context_dtor(struct nvkm_object *object) |
51cb4b39 | 101 | { |
8700287b | 102 | struct nv50_sw_chan *chan = (void *)object; |
51cb4b39 BS |
103 | int i; |
104 | ||
79ca2770 BS |
105 | for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) |
106 | nvkm_notify_fini(&chan->vblank.notify[i]); | |
51cb4b39 | 107 | |
898a2b32 | 108 | nvkm_sw_chan_dtor(&chan->base.base.gpuobj.object); |
51cb4b39 BS |
109 | } |
110 | ||
7589563e | 111 | int |
f84aff4e BS |
112 | nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
113 | struct nvkm_oclass *oclass, void *data, u32 size, | |
114 | struct nvkm_object **pobject) | |
ebb945a9 | 115 | { |
2a7909c0 | 116 | struct nvkm_disp *disp = parent->engine->subdev.device->disp; |
8700287b BS |
117 | struct nv50_sw_cclass *pclass = (void *)oclass; |
118 | struct nv50_sw_chan *chan; | |
51cb4b39 | 119 | int ret, i; |
ebb945a9 | 120 | |
61570911 | 121 | ret = nvkm_sw_context_create(pclass->chan, parent, engine, oclass, &chan); |
ebb945a9 BS |
122 | *pobject = nv_object(chan); |
123 | if (ret) | |
124 | return ret; | |
125 | ||
fd166a18 BS |
126 | for (i = 0; disp && i < disp->vblank.index_nr; i++) { |
127 | ret = nvkm_notify_init(NULL, &disp->vblank, pclass->vblank, | |
996f5a08 | 128 | false, |
79ca2770 BS |
129 | &(struct nvif_notify_head_req_v0) { |
130 | .head = i, | |
131 | }, | |
132 | sizeof(struct nvif_notify_head_req_v0), | |
133 | sizeof(struct nvif_notify_head_rep_v0), | |
134 | &chan->vblank.notify[i]); | |
51cb4b39 BS |
135 | if (ret) |
136 | return ret; | |
137 | } | |
138 | ||
ef8d4781 | 139 | chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; |
ebb945a9 BS |
140 | return 0; |
141 | } | |
142 | ||
8700287b BS |
143 | static struct nv50_sw_cclass |
144 | nv50_sw_cclass = { | |
7589563e | 145 | .base.handle = NV_ENGCTX(SW, 0x50), |
f84aff4e | 146 | .base.ofuncs = &(struct nvkm_ofuncs) { |
8700287b BS |
147 | .ctor = nv50_sw_context_ctor, |
148 | .dtor = nv50_sw_context_dtor, | |
f84aff4e BS |
149 | .init = _nvkm_sw_context_init, |
150 | .fini = _nvkm_sw_context_fini, | |
ebb945a9 | 151 | }, |
8700287b | 152 | .vblank = nv50_sw_vblsem_release, |
61570911 | 153 | .chan = &nv50_sw_chan_func, |
ebb945a9 BS |
154 | }; |
155 | ||
156 | /******************************************************************************* | |
157 | * software engine/subdev functions | |
158 | ******************************************************************************/ | |
159 | ||
7589563e | 160 | int |
f84aff4e BS |
161 | nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
162 | struct nvkm_oclass *oclass, void *data, u32 size, | |
163 | struct nvkm_object **pobject) | |
ebb945a9 | 164 | { |
8700287b | 165 | struct nv50_sw_oclass *pclass = (void *)oclass; |
226dcefe | 166 | struct nvkm_sw *sw; |
ebb945a9 BS |
167 | int ret; |
168 | ||
226dcefe BS |
169 | ret = nvkm_sw_create(parent, engine, oclass, &sw); |
170 | *pobject = nv_object(sw); | |
ebb945a9 BS |
171 | if (ret) |
172 | return ret; | |
173 | ||
226dcefe BS |
174 | nv_engine(sw)->cclass = pclass->cclass; |
175 | nv_engine(sw)->sclass = pclass->sclass; | |
176 | nv_subdev(sw)->intr = nv04_sw_intr; | |
ebb945a9 BS |
177 | return 0; |
178 | } | |
179 | ||
f84aff4e | 180 | struct nvkm_oclass * |
8700287b | 181 | nv50_sw_oclass = &(struct nv50_sw_oclass) { |
c46c3ddf | 182 | .base.handle = NV_ENGINE(SW, 0x50), |
f84aff4e | 183 | .base.ofuncs = &(struct nvkm_ofuncs) { |
8700287b | 184 | .ctor = nv50_sw_ctor, |
f84aff4e BS |
185 | .dtor = _nvkm_sw_dtor, |
186 | .init = _nvkm_sw_init, | |
187 | .fini = _nvkm_sw_fini, | |
ebb945a9 | 188 | }, |
8700287b BS |
189 | .cclass = &nv50_sw_cclass.base, |
190 | .sclass = nv50_sw_sclass, | |
c46c3ddf | 191 | }.base; |