[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / bios / dp.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/dp.h>

static u16
nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	struct bit_entry d;

	if (!bit_entry(bios, 'd', &d)) {
		if (d.version == 1 && d.length >= 2) {
			u16 data = nvbios_rd16(bios, d.offset);
			if (data) {
				*ver = nvbios_rd08(bios, data + 0x00);
				switch (*ver) {
				case 0x20:
				case 0x21:
				case 0x30:
				case 0x40:
				case 0x41:
				case 0x42:
					*hdr = nvbios_rd08(bios, data + 0x01);
					*len = nvbios_rd08(bios, data + 0x02);
					*cnt = nvbios_rd08(bios, data + 0x03);
					return data;
				default:
					break;
				}
			}
		}
	}

	return 0x0000;
}

static u16
nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
	if (data && idx < *cnt) {
		u16 outp = nvbios_rd16(bios, data + *hdr + idx * *len);
		switch (*ver * !!outp) {
		case 0x20:
		case 0x21:
		case 0x30:
			*hdr = nvbios_rd08(bios, data + 0x04);
			*len = nvbios_rd08(bios, data + 0x05);
			*cnt = nvbios_rd08(bios, outp + 0x04);
			break;
		case 0x40:
		case 0x41:
		case 0x42:
			*hdr = nvbios_rd08(bios, data + 0x04);
			*cnt = 0;
			*len = 0;
			break;
		default:
			break;
		}
		return outp;
	}
	*ver = 0x00;
	return 0x0000;
}

u16
nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
		   struct nvbios_dpout *info)
{
	u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
	memset(info, 0x00, sizeof(*info));
	if (data && *ver) {
		info->type = nvbios_rd16(bios, data + 0x00);
		info->mask = nvbios_rd16(bios, data + 0x02);
		switch (*ver) {
		case 0x20:
			info->mask |= 0x00c0; /* match any link */
			/* fall-through */
		case 0x21:
		case 0x30:
			info->flags     = nvbios_rd08(bios, data + 0x05);
			info->script[0] = nvbios_rd16(bios, data + 0x06);
			info->script[1] = nvbios_rd16(bios, data + 0x08);
			if (*len >= 0x0c)
				info->lnkcmp    = nvbios_rd16(bios, data + 0x0a);
			if (*len >= 0x0f) {
				info->script[2] = nvbios_rd16(bios, data + 0x0c);
				info->script[3] = nvbios_rd16(bios, data + 0x0e);
			}
			if (*len >= 0x11)
				info->script[4] = nvbios_rd16(bios, data + 0x10);
			break;
		case 0x40:
		case 0x41:
		case 0x42:
			info->flags     = nvbios_rd08(bios, data + 0x04);
			info->script[0] = nvbios_rd16(bios, data + 0x05);
			info->script[1] = nvbios_rd16(bios, data + 0x07);
			info->lnkcmp    = nvbios_rd16(bios, data + 0x09);
			info->script[2] = nvbios_rd16(bios, data + 0x0b);
			info->script[3] = nvbios_rd16(bios, data + 0x0d);
			info->script[4] = nvbios_rd16(bios, data + 0x0f);
			break;
		default:
			data = 0x0000;
			break;
		}
	}
	return data;
}

u16
nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
		   struct nvbios_dpout *info)
{
	u16 data, idx = 0;
	while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
		if (data && info->type == type) {
			if ((info->mask & mask) == mask)
				break;
		}
	}
	return data;
}

static u16
nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	if (*ver >= 0x40) {
		outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
		*hdr = *hdr + (*len * * cnt);
		*len = nvbios_rd08(bios, outp + 0x06);
		*cnt = nvbios_rd08(bios, outp + 0x07) *
		       nvbios_rd08(bios, outp + 0x05);
	}

	if (idx < *cnt)
		return outp + *hdr + (idx * *len);

	return 0x0000;
}

u16
nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
		   struct nvbios_dpcfg *info)
{
	u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len);
	memset(info, 0x00, sizeof(*info));
	if (data) {
		switch (*ver) {
		case 0x20:
		case 0x21:
			info->dc    = nvbios_rd08(bios, data + 0x02);
			info->pe    = nvbios_rd08(bios, data + 0x03);
			info->tx_pu = nvbios_rd08(bios, data + 0x04);
			break;
		case 0x30:
		case 0x40:
		case 0x41:
			info->pc    = nvbios_rd08(bios, data + 0x00);
			info->dc    = nvbios_rd08(bios, data + 0x01);
			info->pe    = nvbios_rd08(bios, data + 0x02);
			info->tx_pu = nvbios_rd08(bios, data + 0x03);
			break;
		case 0x42:
			info->dc    = nvbios_rd08(bios, data + 0x00);
			info->pe    = nvbios_rd08(bios, data + 0x01);
			info->tx_pu = nvbios_rd08(bios, data + 0x02);
			break;
		default:
			data = 0x0000;
			break;
		}
	}
	return data;
}

u16
nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
		   struct nvbios_dpcfg *info)
{
	u8 idx = 0xff;
	u16 data;

	if (*ver >= 0x30) {
		const u8 vsoff[] = { 0, 4, 7, 9 };
		idx = (pc * 10) + vsoff[vs] + pe;
		if (*ver >= 0x40 && *ver <= 0x41 && *hdr >= 0x12)
			idx += nvbios_rd08(bios, outp + 0x11) * 40;
		else
		if (*ver >= 0x42)
			idx += nvbios_rd08(bios, outp + 0x11) * 10;
	} else {
		while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
						  ver, hdr, cnt, len))) {
			if (nvbios_rd08(bios, data + 0x00) == vs &&
			    nvbios_rd08(bios, data + 0x01) == pe)
				break;
		}
	}

	return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info);
}
Commit	Line	Data
cb75d97e BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
d390b480 BS	24	#include <subdev/bios.h>
	25	#include <subdev/bios/bit.h>
	26	#include <subdev/bios/dp.h>
cb75d97e	27
65c78660	28	static u16
d390b480	29	nvbios_dp_table(struct nvkm_bios bios, u8 ver, u8 hdr, u8 cnt, u8 *len)
cb75d97e	30	{
65c78660	31	struct bit_entry d;
cb75d97e	32
65c78660 BS	33	if (!bit_entry(bios, 'd', &d)) {
65c78660 BS	34	if (d.version == 1 && d.length >= 2) {
7f5f518f	35	u16 data = nvbios_rd16(bios, d.offset);
cb75d97e	36	if (data) {
7f5f518f	37	*ver = nvbios_rd08(bios, data + 0x00);
65c78660	38	switch (*ver) {
f60707a6	39	case 0x20:
65c78660 BS	40	case 0x21:
	41	case 0x30:
	42	case 0x40:
f467dc18	43	case 0x41:
79bf9552	44	case 0x42:
7f5f518f BS	45	*hdr = nvbios_rd08(bios, data + 0x01);
	46	*len = nvbios_rd08(bios, data + 0x02);
	47	*cnt = nvbios_rd08(bios, data + 0x03);
65c78660 BS	48	return data;
	49	default:
	50	break;
	51	}
cb75d97e BS	52	}
	53	}
	54	}
	55
	56	return 0x0000;
	57	}
	58
65c78660	59	static u16
d390b480	60	nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx,
65c78660 BS	61	u8 ver, u8 hdr, u8 cnt, u8 len)
	62	{
	63	u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
	64	if (data && idx < *cnt) {
7f5f518f	65	u16 outp = nvbios_rd16(bios, data + hdr + idx *len);
65c78660	66	switch (ver !!outp) {
f60707a6	67	case 0x20:
65c78660 BS	68	case 0x21:
65c78660 BS	69	case 0x30:
7f5f518f BS	70	*hdr = nvbios_rd08(bios, data + 0x04);
	71	*len = nvbios_rd08(bios, data + 0x05);
	72	*cnt = nvbios_rd08(bios, outp + 0x04);
65c78660 BS	73	break;
65c78660 BS	74	case 0x40:
f467dc18	75	case 0x41:
79bf9552	76	case 0x42:
7f5f518f	77	*hdr = nvbios_rd08(bios, data + 0x04);
65c78660 BS	78	*cnt = 0;
	79	*len = 0;
	80	break;
	81	default:
	82	break;
	83	}
	84	return outp;
	85	}
	86	*ver = 0x00;
	87	return 0x0000;
	88	}
	89
cb75d97e	90	u16
d390b480	91	nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
65c78660 BS	92	u8 ver, u8 hdr, u8 cnt, u8 len,
65c78660 BS	93	struct nvbios_dpout *info)
cb75d97e	94	{
65c78660	95	u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
4767fae8	96	memset(info, 0x00, sizeof(*info));
65c78660	97	if (data && *ver) {
7f5f518f BS	98	info->type = nvbios_rd16(bios, data + 0x00);
7f5f518f BS	99	info->mask = nvbios_rd16(bios, data + 0x02);
65c78660	100	switch (*ver) {
f60707a6 BS	101	case 0x20:
	102	info->mask \|= 0x00c0; /* match any link */
	103	/* fall-through */
65c78660 BS	104	case 0x21:
65c78660 BS	105	case 0x30:
7f5f518f BS	106	info->flags = nvbios_rd08(bios, data + 0x05);
	107	info->script[0] = nvbios_rd16(bios, data + 0x06);
	108	info->script[1] = nvbios_rd16(bios, data + 0x08);
f60707a6 BS	109	if (*len >= 0x0c)
f60707a6 BS	110	info->lnkcmp = nvbios_rd16(bios, data + 0x0a);
4767fae8	111	if (*len >= 0x0f) {
7f5f518f BS	112	info->script[2] = nvbios_rd16(bios, data + 0x0c);
7f5f518f BS	113	info->script[3] = nvbios_rd16(bios, data + 0x0e);
4767fae8 BS	114	}
4767fae8 BS	115	if (*len >= 0x11)
7f5f518f	116	info->script[4] = nvbios_rd16(bios, data + 0x10);
65c78660 BS	117	break;
65c78660 BS	118	case 0x40:
f467dc18	119	case 0x41:
79bf9552	120	case 0x42:
7f5f518f BS	121	info->flags = nvbios_rd08(bios, data + 0x04);
	122	info->script[0] = nvbios_rd16(bios, data + 0x05);
	123	info->script[1] = nvbios_rd16(bios, data + 0x07);
	124	info->lnkcmp = nvbios_rd16(bios, data + 0x09);
	125	info->script[2] = nvbios_rd16(bios, data + 0x0b);
	126	info->script[3] = nvbios_rd16(bios, data + 0x0d);
	127	info->script[4] = nvbios_rd16(bios, data + 0x0f);
65c78660 BS	128	break;
	129	default:
	130	data = 0x0000;
	131	break;
	132	}
	133	}
	134	return data;
cb75d97e BS	135	}
	136
	137	u16
d390b480	138	nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask,
65c78660 BS	139	u8 ver, u8 hdr, u8 cnt, u8 len,
65c78660 BS	140	struct nvbios_dpout *info)
cb75d97e	141	{
65c78660 BS	142	u16 data, idx = 0;
	143	while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) \|\| *ver) {
	144	if (data && info->type == type) {
	145	if ((info->mask & mask) == mask)
	146	break;
cb75d97e BS	147	}
cb75d97e BS	148	}
65c78660 BS	149	return data;
	150	}
	151
	152	static u16
d390b480	153	nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
65c78660 BS	154	u8 ver, u8 hdr, u8 cnt, u8 len)
	155	{
	156	if (*ver >= 0x40) {
	157	outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
	158	hdr = hdr + (len * cnt);
7f5f518f BS	159	*len = nvbios_rd08(bios, outp + 0x06);
	160	cnt = nvbios_rd08(bios, outp + 0x07)
	161	nvbios_rd08(bios, outp + 0x05);
65c78660 BS	162	}
	163
	164	if (idx < *cnt)
	165	return outp + hdr + (idx *len);
	166
cb75d97e BS	167	return 0x0000;
cb75d97e BS	168	}
65c78660 BS	169
65c78660 BS	170	u16
d390b480	171	nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
65c78660 BS	172	u8 ver, u8 hdr, u8 cnt, u8 len,
	173	struct nvbios_dpcfg *info)
	174	{
	175	u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len);
7a14bc78	176	memset(info, 0x00, sizeof(*info));
65c78660 BS	177	if (data) {
65c78660 BS	178	switch (*ver) {
f60707a6	179	case 0x20:
65c78660	180	case 0x21:
7f5f518f BS	181	info->dc = nvbios_rd08(bios, data + 0x02);
	182	info->pe = nvbios_rd08(bios, data + 0x03);
	183	info->tx_pu = nvbios_rd08(bios, data + 0x04);
65c78660 BS	184	break;
	185	case 0x30:
	186	case 0x40:
f467dc18	187	case 0x41:
7f5f518f BS	188	info->pc = nvbios_rd08(bios, data + 0x00);
	189	info->dc = nvbios_rd08(bios, data + 0x01);
	190	info->pe = nvbios_rd08(bios, data + 0x02);
	191	info->tx_pu = nvbios_rd08(bios, data + 0x03);
65c78660	192	break;
79bf9552 BS	193	case 0x42:
	194	info->dc = nvbios_rd08(bios, data + 0x00);
	195	info->pe = nvbios_rd08(bios, data + 0x01);
	196	info->tx_pu = nvbios_rd08(bios, data + 0x02);
	197	break;
65c78660 BS	198	default:
	199	data = 0x0000;
	200	break;
	201	}
	202	}
	203	return data;
	204	}
	205
	206	u16
d390b480	207	nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
65c78660 BS	208	u8 ver, u8 hdr, u8 cnt, u8 len,
	209	struct nvbios_dpcfg *info)
	210	{
	211	u8 idx = 0xff;
	212	u16 data;
	213
	214	if (*ver >= 0x30) {
	215	const u8 vsoff[] = { 0, 4, 7, 9 };
7a14bc78	216	idx = (pc * 10) + vsoff[vs] + pe;
79d48dad	217	if (ver >= 0x40 && ver <= 0x41 && *hdr >= 0x12)
7f5f518f	218	idx += nvbios_rd08(bios, outp + 0x11) * 40;
79d48dad BS	219	else
	220	if (*ver >= 0x42)
	221	idx += nvbios_rd08(bios, outp + 0x11) * 10;
65c78660	222	} else {
7a14bc78	223	while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
65c78660	224	ver, hdr, cnt, len))) {
7f5f518f BS	225	if (nvbios_rd08(bios, data + 0x00) == vs &&
7f5f518f BS	226	nvbios_rd08(bios, data + 0x01) == pe)
65c78660	227	break;
65c78660 BS	228	}
	229	}
	230
7a14bc78	231	return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info);
65c78660	232	}