]>
Commit | Line | Data |
---|---|---|
8aceb7de BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
f3867f43 | 24 | #include <subdev/clk.h> |
7632b30e BS |
25 | #include "pll.h" |
26 | ||
70790f4f BS |
27 | #include <subdev/bios.h> |
28 | #include <subdev/bios/pll.h> | |
7c856522 | 29 | #include <subdev/timer.h> |
70790f4f | 30 | |
7632b30e | 31 | struct gf100_clk_info { |
7c856522 BS |
32 | u32 freq; |
33 | u32 ssel; | |
34 | u32 mdiv; | |
35 | u32 dsrc; | |
36 | u32 ddiv; | |
37 | u32 coef; | |
38 | }; | |
39 | ||
3eca809b | 40 | struct gf100_clk { |
7632b30e BS |
41 | struct nvkm_clk base; |
42 | struct gf100_clk_info eng[16]; | |
7c856522 BS |
43 | }; |
44 | ||
3eca809b | 45 | static u32 read_div(struct gf100_clk *, int, u32, u32); |
7c856522 BS |
46 | |
47 | static u32 | |
3eca809b | 48 | read_vco(struct gf100_clk *clk, u32 dsrc) |
7c856522 | 49 | { |
822ad79f BS |
50 | struct nvkm_device *device = clk->base.subdev.device; |
51 | u32 ssrc = nvkm_rd32(device, dsrc); | |
7c856522 | 52 | if (!(ssrc & 0x00000100)) |
3eca809b BS |
53 | return clk->base.read(&clk->base, nv_clk_src_sppll0); |
54 | return clk->base.read(&clk->base, nv_clk_src_sppll1); | |
7c856522 BS |
55 | } |
56 | ||
57 | static u32 | |
3eca809b | 58 | read_pll(struct gf100_clk *clk, u32 pll) |
7c856522 | 59 | { |
822ad79f BS |
60 | struct nvkm_device *device = clk->base.subdev.device; |
61 | u32 ctrl = nvkm_rd32(device, pll + 0x00); | |
62 | u32 coef = nvkm_rd32(device, pll + 0x04); | |
7c856522 BS |
63 | u32 P = (coef & 0x003f0000) >> 16; |
64 | u32 N = (coef & 0x0000ff00) >> 8; | |
65 | u32 M = (coef & 0x000000ff) >> 0; | |
66 | u32 sclk; | |
67 | ||
68 | if (!(ctrl & 0x00000001)) | |
69 | return 0; | |
70 | ||
71 | switch (pll) { | |
72 | case 0x00e800: | |
73 | case 0x00e820: | |
822ad79f | 74 | sclk = device->crystal; |
7c856522 BS |
75 | P = 1; |
76 | break; | |
77 | case 0x132000: | |
3eca809b | 78 | sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc); |
7c856522 BS |
79 | break; |
80 | case 0x132020: | |
3eca809b | 81 | sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref); |
7c856522 BS |
82 | break; |
83 | case 0x137000: | |
84 | case 0x137020: | |
85 | case 0x137040: | |
86 | case 0x1370e0: | |
3eca809b | 87 | sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); |
7c856522 BS |
88 | break; |
89 | default: | |
90 | return 0; | |
91 | } | |
92 | ||
93 | return sclk * N / M / P; | |
94 | } | |
95 | ||
96 | static u32 | |
3eca809b | 97 | read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl) |
7c856522 | 98 | { |
822ad79f BS |
99 | struct nvkm_device *device = clk->base.subdev.device; |
100 | u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4)); | |
101 | u32 sctl = nvkm_rd32(device, dctl + (doff * 4)); | |
7c856522 BS |
102 | |
103 | switch (ssrc & 0x00000003) { | |
104 | case 0: | |
105 | if ((ssrc & 0x00030000) != 0x00030000) | |
822ad79f | 106 | return device->crystal; |
7c856522 BS |
107 | return 108000; |
108 | case 2: | |
109 | return 100000; | |
110 | case 3: | |
111 | if (sctl & 0x80000000) { | |
3eca809b | 112 | u32 sclk = read_vco(clk, dsrc + (doff * 4)); |
7c856522 BS |
113 | u32 sdiv = (sctl & 0x0000003f) + 2; |
114 | return (sclk * 2) / sdiv; | |
115 | } | |
116 | ||
3eca809b | 117 | return read_vco(clk, dsrc + (doff * 4)); |
7c856522 BS |
118 | default: |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
123 | static u32 | |
3eca809b | 124 | read_clk(struct gf100_clk *clk, int idx) |
7c856522 | 125 | { |
822ad79f BS |
126 | struct nvkm_device *device = clk->base.subdev.device; |
127 | u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); | |
128 | u32 ssel = nvkm_rd32(device, 0x137100); | |
7c856522 BS |
129 | u32 sclk, sdiv; |
130 | ||
3eca809b BS |
131 | if (ssel & (1 << idx)) { |
132 | if (idx < 7) | |
133 | sclk = read_pll(clk, 0x137000 + (idx * 0x20)); | |
7c856522 | 134 | else |
3eca809b | 135 | sclk = read_pll(clk, 0x1370e0); |
7c856522 BS |
136 | sdiv = ((sctl & 0x00003f00) >> 8) + 2; |
137 | } else { | |
3eca809b | 138 | sclk = read_div(clk, idx, 0x137160, 0x1371d0); |
7c856522 BS |
139 | sdiv = ((sctl & 0x0000003f) >> 0) + 2; |
140 | } | |
141 | ||
142 | if (sctl & 0x80000000) | |
143 | return (sclk * 2) / sdiv; | |
144 | ||
145 | return sclk; | |
146 | } | |
147 | ||
148 | static int | |
3eca809b | 149 | gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) |
7c856522 | 150 | { |
3eca809b | 151 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
b907649e BS |
152 | struct nvkm_subdev *subdev = &clk->base.subdev; |
153 | struct nvkm_device *device = subdev->device; | |
7c856522 BS |
154 | |
155 | switch (src) { | |
156 | case nv_clk_src_crystal: | |
157 | return device->crystal; | |
158 | case nv_clk_src_href: | |
159 | return 100000; | |
160 | case nv_clk_src_sppll0: | |
3eca809b | 161 | return read_pll(clk, 0x00e800); |
7c856522 | 162 | case nv_clk_src_sppll1: |
3eca809b | 163 | return read_pll(clk, 0x00e820); |
7c856522 BS |
164 | |
165 | case nv_clk_src_mpllsrcref: | |
3eca809b | 166 | return read_div(clk, 0, 0x137320, 0x137330); |
7c856522 | 167 | case nv_clk_src_mpllsrc: |
3eca809b | 168 | return read_pll(clk, 0x132020); |
7c856522 | 169 | case nv_clk_src_mpll: |
3eca809b | 170 | return read_pll(clk, 0x132000); |
7c856522 | 171 | case nv_clk_src_mdiv: |
3eca809b | 172 | return read_div(clk, 0, 0x137300, 0x137310); |
7c856522 | 173 | case nv_clk_src_mem: |
822ad79f | 174 | if (nvkm_rd32(device, 0x1373f0) & 0x00000002) |
3eca809b BS |
175 | return clk->base.read(&clk->base, nv_clk_src_mpll); |
176 | return clk->base.read(&clk->base, nv_clk_src_mdiv); | |
7c856522 BS |
177 | |
178 | case nv_clk_src_gpc: | |
3eca809b | 179 | return read_clk(clk, 0x00); |
7c856522 | 180 | case nv_clk_src_rop: |
3eca809b | 181 | return read_clk(clk, 0x01); |
7c856522 | 182 | case nv_clk_src_hubk07: |
3eca809b | 183 | return read_clk(clk, 0x02); |
7c856522 | 184 | case nv_clk_src_hubk06: |
3eca809b | 185 | return read_clk(clk, 0x07); |
7c856522 | 186 | case nv_clk_src_hubk01: |
3eca809b | 187 | return read_clk(clk, 0x08); |
7c856522 | 188 | case nv_clk_src_copy: |
3eca809b | 189 | return read_clk(clk, 0x09); |
7c856522 | 190 | case nv_clk_src_daemon: |
3eca809b | 191 | return read_clk(clk, 0x0c); |
7c856522 | 192 | case nv_clk_src_vdec: |
3eca809b | 193 | return read_clk(clk, 0x0e); |
7c856522 | 194 | default: |
b907649e | 195 | nvkm_error(subdev, "invalid clock source %d\n", src); |
7c856522 BS |
196 | return -EINVAL; |
197 | } | |
198 | } | |
199 | ||
200 | static u32 | |
3eca809b | 201 | calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) |
7c856522 BS |
202 | { |
203 | u32 div = min((ref * 2) / freq, (u32)65); | |
204 | if (div < 2) | |
205 | div = 2; | |
206 | ||
207 | *ddiv = div - 2; | |
208 | return (ref * 2) / div; | |
209 | } | |
210 | ||
211 | static u32 | |
3eca809b | 212 | calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) |
7c856522 BS |
213 | { |
214 | u32 sclk; | |
215 | ||
216 | /* use one of the fixed frequencies if possible */ | |
217 | *ddiv = 0x00000000; | |
218 | switch (freq) { | |
219 | case 27000: | |
220 | case 108000: | |
221 | *dsrc = 0x00000000; | |
222 | if (freq == 108000) | |
223 | *dsrc |= 0x00030000; | |
224 | return freq; | |
225 | case 100000: | |
226 | *dsrc = 0x00000002; | |
227 | return freq; | |
228 | default: | |
229 | *dsrc = 0x00000003; | |
230 | break; | |
231 | } | |
232 | ||
233 | /* otherwise, calculate the closest divider */ | |
3eca809b BS |
234 | sclk = read_vco(clk, 0x137160 + (idx * 4)); |
235 | if (idx < 7) | |
236 | sclk = calc_div(clk, idx, sclk, freq, ddiv); | |
7c856522 BS |
237 | return sclk; |
238 | } | |
239 | ||
240 | static u32 | |
3eca809b | 241 | calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef) |
7c856522 | 242 | { |
46484438 BS |
243 | struct nvkm_subdev *subdev = &clk->base.subdev; |
244 | struct nvkm_bios *bios = subdev->device->bios; | |
7c856522 BS |
245 | struct nvbios_pll limits; |
246 | int N, M, P, ret; | |
247 | ||
3eca809b | 248 | ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits); |
7c856522 BS |
249 | if (ret) |
250 | return 0; | |
251 | ||
3eca809b | 252 | limits.refclk = read_div(clk, idx, 0x137120, 0x137140); |
7c856522 BS |
253 | if (!limits.refclk) |
254 | return 0; | |
255 | ||
46484438 | 256 | ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); |
7c856522 BS |
257 | if (ret <= 0) |
258 | return 0; | |
259 | ||
260 | *coef = (P << 16) | (N << 8) | M; | |
261 | return ret; | |
262 | } | |
263 | ||
264 | static int | |
3eca809b | 265 | calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) |
7c856522 | 266 | { |
3eca809b | 267 | struct gf100_clk_info *info = &clk->eng[idx]; |
7c856522 BS |
268 | u32 freq = cstate->domain[dom]; |
269 | u32 src0, div0, div1D, div1P = 0; | |
270 | u32 clk0, clk1 = 0; | |
271 | ||
272 | /* invalid clock domain */ | |
273 | if (!freq) | |
274 | return 0; | |
275 | ||
276 | /* first possible path, using only dividers */ | |
3eca809b BS |
277 | clk0 = calc_src(clk, idx, freq, &src0, &div0); |
278 | clk0 = calc_div(clk, idx, clk0, freq, &div1D); | |
7c856522 BS |
279 | |
280 | /* see if we can get any closer using PLLs */ | |
3eca809b BS |
281 | if (clk0 != freq && (0x00004387 & (1 << idx))) { |
282 | if (idx <= 7) | |
283 | clk1 = calc_pll(clk, idx, freq, &info->coef); | |
7c856522 BS |
284 | else |
285 | clk1 = cstate->domain[nv_clk_src_hubk06]; | |
3eca809b | 286 | clk1 = calc_div(clk, idx, clk1, freq, &div1P); |
7c856522 BS |
287 | } |
288 | ||
289 | /* select the method which gets closest to target freq */ | |
290 | if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { | |
291 | info->dsrc = src0; | |
292 | if (div0) { | |
293 | info->ddiv |= 0x80000000; | |
294 | info->ddiv |= div0 << 8; | |
295 | info->ddiv |= div0; | |
296 | } | |
297 | if (div1D) { | |
298 | info->mdiv |= 0x80000000; | |
299 | info->mdiv |= div1D; | |
300 | } | |
301 | info->ssel = info->coef = 0; | |
302 | info->freq = clk0; | |
303 | } else { | |
304 | if (div1P) { | |
305 | info->mdiv |= 0x80000000; | |
306 | info->mdiv |= div1P << 8; | |
307 | } | |
3eca809b | 308 | info->ssel = (1 << idx); |
7c856522 BS |
309 | info->freq = clk1; |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static int | |
3eca809b | 316 | gf100_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) |
7c856522 | 317 | { |
3eca809b | 318 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
7c856522 BS |
319 | int ret; |
320 | ||
3eca809b BS |
321 | if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || |
322 | (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || | |
323 | (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || | |
324 | (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || | |
325 | (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || | |
326 | (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || | |
327 | (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || | |
328 | (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) | |
7c856522 BS |
329 | return ret; |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static void | |
3eca809b | 335 | gf100_clk_prog_0(struct gf100_clk *clk, int idx) |
7c856522 | 336 | { |
3eca809b | 337 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 338 | struct nvkm_device *device = clk->base.subdev.device; |
3eca809b | 339 | if (idx < 7 && !info->ssel) { |
822ad79f BS |
340 | nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv); |
341 | nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); | |
7c856522 BS |
342 | } |
343 | } | |
344 | ||
345 | static void | |
3eca809b | 346 | gf100_clk_prog_1(struct gf100_clk *clk, int idx) |
7c856522 | 347 | { |
822ad79f BS |
348 | struct nvkm_device *device = clk->base.subdev.device; |
349 | nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); | |
6979c630 BS |
350 | nvkm_msec(device, 2000, |
351 | if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) | |
352 | break; | |
353 | ); | |
7c856522 BS |
354 | } |
355 | ||
356 | static void | |
3eca809b | 357 | gf100_clk_prog_2(struct gf100_clk *clk, int idx) |
7c856522 | 358 | { |
3eca809b | 359 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 360 | struct nvkm_device *device = clk->base.subdev.device; |
3eca809b BS |
361 | const u32 addr = 0x137000 + (idx * 0x20); |
362 | if (idx <= 7) { | |
822ad79f BS |
363 | nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); |
364 | nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); | |
7c856522 | 365 | if (info->coef) { |
822ad79f BS |
366 | nvkm_wr32(device, addr + 0x04, info->coef); |
367 | nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); | |
6979c630 BS |
368 | nvkm_msec(device, 2000, |
369 | if (nvkm_rd32(device, addr + 0x00) & 0x00020000) | |
370 | break; | |
371 | ); | |
822ad79f | 372 | nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); |
7c856522 BS |
373 | } |
374 | } | |
375 | } | |
376 | ||
377 | static void | |
3eca809b | 378 | gf100_clk_prog_3(struct gf100_clk *clk, int idx) |
7c856522 | 379 | { |
3eca809b | 380 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f | 381 | struct nvkm_device *device = clk->base.subdev.device; |
7c856522 | 382 | if (info->ssel) { |
822ad79f | 383 | nvkm_mask(device, 0x137100, (1 << idx), info->ssel); |
6979c630 BS |
384 | nvkm_msec(device, 2000, |
385 | u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); | |
386 | if (tmp == info->ssel) | |
387 | break; | |
388 | ); | |
7c856522 BS |
389 | } |
390 | } | |
391 | ||
392 | static void | |
3eca809b | 393 | gf100_clk_prog_4(struct gf100_clk *clk, int idx) |
7c856522 | 394 | { |
3eca809b | 395 | struct gf100_clk_info *info = &clk->eng[idx]; |
822ad79f BS |
396 | struct nvkm_device *device = clk->base.subdev.device; |
397 | nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); | |
7c856522 BS |
398 | } |
399 | ||
400 | static int | |
3eca809b | 401 | gf100_clk_prog(struct nvkm_clk *obj) |
7c856522 | 402 | { |
3eca809b | 403 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
7c856522 | 404 | struct { |
3eca809b | 405 | void (*exec)(struct gf100_clk *, int); |
7c856522 | 406 | } stage[] = { |
7632b30e BS |
407 | { gf100_clk_prog_0 }, /* div programming */ |
408 | { gf100_clk_prog_1 }, /* select div mode */ | |
409 | { gf100_clk_prog_2 }, /* (maybe) program pll */ | |
410 | { gf100_clk_prog_3 }, /* (maybe) select pll mode */ | |
411 | { gf100_clk_prog_4 }, /* final divider */ | |
7c856522 BS |
412 | }; |
413 | int i, j; | |
414 | ||
415 | for (i = 0; i < ARRAY_SIZE(stage); i++) { | |
3eca809b BS |
416 | for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { |
417 | if (!clk->eng[j].freq) | |
7c856522 | 418 | continue; |
3eca809b | 419 | stage[i].exec(clk, j); |
7c856522 BS |
420 | } |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static void | |
3eca809b | 427 | gf100_clk_tidy(struct nvkm_clk *obj) |
7c856522 | 428 | { |
3eca809b BS |
429 | struct gf100_clk *clk = container_of(obj, typeof(*clk), base); |
430 | memset(clk->eng, 0x00, sizeof(clk->eng)); | |
7c856522 BS |
431 | } |
432 | ||
7632b30e BS |
433 | static struct nvkm_domain |
434 | gf100_domain[] = { | |
7c856522 BS |
435 | { nv_clk_src_crystal, 0xff }, |
436 | { nv_clk_src_href , 0xff }, | |
437 | { nv_clk_src_hubk06 , 0x00 }, | |
438 | { nv_clk_src_hubk01 , 0x01 }, | |
439 | { nv_clk_src_copy , 0x02 }, | |
440 | { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, | |
441 | { nv_clk_src_rop , 0x04 }, | |
442 | { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, | |
443 | { nv_clk_src_vdec , 0x06 }, | |
444 | { nv_clk_src_daemon , 0x0a }, | |
445 | { nv_clk_src_hubk07 , 0x0b }, | |
446 | { nv_clk_src_max } | |
8aceb7de BS |
447 | }; |
448 | ||
8aceb7de | 449 | static int |
7632b30e BS |
450 | gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
451 | struct nvkm_oclass *oclass, void *data, u32 size, | |
452 | struct nvkm_object **pobject) | |
8aceb7de | 453 | { |
3eca809b | 454 | struct gf100_clk *clk; |
8aceb7de BS |
455 | int ret; |
456 | ||
7632b30e | 457 | ret = nvkm_clk_create(parent, engine, oclass, gf100_domain, |
3eca809b BS |
458 | NULL, 0, false, &clk); |
459 | *pobject = nv_object(clk); | |
8aceb7de BS |
460 | if (ret) |
461 | return ret; | |
462 | ||
3eca809b BS |
463 | clk->base.read = gf100_clk_read; |
464 | clk->base.calc = gf100_clk_calc; | |
465 | clk->base.prog = gf100_clk_prog; | |
466 | clk->base.tidy = gf100_clk_tidy; | |
8aceb7de BS |
467 | return 0; |
468 | } | |
469 | ||
7632b30e BS |
470 | struct nvkm_oclass |
471 | gf100_clk_oclass = { | |
f3867f43 | 472 | .handle = NV_SUBDEV(CLK, 0xc0), |
7632b30e BS |
473 | .ofuncs = &(struct nvkm_ofuncs) { |
474 | .ctor = gf100_clk_ctor, | |
475 | .dtor = _nvkm_clk_dtor, | |
476 | .init = _nvkm_clk_init, | |
477 | .fini = _nvkm_clk_fini, | |
8aceb7de BS |
478 | }, |
479 | }; |