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1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
cf336014 | 24 | #include "nv50.h" |
88524bc0 | 25 | |
a8c4362b BS |
26 | #include <subdev/bios.h> |
27 | #include <subdev/bios/init.h> | |
28 | #include <subdev/bios/pll.h> | |
29 | #include <subdev/clk/pll.h> | |
30 | ||
4bf23ead | 31 | int |
8ac3f64f | 32 | gf100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) |
88524bc0 | 33 | { |
8ac3f64f BS |
34 | struct nvkm_subdev *subdev = &init->subdev; |
35 | struct nvkm_device *device = subdev->device; | |
88524bc0 BS |
36 | struct nvbios_pll info; |
37 | int N, fN, M, P; | |
38 | int ret; | |
39 | ||
8ac3f64f | 40 | ret = nvbios_pll_parse(device->bios, type, &info); |
88524bc0 BS |
41 | if (ret) |
42 | return ret; | |
43 | ||
8ac3f64f | 44 | ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P); |
88524bc0 BS |
45 | if (ret < 0) |
46 | return ret; | |
47 | ||
48 | switch (info.type) { | |
49 | case PLL_VPLL0: | |
50 | case PLL_VPLL1: | |
51 | case PLL_VPLL2: | |
52 | case PLL_VPLL3: | |
8ac3f64f BS |
53 | nvkm_mask(device, info.reg + 0x0c, 0x00000000, 0x00000100); |
54 | nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); | |
55 | nvkm_wr32(device, info.reg + 0x10, fN << 16); | |
88524bc0 BS |
56 | break; |
57 | default: | |
aa860e4b | 58 | nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq); |
88524bc0 BS |
59 | ret = -EINVAL; |
60 | break; | |
61 | } | |
62 | ||
63 | return ret; | |
64 | } | |
65 | ||
4019aaa2 | 66 | static u64 |
8ac3f64f | 67 | gf100_devinit_disable(struct nvkm_devinit *init) |
4019aaa2 | 68 | { |
8ac3f64f BS |
69 | struct nvkm_device *device = init->subdev.device; |
70 | u32 r022500 = nvkm_rd32(device, 0x022500); | |
4019aaa2 IM |
71 | u64 disable = 0ULL; |
72 | ||
73 | if (r022500 & 0x00000001) | |
68f3f702 | 74 | disable |= (1ULL << NVKM_ENGINE_DISP); |
4019aaa2 IM |
75 | |
76 | if (r022500 & 0x00000002) { | |
68f3f702 BS |
77 | disable |= (1ULL << NVKM_ENGINE_MSPDEC); |
78 | disable |= (1ULL << NVKM_ENGINE_MSPPP); | |
4019aaa2 IM |
79 | } |
80 | ||
81 | if (r022500 & 0x00000004) | |
68f3f702 | 82 | disable |= (1ULL << NVKM_ENGINE_MSVLD); |
4019aaa2 | 83 | if (r022500 & 0x00000008) |
68f3f702 | 84 | disable |= (1ULL << NVKM_ENGINE_MSENC); |
4019aaa2 | 85 | if (r022500 & 0x00000100) |
68f3f702 | 86 | disable |= (1ULL << NVKM_ENGINE_CE0); |
4019aaa2 | 87 | if (r022500 & 0x00000200) |
68f3f702 | 88 | disable |= (1ULL << NVKM_ENGINE_CE1); |
4019aaa2 IM |
89 | |
90 | return disable; | |
91 | } | |
92 | ||
a6a0f67c AC |
93 | void |
94 | gf100_devinit_preinit(struct nvkm_devinit *base) | |
95 | { | |
96 | struct nv50_devinit *init = nv50_devinit(base); | |
97 | struct nvkm_subdev *subdev = &init->base.subdev; | |
98 | struct nvkm_device *device = subdev->device; | |
99 | ||
100 | /* This bit is set by devinit, and flips back to 0 on suspend */ | |
101 | if (!base->post) | |
102 | base->post = ((nvkm_rd32(device, 0x2240c) & BIT(1)) == 0); | |
103 | } | |
104 | ||
151abd44 BS |
105 | static const struct nvkm_devinit_func |
106 | gf100_devinit = { | |
a6a0f67c | 107 | .preinit = gf100_devinit_preinit, |
151abd44 BS |
108 | .init = nv50_devinit_init, |
109 | .post = nv04_devinit_post, | |
110 | .pll_set = gf100_devinit_pll_set, | |
111 | .disable = gf100_devinit_disable, | |
112 | }; | |
113 | ||
4d4d6f75 | 114 | int |
151abd44 BS |
115 | gf100_devinit_new(struct nvkm_device *device, int index, |
116 | struct nvkm_devinit **pinit) | |
88524bc0 | 117 | { |
151abd44 | 118 | return nv50_devinit_new_(&gf100_devinit, device, index, pinit); |
88524bc0 | 119 | } |