[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / fb / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "nv50.h"
#include "ram.h"

#include <core/client.h>
#include <core/enum.h>
#include <engine/fifo.h>

static int
nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram)
{
	struct nv50_fb *fb = nv50_fb(base);
	return fb->func->ram_new(&fb->base, pram);
}

static const struct nvkm_enum vm_dispatch_subclients[] = {
	{ 0x00000000, "GRCTX" },
	{ 0x00000001, "NOTIFY" },
	{ 0x00000002, "QUERY" },
	{ 0x00000003, "COND" },
	{ 0x00000004, "M2M_IN" },
	{ 0x00000005, "M2M_OUT" },
	{ 0x00000006, "M2M_NOTIFY" },
	{}
};

static const struct nvkm_enum vm_ccache_subclients[] = {
	{ 0x00000000, "CB" },
	{ 0x00000001, "TIC" },
	{ 0x00000002, "TSC" },
	{}
};

static const struct nvkm_enum vm_prop_subclients[] = {
	{ 0x00000000, "RT0" },
	{ 0x00000001, "RT1" },
	{ 0x00000002, "RT2" },
	{ 0x00000003, "RT3" },
	{ 0x00000004, "RT4" },
	{ 0x00000005, "RT5" },
	{ 0x00000006, "RT6" },
	{ 0x00000007, "RT7" },
	{ 0x00000008, "ZETA" },
	{ 0x00000009, "LOCAL" },
	{ 0x0000000a, "GLOBAL" },
	{ 0x0000000b, "STACK" },
	{ 0x0000000c, "DST2D" },
	{}
};

static const struct nvkm_enum vm_pfifo_subclients[] = {
	{ 0x00000000, "PUSHBUF" },
	{ 0x00000001, "SEMAPHORE" },
	{}
};

static const struct nvkm_enum vm_bar_subclients[] = {
	{ 0x00000000, "FB" },
	{ 0x00000001, "IN" },
	{}
};

static const struct nvkm_enum vm_client[] = {
	{ 0x00000000, "STRMOUT" },
	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
	{ 0x00000004, "PFIFO_WRITE" },
	{ 0x00000005, "CCACHE", vm_ccache_subclients },
	{ 0x00000006, "PMSPPP" },
	{ 0x00000007, "CLIPID" },
	{ 0x00000008, "PFIFO_READ" },
	{ 0x00000009, "VFETCH" },
	{ 0x0000000a, "TEXTURE" },
	{ 0x0000000b, "PROP", vm_prop_subclients },
	{ 0x0000000c, "PVP" },
	{ 0x0000000d, "PBSP" },
	{ 0x0000000e, "PCRYPT" },
	{ 0x0000000f, "PCOUNTER" },
	{ 0x00000011, "PDAEMON" },
	{}
};

static const struct nvkm_enum vm_engine[] = {
	{ 0x00000000, "PGRAPH" },
	{ 0x00000001, "PVP" },
	{ 0x00000004, "PEEPHOLE" },
	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
	{ 0x00000006, "BAR", vm_bar_subclients },
	{ 0x00000008, "PMSPPP" },
	{ 0x00000008, "PMPEG" },
	{ 0x00000009, "PBSP" },
	{ 0x0000000a, "PCRYPT" },
	{ 0x0000000b, "PCOUNTER" },
	{ 0x0000000c, "SEMAPHORE_BG" },
	{ 0x0000000d, "PCE0" },
	{ 0x0000000e, "PMU" },
	{}
};

static const struct nvkm_enum vm_fault[] = {
	{ 0x00000000, "PT_NOT_PRESENT" },
	{ 0x00000001, "PT_TOO_SHORT" },
	{ 0x00000002, "PAGE_NOT_PRESENT" },
	{ 0x00000003, "PAGE_SYSTEM_ONLY" },
	{ 0x00000004, "PAGE_READ_ONLY" },
	{ 0x00000006, "NULL_DMAOBJ" },
	{ 0x00000007, "WRONG_MEMTYPE" },
	{ 0x0000000b, "VRAM_LIMIT" },
	{ 0x0000000f, "DMAOBJ_LIMIT" },
	{}
};

static void
nv50_fb_intr(struct nvkm_fb *base)
{
	struct nv50_fb *fb = nv50_fb(base);
	struct nvkm_subdev *subdev = &fb->base.subdev;
	struct nvkm_device *device = subdev->device;
	struct nvkm_fifo *fifo = device->fifo;
	struct nvkm_fifo_chan *chan;
	const struct nvkm_enum *en, *re, *cl, *sc;
	u32 trap[6], idx, inst;
	u8 st0, st1, st2, st3;
	unsigned long flags;
	int i;

	idx = nvkm_rd32(device, 0x100c90);
	if (!(idx & 0x80000000))
		return;
	idx &= 0x00ffffff;

	for (i = 0; i < 6; i++) {
		nvkm_wr32(device, 0x100c90, idx | i << 24);
		trap[i] = nvkm_rd32(device, 0x100c94);
	}
	nvkm_wr32(device, 0x100c90, idx | 0x80000000);

	/* decode status bits into something more useful */
	if (device->chipset  < 0xa3 ||
	    device->chipset == 0xaa || device->chipset == 0xac) {
		st0 = (trap[0] & 0x0000000f) >> 0;
		st1 = (trap[0] & 0x000000f0) >> 4;
		st2 = (trap[0] & 0x00000f00) >> 8;
		st3 = (trap[0] & 0x0000f000) >> 12;
	} else {
		st0 = (trap[0] & 0x000000ff) >> 0;
		st1 = (trap[0] & 0x0000ff00) >> 8;
		st2 = (trap[0] & 0x00ff0000) >> 16;
		st3 = (trap[0] & 0xff000000) >> 24;
	}
	inst = ((trap[2] << 16) | trap[1]) << 12;

	en = nvkm_enum_find(vm_engine, st0);
	re = nvkm_enum_find(vm_fault , st1);
	cl = nvkm_enum_find(vm_client, st2);
	if      (cl && cl->data) sc = nvkm_enum_find(cl->data, st3);
	else if (en && en->data) sc = nvkm_enum_find(en->data, st3);
	else                     sc = NULL;

	chan = nvkm_fifo_chan_inst(fifo, inst, &flags);
	nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel %d [%08x %s] "
			   "engine %02x [%s] client %02x [%s] "
			   "subclient %02x [%s] reason %08x [%s]\n",
		   (trap[5] & 0x00000100) ? "read" : "write",
		   trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
		   chan ? chan->chid : -1, inst,
		   chan ? chan->object.client->name : "unknown",
		   st0, en ? en->name : "",
		   st2, cl ? cl->name : "", st3, sc ? sc->name : "",
		   st1, re ? re->name : "");
	nvkm_fifo_chan_put(fifo, flags, &chan);
}

static int
nv50_fb_oneinit(struct nvkm_fb *base)
{
	struct nv50_fb *fb = nv50_fb(base);
	struct nvkm_device *device = fb->base.subdev.device;

	fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
	if (fb->r100c08_page) {
		fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0,
					   PAGE_SIZE, DMA_BIDIRECTIONAL);
		if (dma_mapping_error(device->dev, fb->r100c08))
			return -EFAULT;
	}

	return 0;
}

static void
nv50_fb_init(struct nvkm_fb *base)
{
	struct nv50_fb *fb = nv50_fb(base);
	struct nvkm_device *device = fb->base.subdev.device;

	/* Not a clue what this is exactly.  Without pointing it at a
	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	 * cause IOMMU "read from address 0" errors (rh#561267)
	 */
	nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);

	/* This is needed to get meaningful information from 100c90
	 * on traps. No idea what these values mean exactly. */
	nvkm_wr32(device, 0x100c90, fb->func->trap);
}

static u32
nv50_fb_tags(struct nvkm_fb *base)
{
	struct nv50_fb *fb = nv50_fb(base);
	if (fb->func->tags)
		return fb->func->tags(&fb->base);
	return 0;
}

static void *
nv50_fb_dtor(struct nvkm_fb *base)
{
	struct nv50_fb *fb = nv50_fb(base);
	struct nvkm_device *device = fb->base.subdev.device;

	if (fb->r100c08_page) {
		dma_unmap_page(device->dev, fb->r100c08, PAGE_SIZE,
			       DMA_BIDIRECTIONAL);
		__free_page(fb->r100c08_page);
	}

	return fb;
}

static const struct nvkm_fb_func
nv50_fb_ = {
	.dtor = nv50_fb_dtor,
	.tags = nv50_fb_tags,
	.oneinit = nv50_fb_oneinit,
	.init = nv50_fb_init,
	.intr = nv50_fb_intr,
	.ram_new = nv50_fb_ram_new,
};

int
nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device,
	     int index, struct nvkm_fb **pfb)
{
	struct nv50_fb *fb;

	if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
		return -ENOMEM;
	nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base);
	fb->func = func;
	*pfb = &fb->base;

	return 0;
}

static const struct nv50_fb_func
nv50_fb = {
	.ram_new = nv50_ram_new,
	.tags = nv20_fb_tags,
	.trap = 0x000707ff,
};

int
nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
{
	return nv50_fb_new_(&nv50_fb, device, index, pfb);
}
Commit	Line	Data
861d2107 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
639c308e	24	#include "nv50.h"
d36a99d2	25	#include "ram.h"
861d2107	26
93260d3c	27	#include <core/client.h>
639c308e	28	#include <core/enum.h>
344c2d42	29	#include <engine/fifo.h>
20f63afe	30
03c8952f BS	31	static int
	32	nv50_fb_ram_new(struct nvkm_fb base, struct nvkm_ram *pram)
	33	{
	34	struct nv50_fb *fb = nv50_fb(base);
	35	return fb->func->ram_new(&fb->base, pram);
	36	}
	37
639c308e	38	static const struct nvkm_enum vm_dispatch_subclients[] = {
344c2d42 BS	39	{ 0x00000000, "GRCTX" },
	40	{ 0x00000001, "NOTIFY" },
	41	{ 0x00000002, "QUERY" },
	42	{ 0x00000003, "COND" },
	43	{ 0x00000004, "M2M_IN" },
	44	{ 0x00000005, "M2M_OUT" },
	45	{ 0x00000006, "M2M_NOTIFY" },
312d1d5f BS	46	{}
	47	};
	48
639c308e	49	static const struct nvkm_enum vm_ccache_subclients[] = {
344c2d42 BS	50	{ 0x00000000, "CB" },
	51	{ 0x00000001, "TIC" },
	52	{ 0x00000002, "TSC" },
312d1d5f BS	53	{}
	54	};
	55
639c308e	56	static const struct nvkm_enum vm_prop_subclients[] = {
344c2d42 BS	57	{ 0x00000000, "RT0" },
	58	{ 0x00000001, "RT1" },
	59	{ 0x00000002, "RT2" },
	60	{ 0x00000003, "RT3" },
	61	{ 0x00000004, "RT4" },
	62	{ 0x00000005, "RT5" },
	63	{ 0x00000006, "RT6" },
	64	{ 0x00000007, "RT7" },
	65	{ 0x00000008, "ZETA" },
	66	{ 0x00000009, "LOCAL" },
	67	{ 0x0000000a, "GLOBAL" },
	68	{ 0x0000000b, "STACK" },
	69	{ 0x0000000c, "DST2D" },
312d1d5f BS	70	{}
	71	};
	72
639c308e	73	static const struct nvkm_enum vm_pfifo_subclients[] = {
344c2d42 BS	74	{ 0x00000000, "PUSHBUF" },
344c2d42 BS	75	{ 0x00000001, "SEMAPHORE" },
312d1d5f BS	76	{}
	77	};
	78
639c308e	79	static const struct nvkm_enum vm_bar_subclients[] = {
344c2d42 BS	80	{ 0x00000000, "FB" },
344c2d42 BS	81	{ 0x00000001, "IN" },
312d1d5f BS	82	{}
	83	};
	84
639c308e	85	static const struct nvkm_enum vm_client[] = {
344c2d42	86	{ 0x00000000, "STRMOUT" },
312d1d5f	87	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
344c2d42	88	{ 0x00000004, "PFIFO_WRITE" },
312d1d5f	89	{ 0x00000005, "CCACHE", vm_ccache_subclients },
344c2d42 BS	90	{ 0x00000006, "PMSPPP" },
	91	{ 0x00000007, "CLIPID" },
	92	{ 0x00000008, "PFIFO_READ" },
	93	{ 0x00000009, "VFETCH" },
	94	{ 0x0000000a, "TEXTURE" },
312d1d5f	95	{ 0x0000000b, "PROP", vm_prop_subclients },
344c2d42 BS	96	{ 0x0000000c, "PVP" },
	97	{ 0x0000000d, "PBSP" },
	98	{ 0x0000000e, "PCRYPT" },
	99	{ 0x0000000f, "PCOUNTER" },
	100	{ 0x00000011, "PDAEMON" },
312d1d5f BS	101	{}
	102	};
	103
639c308e	104	static const struct nvkm_enum vm_engine[] = {
344c2d42 BS	105	{ 0x00000000, "PGRAPH" },
	106	{ 0x00000001, "PVP" },
	107	{ 0x00000004, "PEEPHOLE" },
	108	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
312d1d5f	109	{ 0x00000006, "BAR", vm_bar_subclients },
344c2d42 BS	110	{ 0x00000008, "PMSPPP" },
	111	{ 0x00000008, "PMPEG" },
	112	{ 0x00000009, "PBSP" },
	113	{ 0x0000000a, "PCRYPT" },
	114	{ 0x0000000b, "PCOUNTER" },
	115	{ 0x0000000c, "SEMAPHORE_BG" },
	116	{ 0x0000000d, "PCE0" },
bac34ed6	117	{ 0x0000000e, "PMU" },
312d1d5f BS	118	{}
	119	};
	120
639c308e	121	static const struct nvkm_enum vm_fault[] = {
344c2d42 BS	122	{ 0x00000000, "PT_NOT_PRESENT" },
	123	{ 0x00000001, "PT_TOO_SHORT" },
	124	{ 0x00000002, "PAGE_NOT_PRESENT" },
	125	{ 0x00000003, "PAGE_SYSTEM_ONLY" },
	126	{ 0x00000004, "PAGE_READ_ONLY" },
	127	{ 0x00000006, "NULL_DMAOBJ" },
	128	{ 0x00000007, "WRONG_MEMTYPE" },
	129	{ 0x0000000b, "VRAM_LIMIT" },
	130	{ 0x0000000f, "DMAOBJ_LIMIT" },
312d1d5f BS	131	{}
	132	};
	133
874309a5	134	static void
03c8952f	135	nv50_fb_intr(struct nvkm_fb *base)
d96773e7	136	{
03c8952f BS	137	struct nv50_fb *fb = nv50_fb(base);
	138	struct nvkm_subdev *subdev = &fb->base.subdev;
	139	struct nvkm_device *device = subdev->device;
344c2d42 BS	140	struct nvkm_fifo *fifo = device->fifo;
344c2d42 BS	141	struct nvkm_fifo_chan *chan;
3ecd329b	142	const struct nvkm_enum en, re, cl, sc;
344c2d42	143	u32 trap[6], idx, inst;
312d1d5f	144	u8 st0, st1, st2, st3;
344c2d42	145	unsigned long flags;
861d2107	146	int i;
d96773e7	147
6758745b	148	idx = nvkm_rd32(device, 0x100c90);
d96773e7 BS	149	if (!(idx & 0x80000000))
	150	return;
	151	idx &= 0x00ffffff;
	152
	153	for (i = 0; i < 6; i++) {
6758745b BS	154	nvkm_wr32(device, 0x100c90, idx \| i << 24);
6758745b BS	155	trap[i] = nvkm_rd32(device, 0x100c94);
d96773e7	156	}
6758745b	157	nvkm_wr32(device, 0x100c90, idx \| 0x80000000);
d96773e7	158
312d1d5f	159	/* decode status bits into something more useful */
861d2107 BS	160	if (device->chipset < 0xa3 \|\|
861d2107 BS	161	device->chipset == 0xaa \|\| device->chipset == 0xac) {
312d1d5f BS	162	st0 = (trap[0] & 0x0000000f) >> 0;
	163	st1 = (trap[0] & 0x000000f0) >> 4;
	164	st2 = (trap[0] & 0x00000f00) >> 8;
	165	st3 = (trap[0] & 0x0000f000) >> 12;
	166	} else {
	167	st0 = (trap[0] & 0x000000ff) >> 0;
	168	st1 = (trap[0] & 0x0000ff00) >> 8;
	169	st2 = (trap[0] & 0x00ff0000) >> 16;
	170	st3 = (trap[0] & 0xff000000) >> 24;
	171	}
344c2d42	172	inst = ((trap[2] << 16) \| trap[1]) << 12;
312d1d5f	173
639c308e	174	en = nvkm_enum_find(vm_engine, st0);
3ecd329b	175	re = nvkm_enum_find(vm_fault , st1);
639c308e	176	cl = nvkm_enum_find(vm_client, st2);
3ecd329b BS	177	if (cl && cl->data) sc = nvkm_enum_find(cl->data, st3);
	178	else if (en && en->data) sc = nvkm_enum_find(en->data, st3);
	179	else sc = NULL;
312d1d5f	180
344c2d42	181	chan = nvkm_fifo_chan_inst(fifo, inst, &flags);
8f0649b5 BS	182	nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel %d [%08x %s] "
8f0649b5 BS	183	"engine %02x [%s] client %02x [%s] "
3ecd329b BS	184	"subclient %02x [%s] reason %08x [%s]\n",
3ecd329b BS	185	(trap[5] & 0x00000100) ? "read" : "write",
8f0649b5 BS	186	trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
	187	chan ? chan->chid : -1, inst,
	188	chan ? chan->object.client->name : "unknown",
	189	st0, en ? en->name : "",
3ecd329b BS	190	st2, cl ? cl->name : "", st3, sc ? sc->name : "",
3ecd329b BS	191	st1, re ? re->name : "");
344c2d42	192	nvkm_fifo_chan_put(fifo, flags, &chan);
d96773e7	193	}
874309a5	194
2ecf7c43 AB	195	static int
	196	nv50_fb_oneinit(struct nvkm_fb *base)
	197	{
	198	struct nv50_fb *fb = nv50_fb(base);
	199	struct nvkm_device *device = fb->base.subdev.device;
	200
	201	fb->r100c08_page = alloc_page(GFP_KERNEL \| __GFP_ZERO);
	202	if (fb->r100c08_page) {
	203	fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0,
	204	PAGE_SIZE, DMA_BIDIRECTIONAL);
	205	if (dma_mapping_error(device->dev, fb->r100c08))
	206	return -EFAULT;
	207	}
	208
	209	return 0;
	210	}
	211
03c8952f BS	212	static void
03c8952f BS	213	nv50_fb_init(struct nvkm_fb *base)
874309a5	214	{
03c8952f BS	215	struct nv50_fb *fb = nv50_fb(base);
03c8952f BS	216	struct nvkm_device *device = fb->base.subdev.device;
874309a5	217
03c8952f BS	218	/* Not a clue what this is exactly. Without pointing it at a
	219	* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	220	* cause IOMMU "read from address 0" errors (rh#561267)
	221	*/
	222	nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);
874309a5	223
03c8952f BS	224	/* This is needed to get meaningful information from 100c90
	225	* on traps. No idea what these values mean exactly. */
	226	nvkm_wr32(device, 0x100c90, fb->func->trap);
874309a5 BS	227	}
874309a5 BS	228
af793b8c BS	229	static u32
	230	nv50_fb_tags(struct nvkm_fb *base)
	231	{
	232	struct nv50_fb *fb = nv50_fb(base);
	233	if (fb->func->tags)
	234	return fb->func->tags(&fb->base);
	235	return 0;
	236	}
	237
03c8952f BS	238	static void *
03c8952f BS	239	nv50_fb_dtor(struct nvkm_fb *base)
874309a5	240	{
03c8952f BS	241	struct nv50_fb *fb = nv50_fb(base);
03c8952f BS	242	struct nvkm_device *device = fb->base.subdev.device;
874309a5	243
b1e4553c	244	if (fb->r100c08_page) {
26c9e8ef	245	dma_unmap_page(device->dev, fb->r100c08, PAGE_SIZE,
fd1496a0	246	DMA_BIDIRECTIONAL);
b1e4553c	247	__free_page(fb->r100c08_page);
874309a5 BS	248	}
874309a5 BS	249
03c8952f	250	return fb;
874309a5 BS	251	}
874309a5 BS	252
03c8952f BS	253	static const struct nvkm_fb_func
	254	nv50_fb_ = {
	255	.dtor = nv50_fb_dtor,
af793b8c	256	.tags = nv50_fb_tags,
2ecf7c43	257	.oneinit = nv50_fb_oneinit,
03c8952f BS	258	.init = nv50_fb_init,
	259	.intr = nv50_fb_intr,
	260	.ram_new = nv50_fb_ram_new,
03c8952f BS	261	};
03c8952f BS	262
9ca3037e	263	int
03c8952f BS	264	nv50_fb_new_(const struct nv50_fb_func func, struct nvkm_device device,
03c8952f BS	265	int index, struct nvkm_fb **pfb)
874309a5	266	{
03c8952f	267	struct nv50_fb *fb;
874309a5	268
03c8952f BS	269	if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
	270	return -ENOMEM;
	271	nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base);
	272	fb->func = func;
	273	*pfb = &fb->base;
874309a5	274
874309a5 BS	275	return 0;
	276	}
	277
03c8952f BS	278	static const struct nv50_fb_func
	279	nv50_fb = {
	280	.ram_new = nv50_ram_new,
af793b8c	281	.tags = nv20_fb_tags,
9ca3037e	282	.trap = 0x000707ff,
03c8952f BS	283	};
	284
	285	int
	286	nv50_fb_new(struct nvkm_device device, int index, struct nvkm_fb *pfb)
	287	{
	288	return nv50_fb_new_(&nv50_fb, device, index, pfb);
	289	}